Hi,
I am looking for a DAC with inbuilt EEPROM / flash to retain DAC configuration when powered up. I need output voltage upto 15V. Please suggest a suitable Part number.
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Regards,
Ramakrishna D C
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Looking for DAC with EEPROM / Flash
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Questions about the AD734 data sheet
My customer asked me a question.
"Does the arrow part in Figure 34 use technology I do not know?"
![Figure34 in Data sheet Rev.E.]()
I think this is a voltage follower.
This is just a mistake, is not it?
Best regards
"Does the arrow part in Figure 34 use technology I do not know?"
I think this is a voltage follower.
This is just a mistake, is not it?
Best regards
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ADRF6820 and ADRF6720 reference clock
Could you please suggest an ADI device to provide the PLL reference signal for the ADRF6820 demodulator and ADRF6720 modulator?
Thanks
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how to link cces with sigmastudio? and how to generate .ldr file
Hello everybody,
I have a card ADSP-21489 and I wanted the link with sigmastudio, but the problem is that I can not do.
I saw the documents concerning the generation of the file .ldr but I did not understand well. then if there is anyone who can guide me in a simple way I will be grateful to him.
I use SigmaStudio 4.1 and cces 2.8.0.
best regards
Amine
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ADXL362 Self Test Limits
Hi,
I have attached the self test limit of each axis for different supply voltages at +/-2g and +/-8g ranges.
Is my understanding correct?
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For the AD7176-2, can the SYNC input be used for sample timing?
We are using the AD7176-2 to collect a sequence of samples but we want an external microprocessor to time the sampling. Sample rate will be in the 4 kHz to 5 kHz range but the sample timing needs to be coordinated with stepper motor control and rotating mechanical parts -- e.g., we want N samples for every rotation. Can we use the AD7176-2 SYNC input to time sampling with the AD7176-2 in single cycle mode? If the SYNC is toggled at around 5 kHz, what settings should be used in the FILTCONx register? (Output Data Rate = 5000 or 10000? Filter Type = Sinc5 to reduce settling time?) Any advice you can provide would be appreciated.
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For the AD7176-2, can the SYNC input be used for sample timing?
We are using the AD7176-2 to collect a sequence of samples but we want an external microprocessor to time the sampling. Sample rate will be in the 4 kHz to 5 kHz range but the sample timing needs to be coordinated with stepper motor control and rotating mechanical parts -- e.g., we want N samples for every rotation. Can we use the AD7176-2 SYNC input to time sampling with the AD7176-2 in single cycle mode? If the SYNC is toggled at around 5 kHz, what settings should be used in the FILTCONx register? (Output Data Rate = 5000 or 10000? Filter Type = Sinc5 to reduce settling time?) Any advice you can provide would be appreciated.
https://ez.analog.com/thread/108708-for-the-ad7176-2-can-the-sync-input-be-used-for-sample-timing
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Zedboard ADAU1761 audio playing not working (changed with three adau1761 chips )
I have been trying to verify audio capture and playback functionality (using ADAU1761 codec and NOT HDMI) for the past few days.
So far I could get the board to play audio files and audio capture on zedboard,it works well.
But I need to add 2 ADAU1761 chips, a total of three ADAU1761 chips. When I use 3 chips, there is no sound playing with aplay commond. Thanks for taking time to read. Any help will be highly appreciated.
The pl device tree is as follows：
/ {
amba_pl: amba_pl {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges ;
axi_i2s_adi_0: axi_i2s_adi@43c00000 {
compatible = "xlnx,axi-i2s-adi-1.0";
reg = <0x43c00000 0x10000>;
};
axi_i2s_adi_1: axi_i2s_adi@43c10000 {
compatible = "xlnx,axi-i2s-adi-1.0";
reg = <0x43c10000 0x10000>;
};
axi_i2s_adi_2: axi_i2s_adi@43c20000 {
compatible = "xlnx,axi-i2s-adi-1.0";
reg = <0x43c20000 0x10000>;
};
axi_iic_0: i2c@41600000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "xlnx,xps-iic-2.00.a";
interrupt-parent = <&intc>;
interrupts = <0 29 4>;
reg = <0x41600000 0x10000>;
adau1761_0: adau1761_0@3b {
compatible = "adi,adau1761";
reg = <0x3b>;
};
};
axi_iic_1: i2c@41610000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "xlnx,xps-iic-2.00.a";
interrupt-parent = <&intc>;
interrupts = <0 30 4>;
reg = <0x41610000 0x10000>;
adau1761_1: adau1761_1@3b {
compatible = "adi,adau1761";
reg = <0x3b>;
};
};
axi_iic_2: i2c@41620000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "xlnx,xps-iic-2.00.a";
interrupt-parent = <&intc>;
interrupts = <0 31 4>;
reg = <0x41620000 0x10000>;
adau1761_2: adau1761_2@3b {
compatible = "adi,adau1761";
reg = <0x3b>;
};
};
audio_clock: audio_clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <12288000>;
};
axi_i2s_0: axi-i2s@0x43c00000 {
compatible = "adi,axi-i2s-1.00.a";
reg = <0x43c00000 0x1000>;
dmas = <&dmac_s 0 &dmac_s 1>;
dma-names = "tx", "rx";
clocks = <&clkc 15>, <&audio_clock>;
clock-names = "axi", "ref";
};
axi_i2s_1: axi-i2s@0x43c10000 {
compatible = "adi,axi-i2s-1.00.a";
reg = <0x43c10000 0x1000>;
dmas = <&dmac_s 2>;
dma-names = "rx";
clocks = <&clkc 15>, <&audio_clock>;
clock-names = "axi", "ref";
};
axi_i2s_2: axi-i2s@0x43c20000 {
compatible = "adi,axi-i2s-1.00.a";
reg = <0x43c20000 0x1000>;
dmas = <&dmac_s 3>;
dma-names = "rx";
clocks = <&clkc 15>, <&audio_clock>;
clock-names = "axi", "ref";
};
zed_sound_0: zed_sound_0 {
compatible = "digilent,zed-sound";
audio-codec = <&adau1761_0>;
cpu-dai = <&axi_i2s_0>;
};
zed_sound_1: zed_sound_1 {
compatible = "digilent,zed-sound";
audio-codec = <&adau1761_1>;
cpu-dai = <&axi_i2s_1>;
};
zed_sound_2: zed_sound_2 {
compatible = "digilent,zed-sound";
audio-codec = <&adau1761_2>;
cpu-dai = <&axi_i2s_2>;
};
};
};
The loading record is as follows:
ALSA device list:
#0: ZED ADAU1761
#1: ZED ADAU1761
#2: ZED ADAU1761
root@3adau1761_project:/# aplay -l
**** List of PLAYBACK Hardware Devices ****
card 0: ADAU1761 [ZED ADAU1761], device 0: adau1761 adau-hifi-0 []
Subdevices: 1/1
Subdevice #0: subdevice #0
card 1: ADAU1761_1 [ZED ADAU1761], device 0: adau1761 adau-hifi-0 []
Subdevices: 1/1
Subdevice #0: subdevice #0
card 2: ADAU1761_2 [ZED ADAU1761], device 0: adau1761 adau-hifi-0 []
Subdevices: 1/1
Subdevice #0: subdevice #0
I configure the card 0 with adau1761.state file:
alsactl restore -c 0 -f adau1761.state
Then I use aplay to play the file of Front_Center.wav with command(aplay Front_Center.wav) , it doesn't have a sound.
root@3adau1761_project:/# aplay Front_Center.wav
Playing WAVE 'Front_Center.wav' : Signed 16 bit Little Endian, Rate 48000 Hz, Mono
But I just load a single adau1761 chip driver, the playback and recording are normal.
Any help will be highly appreciated.
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question about IIO Oscilloscope
Hello,
I am using ZC706 with fmcomms3. I followed Zynq & Altera SoC Quick Start Guide to boot the board, and I saw application IIO Scope tool running. There are 4 files in SD card to boot the board: BOOT.BIN, bootgen_sysfiles, devicetree.dtb, and uImage.
Has the source code of IIO Oscilloscope been compiled into one of these 4 files? So that the IIO Scope tool can be running once the board start.Is BOOT.bin only composed of fsbl.elf, system_top.bit, and uboot.elf?
Thanks
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HMC797APM5E Amplifier OIP2 & OIP3 data from 0.5 to 2GHz
We are planning to use your HMC797APM5E amplifier in our wide-band circuit from 0.5 to 18Ghz.
whereas OIP2 & OIP3 data is not available in datasheet from 0.5 to 2GHz.
Please provide the same to check and proceed further.
Please provide above data for 350mA & 400mA Idd current values.
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calibration in hopping mode
we understand from the device literature that adrv9008-1/2 support fast frequency hopping. Please indicate if if the chip will be performing calibrations whenever the frequency is changed.If so, how much time it takes.
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Looking for DAC with EEPROM / Flash
Hi,
I am looking for a DAC with inbuilt EEPROM / flash to retain DAC configuration when powered up. I need output voltage upto 15V. Please suggest a suitable Part number.
--
Regards,
Ramakrishna D C
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Schema connection DAC AD7538
I use DAC AD7538.
Where is pluged blocking capacitor?
What type capacitor (aluminium electrolytic, tantalum, ceramic) is needed?
What is nominal voltage capacitor?
Should is use ferrite bead?
Should is use choke?
Temperature work DAC maximum 55 grade. Current LEAKAGE influences on accuracy
with 75 grade. It is sufficiently attached Vss to grond?
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HMC960LP4E output characteristics
The HMC960LP4E's input impedance can be set to differential 100 or 400 Ohms. But how about the output impedance? In the data sheet, it states:
- The full scale output changes with load, why the span cut a half when the load is 100 Ohms? Does this imply HMC960 is not low output impedance, but has fixed output impedance?
- The 'Output Voltage Range' means the each single end output voltage range, right?
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AD7761 imporve Synchronisation speed
Hey everyone,
I've got three AD7761's in a daisy chained configuration. I've followed the datasheet to the letter when designing the circuit and it works perfectly although the synchronization is slower than ideal.
Currently my routine after powering them up is the following:
I apply 2 reset pulse followed by 2 start pulses.
In between each transition from high to low or vice versa I have a 100 millisecond delay just as to not apply the pulses too fast.
After this I activate all the channels by making the standby pins low. At this point the output activates, but I can clearly see that its not synced yet. At this point it runs unsynced for quite a few samples and then syncs up and works perfectly.
Ideally I'd like to have the ADC's synced up when they start outputting data. Is there anything I can do to have them sync up properly before outputting data?
Thanks in advance for any help!
I know it is possible because I had old code that I can't seem to find anymore that initialized them in a way that when I activated the channels, they were completely in sync.
If any more info is required please let me know!
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Offset calibration of AD7768-4
The AD7768-4 offers multiplexing a "zero-scale [...] voltage close to 0V". In my understanding this can be used for calibration (by reading the offset of the "shorted" input and applying a corresponding value to the OFFSET REGISTERS). Is this assumption correct?
My problem is that I don't seem to get the multiplexer working correctly. I set all bits in the diagnostic receive select register for the channel and then write the Diagnostic Mux Control register according to the data sheet (0b101). Data is applied correctly, however, there seems to be no effect at all - the adc output data is still not nulled, e.g. I still see the sine input I feed to the inputs.
What am I missing here?
Additionally: By using full scale and full negative scale muxed voltages, could I calibrate the gain?
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How to acknowledge interrupts on AD9371?
In the documentation, page 226/360, I read:
"Note that the phase-locked loop (PLL) unlock bits are not sticky. These bits follow the current status of the PLLs. If the PLL relocks, the status bit clears as well."
I understand for the PLL unlock bits, but I suppose it means also that the other bits are sticky. How can one acknowledge the other bits?
Currently bit 5 (JESD204 deframer interrupt occurred) is set, which is consistent with the DeframerStatus where bit 6 (This bit indicates that the IRQ interrupt was asserted). How to acknoledge?
Réf. UG-992, AD9371/AD9375 System Development User Guide, Rev B.
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Port Linux Run-Time SHARC Loader on the ADSP-SC57x
Hello,
I'm porting Linux Run-Time loader on ADSP-SC573.
EE-399 - https://github.com/analogdevicesinc/runtime-sharc-loader
I'm using ADZS-SC573-EZ-BRD
Target OS -> Linux Addins for CCES(1.2.0)
I need the address in the bootrom that idles SHARC (in loader.c) for SC573
This is for SC589
/* location of bootrom that loops idle */
#define SHARC_LOOP_IDLE 0x5000a6
What is the IDLE address for SC573?
Georgi
Design and Programming Expert
AP-Electronics
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ADRv9008-1 - get current LO divider via API?
Hello.
Is there an API call to get VCO frequency, or the raw RF VCO frequency?
For instance, when I am tuned to 1GHz, the VCO will be running at 8GHz with a divider of 8. As far as I can tell the API only lets me know that I am tuned to 1GHz via TALISE_getRFPllFrequency().
Table 36 in your used guide shows the dividers that are used for a given tune frequency, but I'm not sure what happens at the crossing between the last Upper limit and the next Lower limit. For instance, if tuned to 1500MHz, is the VCO running at 12GHz or 6GHz?
Thanks for the help.
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AD9208-3000EBZ with the ADS7-V2 2X DDC Question
Hello,
I am trying to capture data using the AD9208-3000EBZ with the ADS7-V2. Currently I have 3 GHz going into J201 at 10 dBm, and 3.3 GHz going into J101 at -20 dBm on the AD9208-3000EBZ. On the ADS7-V2 I have a 375 MHz signal going in at 10 dBm.
I have the following configured in initial configuration of the ACE software:
Clock Input: 3 GHz
Chip Operating Mode: DDC0 On...
DDC0 Dec Select: HB1 Complex...
L = 4, M = 1, F = 2, N' = 16...
What I want to do is get a 2x DDC going, if possible, with an input sampling frequency of 3 GHz into J201, and a swept input frequency going into J101 from 2.95 Ghz to 3.65 GHz.
I have attached some screenshots from the GUI if that helps. Thanks!
Additional side question:
Under the AD9208 Analysis window in the Capture Tab there is a Resolution Setting (in the General settings drop down menu). What does this resolution adjust both in the GUI and the hardware?
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