Hello,

I'm working with AD9172-EBZ and ADS7v2.

I'm trying to generate a sine thanks to NCOs.

My config is the following :

• JESD mode 2
• data rate = 125 MHz
• DAC clock = 3 GHz (PLL disabled)
• Subclass 1.

I program it with ACE, then I load DC thanks to DPG downloader. It synchronized well and I even have desired outputs.

However, I realised that the subclass selected in DPG downloader is 0 instead of 1.

So I changed it and now there is no output anymore though all is still synchronized.

I first thought it was a bug in the software, but when I check the DAC registers, the received JESD parameters show that subclass used by the FPGA is correspond to the one of DPG downloader.

Could someone help me understand what is the problem?

Thanks in advance,

LCr

0x2E  Output  Open  Open  Open  Open  Open  Open  Open  0 = ADC A  ADC A = 0x00  Assigns an ADC to an

           assign                                                                             1 = ADC B  ADC B = 0x01   output channel

           (local)                                                                               (local)

In the above register 0x2E it says that it is written to either or both channels (local) depending on register 0x05.

The default column makes me think that ch A is set to A = 0x00 and ch B is set to B = 0x01 on power reset. Is that correct?

So if I was to re-write defaults to both, is the following correct?

write_spi(0x05, 0x01); //select ch A

write_spi(0x2E, 0x00); //set A to ch A

write_spi(0x05, 0x02); //select ch B

write_spi(0x2E, 0x01); //set B to ch B

Or am I complicating things?

I just want to make sure the default values are in all registers before I consider ADC fully operational.

Please advise.

Thanks!

Dear Engineers,

    When I used the AD8232.cir  file downloaded from the official website to perform Pspice simulation, although I have added the .LIB library in Configuration Files as shown in Figure 1, there are always error prompts, "ERROR(ORPSIM-15108): Subcircuit AD8232 used by X_U1 is undefined", as shown in Figure 2, I hope you can help me, thank you very much . 

                                                                                   Fig. 1

                                                                               Fig. 2

                                                                                              Sincerely

                                                                                               Li Zeyou

I've got an ADA2200 which should self boot from a connected EEPROM, loading the filter settings and the clock configuration.

I've connected the RST pin to VDD and the BOOT pin to GND. As shown in figure 29 of the datasheet.

The problem is the following: When I power-on the ADA2200 it doesn't load the proper settings from the EEPROM.

I need to bring the BOOT pin high and then low again to have the ADA2200 acting properly as it is configured in the EEPROM.

- Is that the correct behaviour?

- Could it be that the Checksum isn't calculate properly?

Thank you for your help.

Hello, I have been using the Pluto SDR with MATLAB  (simulink). I want that in one simulation the device will transmit for a few seconds. after than it will stop the transmission and then the device will receive.

My main purpose is to use the device as a receiver and transmitter. place two devices in front of each other at a certain distance when one transmit for a certain time and the other receive, and then after a certain time they change role(Tx/Rx) between them.

I want to know how to do the switch between the transmission and receiver.

Thank you,

Itai.

I have a question about how the signal monitor bits are mapped into the JESD lanes if you have more than one converter.  

Where do the signal monitor bits come out, Do A and B come out at the same time or do you have to have a SPI write to select which one comes out.  Do the bits come out only in lane 0 or multiple lanes?  If the data come out multiple lanes is it duplicated across the lanes so that lane 0, 1, ... all have the same signal monitor information at one time?  Or will A come out some lanes and B out others.

Thanks,

Jon

I build hdl ref design for AD9361 from hdl library and fmcomms2 project. I got following errors. I searched in web but didnt get any answer..

WARNING: [Coretcl 2-175] No Catalog IPs found
ERROR: [BD 41-74] Exec TCL: Please specify VLNV when creating IP cell axi_ad9361
ERROR: [BD 5-7] Error: running create_bd_cell.
ERROR: [Common 17-39] 'create_bd_cell' failed due to earlier errors.

while executing
"create_bd_cell -type ip -vlnv [get_ipdefs -all -filter "VLNV =~ *:${i_ip}:* && design_tool_contexts =~ *IPI* && UPGRADE_VERSIONS == \"\""] ${i_name}"
(procedure "ad_ip_instance" line 3)
invoked from within
"ad_ip_instance axi_ad9361 axi_ad9361"
(file "../common/fmcomms2_bd.tcl" line 29)

while executing
"source ../common/fmcomms2_bd.tcl"
(file "system_bd.tcl" line 3)

while executing
"source system_bd.tcl"
(procedure "adi_project_xilinx" line 97)
invoked from within
"adi_project_xilinx fmcomms2_kc705"
(file "./system_project.tcl" line 6)
save_bd_design
Wrote : <I:/Maheshfiles/VHDLfiles/hdlmaster/projects/fmcomms2/kc705/fmcomms2_kc705.srcs/sources_1/bd/system/system.bd>
current_project axi_ad9361
launch_runs synth_1
[Tue May 29 16:25:46 2018] Launched synth_1...
Run output will be captured here: I:/Maheshfiles/VHDLfiles/hdlmaster/library/axi_ad9361/axi_ad9361.runs/synth_1/runme.log
current_project fmcomms2_kc705
open_bd_design {I:/Maheshfiles/VHDLfiles/hdlmaster/projects/fmcomms2/kc705/fmcomms2_kc705.srcs/sources_1/bd/system/system.bd}
current_project axi_ad9361
current_project fmcomms2_kc705

Hello all,

I'm using Xilinx Vivado 2017.4 and Petalinux 17.4. I'm using the latest ADI linux repo, rootfs, device tree, and all the latest libraries. Yes, somehow I am able to get Petalinux up and running using the ADI stuff as an external source. It was weeks of headaches... Anyway, my target board is a custom designed ZynqMP board with an FMC connector, and attached to it is the FMCOMMS3. I finally have proper communication and calibration completed with the ad9361 device. I am able to run my custom software to read in RX data and that seems to work okay.

However, to make sure I am really reading in data, I want to run the IIO OSCILLOSCOPE software, but when I run it, it immediately crashes after pressing OK when connecting to the device remotely from my remote ubuntu machine over ethernet to the custom device.

The .osc_crash_report says:

IIO-Oscilloscope Crash Info

PID: 28579

Signal No: 11

Signal String: Segmentation fault

Error No: 0

Error String: Success

Time Stamp: Thu Jun 28 12:50:07 2018

IIO-Oscilloscope Backtrace

osc(obtainBacktrade+0x5b)[0x402cab]

/lib/x86_64-linux-gnu/libpthread.so.0(+0x11390)[0x7f811bc4a390]

/usr/lib/x86_64-linux-gnu/libiio.so.0(iio_device_find_channel+0x0)[0x7f811be5d820]

plugins/fmcomms2.so(+0xaefc)[0x7f80f8f5aefc]

/usr/local/lib/libosc.so(+0x12487)[0x7f811d106487]

/lib/x86_64-linux-gnu/libglib-2.0.so.0(+0x70bb5)[0x7f811ce53bb5]

/lib/x86_64-linux-gnu/libpthread.so.0(+0x76ba)[0x7f811bc406ba]

/lib/x86_64-linux-gnu/libc.so.6(clone+0x6d)[0x7f811b97641d]

I'm not sure how much of that actually matters to debugging it...

Reading previous threads like (iio-oscilloscope segmentation fault using hand-built uImage/dtb ), I realize I'm not sure what I should be doing next. I have custom-modified the ADI Linux to include my own drivers. If I need though, I can always update everything and go from there. However, I cannot put the development board on the network, so I cannot simply do an adi_update_script.sh.

Any pointers?

Thanks

I'm testing the LTC1856 differential channels, Chan 6 & 7. I'm confused how to configure them and read them back.

Both channels work in single ended mode reading back 32767 0x7FFF with +10V input.

When I configure the channels as differential and input +10V on chan 6 and -10V on chan 7 I read back 32767 from both channels. I also get the same result when injecting +5V on chan 6 and -5V on chan 7?

I've configured both channels with the input word 00110000 which should configure the multiplexer for differential channels + on 6 and - on 7.

I have been trying to verify audio capture and playback functionality (using ADAU1761 codec and NOT HDMI) for the past few days.

So far I could get the board to play audio files and  audio capture on zedboard,it works well.

But I need to add 2 ADAU1761 chips, a total of three ADAU1761 chips. When I use 3 chips, there is no sound playing with aplay commond.  Thanks for taking time to read. Any help will be highly appreciated.

The pl device tree is as follows：

/ {
   amba_pl: amba_pl {
      #address-cells = <1>;
      #size-cells = <1>;
      compatible = "simple-bus";
      ranges ;
          axi_i2s_adi_0: axi_i2s_adi@43c00000 {
                  compatible = "xlnx,axi-i2s-adi-1.0";
                   reg = <0x43c00000 0x10000>;
         };
         axi_i2s_adi_1: axi_i2s_adi@43c10000 {
                  compatible = "xlnx,axi-i2s-adi-1.0";
                   reg = <0x43c10000 0x10000>;
            };
         axi_i2s_adi_2: axi_i2s_adi@43c20000 {
                     compatible = "xlnx,axi-i2s-adi-1.0";
                     reg = <0x43c20000 0x10000>;
            };
         axi_iic_0: i2c@41600000 {
                     #address-cells = <1>;
                     #size-cells = <0>;
                     compatible = "xlnx,xps-iic-2.00.a";
                     interrupt-parent = <&intc>;
                     interrupts = <0 29 4>;
                     reg = <0x41600000 0x10000>;

                     adau1761_0: adau1761_0@3b {
                              compatible = "adi,adau1761";
                              reg = <0x3b>;
                        };
            };
            axi_iic_1: i2c@41610000 {
                        #address-cells = <1>;
                        #size-cells = <0>;
                        compatible = "xlnx,xps-iic-2.00.a";
                        interrupt-parent = <&intc>;
                          interrupts = <0 30 4>;
                        reg = <0x41610000 0x10000>;

                        adau1761_1: adau1761_1@3b {
                                 compatible = "adi,adau1761";
                                 reg = <0x3b>;
                           };
                  };
                  axi_iic_2: i2c@41620000 {
                           #address-cells = <1>;
                           #size-cells = <0>;
                            compatible = "xlnx,xps-iic-2.00.a";
                           interrupt-parent = <&intc>;
                           interrupts = <0 31 4>;
                           reg = <0x41620000 0x10000>;

                           adau1761_2: adau1761_2@3b {
                                    compatible = "adi,adau1761";
                                      reg = <0x3b>;
                              };
                      };
                     audio_clock: audio_clock {
                                 compatible = "fixed-clock";
                                 #clock-cells = <0>;
                                 clock-frequency = <12288000>;
                        };
                     axi_i2s_0: axi-i2s@0x43c00000 {
                                 compatible = "adi,axi-i2s-1.00.a";
                                 reg = <0x43c00000 0x1000>;
                                 dmas = <&dmac_s 0 &dmac_s 1>;
                                 dma-names = "tx", "rx";
                                 clocks = <&clkc 15>, <&audio_clock>;
                                 clock-names = "axi", "ref";
                        };
                        axi_i2s_1: axi-i2s@0x43c10000 {
                                 compatible = "adi,axi-i2s-1.00.a";
                                  reg = <0x43c10000 0x1000>;
                                 dmas = <&dmac_s 2>;
                                   dma-names = "rx";
                                    clocks = <&clkc 15>, <&audio_clock>;
                                    clock-names = "axi", "ref";
                           };
                           axi_i2s_2: axi-i2s@0x43c20000 {
                                    compatible = "adi,axi-i2s-1.00.a";
                                    reg = <0x43c20000 0x1000>;
                                    dmas = <&dmac_s 3>;
                                    dma-names = "rx";
                                    clocks = <&clkc 15>, <&audio_clock>;
                                    clock-names = "axi", "ref";
                           };
                           zed_sound_0: zed_sound_0 {
                                    compatible = "digilent,zed-sound";
                                      audio-codec = <&adau1761_0>;
                                      cpu-dai = <&axi_i2s_0>;
                                 };
                           zed_sound_1: zed_sound_1 {
                                    compatible = "digilent,zed-sound";
                                    audio-codec = <&adau1761_1>;
                                    cpu-dai = <&axi_i2s_1>;
                               };
                              zed_sound_2: zed_sound_2 {
                                       compatible = "digilent,zed-sound";
                                       audio-codec = <&adau1761_2>;
                                        cpu-dai = <&axi_i2s_2>;
                                 };
                  };
};

The loading record is as follows:

ALSA device list:
#0: ZED ADAU1761
#1: ZED ADAU1761
#2: ZED ADAU1761

root@3adau1761_project:/# aplay -l
**** List of PLAYBACK Hardware Devices ****
card 0: ADAU1761 [ZED ADAU1761], device 0: adau1761 adau-hifi-0 []
Subdevices: 1/1
Subdevice #0: subdevice #0
card 1: ADAU1761_1 [ZED ADAU1761], device 0: adau1761 adau-hifi-0 []
Subdevices: 1/1
Subdevice #0: subdevice #0
card 2: ADAU1761_2 [ZED ADAU1761], device 0: adau1761 adau-hifi-0 []
Subdevices: 1/1
Subdevice #0: subdevice #0

I configure the card 0 with adau1761.state file:

alsactl restore -c 0 -f adau1761.state

Then I use aplay to play the file of Front_Center.wav with command(aplay Front_Center.wav)  , it doesn't have a sound.

root@3adau1761_project:/# aplay Front_Center.wav
Playing WAVE 'Front_Center.wav' : Signed 16 bit Little Endian, Rate 48000 Hz, Mono

But  I just load a single adau1761 chip driver, the playback and recording are normal.

Any help will be highly appreciated.

larsc

We are using the amplifier ADA4807-2 as an integrator. The ADA4807 is powerd from 6V. As an integrator the output is saturated to the rails. In our circuit it seems that the current consumption without any load increases with a few milliammperes when the output saturates to the rails. Is this behaviour as expected for this amplifier?

An LTSpice simulation of our circuit does not show increased current consumption when the output saturates to the rails.

Hi all,

I want to add custom IPs to the ADRV9371 HDL reference design. I'm working with AD9371 eval board and zynq ZC706. 

Just I have a question about your Analog Devices Inc. Board Support Packages to integerate my FPGA IP without doing that manually (modify the design block) but when I go through HDL Workflow Adviser I don't find AD9371+ZC706 (as target platform) ????

Thank you

We are using the fast lock profiles to switch with the ctrl pins , but it seems that the pins are shifted from the data sheet Ref F

According the data sheet ctrl_in[2:0] should be used, but this didn't not work, we got only 4 frequencies instead of 8 out.

Now we use ctrl_[3:1] and it works fine.

We measure it also on our PCB and it works also if we switch them with the SPI command.

Please can you confirm, that this is an bug in data sheet.

Hello,

We have custom board for ad9363. We try to use SINGLE-PORT, FULL DUPLEX MODE(CMOS). I use the parameters that located in attachments. we need only rx side, so that we try to tune only for rx. 

Our driver is 2017_1 (KC705 reference desing.)

Do you have any suggestion about this issue?

Note : On the same board there is ad9364. And we use in LVDS mode properly.

Regards,

Yasin

Hi there,

we no configured the structs of the HMC7044 driver but for some reason I can't see any output. So far it looks like the driver is calculating reasonable values from the settings but if I read the status readback registers I see the PLL1 staying in reset. 

Here's the output: 
Alarm Readback Reg 0x007B: 0x00
Alarm Readback Reg 0x007C: 0x00
Alarm Readback Reg 0x007D: 0x02
Alarm Readback Reg 0x007E: 0x00
Alarm Readback Reg 0x007F: 0x00
PLL1 Status Reg 0x0082: 0x00
PLL1 Status Reg 0x0083: 0x40
PLL1 Status Reg 0x0084: 0x3F
PLL1 Status Reg 0x0085:  0x03
PLL2 Status Reg 0x008C: 0x10
PLL2 Status Reg 0x008D: 0xFF
PLL2 Status Reg 0x008E: 0x1F
PLL2 Status Reg 0x008F: 0x00
Sysref Status Reg 0x0091: 0x1A

Any chance you guys have an idea what could cause this? If the input reference is not good enough I'd expect the PLL1 not locking to the clock but it doesn't really seam to do anything?! Does it need a sync? From my understanding the sync is only required to synchronize several HMC7044 devices, which we don't have?!

Any hints would be highly appreciated.

Regards,

Lennart

Hello,

We have mounted adv7604(hdmi decoder) and adv7340(encoder) on interface board. we have installed appropriate drivers and configured them in device tree but when I connect analog monitor I am not getting anything on that monitor.

Is it because of absence of edid? please let me know how do I configure analog monitor to get the analog output on it.

Thanks in Advance,

Hello,

I have started to see spikes in the data from the AD9371 receiver and would like to understand the cause and eliminate them.

Initially I tested the AD9371 with the default centre frequency of 2.55GHz. The data was captured from JESD into RAM and analysed over of a range of test tone frequencies and amplitudes. The amplitudes were measured in -10dbm intervals down to -100dbm and no-signal. At the lower end the output was noise in the range of +/-10 counts.

Altering the centre frequency to 1.3GHz and re-measuring now shows single sample noise spikes in the input signal when significantly lower than 8-bits (eg/ +/-40 counts). Spikes are in the range -256 to -249 counts, and +248 to +255 appear over about 1% of the samples (example time domain plot of captured test data attached showing problem).

I am surprised that just changing the centre frequency would cause this, however now I am wondering about the LO/PLL and problems with it, and things like decoupling. The hardware is a AD9371 evaluation board.

Any ideas as to the cause of this and how to eliminate the source of the noise?

Before I dig it out in detail on my own from the 2200 pages HRM - can one give me a feedback if the following is possible with the ADSP-CM408/409?

I want to capture the actual CNT-Value and Time-Interval from the last increment or decrement with DMA and start simultaneous a DMA-data-transfer via SPI0 and SPI1 all at the exact same time in a predefined interval.

And if so - how to configure all that?

Hello.

We have in some trouble about using PVSP and SVSP simultaneously of ADV8005.

Please give us your advise.

Case1

[1080p] -> Primary Input Channel -> PVSP(1080p to 1080p) -> TX1       ==>> No problem

Case2

[1080p] -> Primary Input Channel -> PVSP(1080p to 1080p) -> TX1      ==>> NG(shaking vertically)

                                                      -> SVSP(1080p to 1080p) -> TX2      ==>> NG(shaking vertically)

Case3

[1080p] -> Primary Input Channel -> PVSP(1080p to 1080p) -> TX1      ==>> NG(shaking vertically)

                                                      -> SVSP(1080p to 1080p)

                                                      ----------<Bypass>-------------> TX2      ==>> No problem

Case4

[1080p] -> Primary Input Channel -> PVSP(1080p to 1080p) -> TX1      ==>> No problem

                                                      -> SVSP(Disable)

                                                      ----------<Bypass>-------------> TX2      ==>> No problem

<other comments>

-HDMI timing is OK on Astro protocol analyzer in even NG case.

-It seems no problem in following case

               PVSP(1080p to 480p) and SVSP(1080p to 480p)

              PVSP(1080p to 2160p) and SVSP(1080p to 480p)

-The register settings of PVSP and SVSP are below.

:112 PVSP In-1080p60 Out-1080p60:
1A E828 10 ; Disable VIM, FFS and VOM
1A 1A44 4C ; Default 0x00, Enable Frame Track Mode, vsp3d_freq_sel = 0, vsp2d_freq_sel = 1
1A E884 00 ; Default 0x00, di_lowpower_en = 0
1A E890 00 ; Default 0x00, pvsp_srccal_8bit = 0
1A E883 80 ; Default 0x80, enable autoconfiguration
1A E881 10 ; Default 0x06, pvsp_autocfg_input_vid = 0x10
1A E882 10 ; Default 0x10, pvsp_autocfg_output_vid = 0x10
1A E86C 00 ; Default 0x10, pvsp_dp_subid = 0x0
1A E935 C6 ; Default 0xC6, di_fd_scaler_predict = 0x0C
1A 1A4E 08 ; Default 0x80, Automatic track mode for PVSP
1A E84E 01 ; Default 0x11, pvsp_frc_change_phase_en = 0x0
1A E890 00 ; Default 0x00, srscal_downscaling_blur = 0
1A E828 11 ; Default 0x10, Enable FFS
1A E828 13 ; Default 0x10, Enable VIM
1A E828 17 ; Default 0x10, Enable VOM
End

:72 SVSP In-1080p60 Out-1080p60:
1A E610 08 ; Disable VIM, FFS and VOM
1A E662 81 ; Default 0x80, enable autoconfiguration
1A 1A44 C4 ; Default 0x00, Enable Frame Track Mode, vsp3d_freq_sel = 1, vsp2d_freq_sel = 0
1A 1A00 10 ; Default 0xFE, video_in_id = 0x10
1A E660 10 ; Default 0x00, svsp_autocfg_input_vid = 0x10
1A E661 10 ; Default 0x00, svsp_autocfg_output_vid = 0x10
1A E64A 10 ; Default 0x00, svsp_s_p2i_vid = 0x10
1A 1A4F 08 ; Default 0x80, Automatic track mode for SVSP
1A E649 10 ; Default 0x00, main P2I always enabled
1A E663 00 ; Default 0x00, disable manual configuration
1A E610 88 ; Default 0x00, Enable FFS
1A E610 C8 ; Default 0x00, Enable VIM
1A E610 E8 ; Default 0x00, Enable VOM
End

 How should we do to solve this problem?

Could you please give us some advise?

Best regards.

Kikka

Hello,

I would like some advice on how to understand and fix the root cause of error flags tripping in the transmit path. I am using the AD9371 evaluation board, with a Xilinx ZCU102 FPGA eval board.

The transmit path is being fed a digitally generated sine wave for "I" and the 90 degree offset "Q" signal over JESD. I have a simple control over amplitude by shifting (ie/ dividing by 2). So generate a full range signal, then half range, quarter range etc. Giving 8 output levels (call them 0dB to -42dB in -6dB steps). I can understand a full range signal allows no headroom for the calibration routines supported by the ARM device inside the transceiver, as they alter the gain of the paths - and in this case a spectrum analyser on the output series of harmonics at the test tone frequency. These disappear with a slight reduction of input signal.

However, I am finding the error flags trip (and latch) when switching on much lower signals between -6dB to -18dB. So at the moment I am restricting measurements to -24dB and below. This loses a lot of dynamic range (1/16th of full range).

The HB1, HB2 and QEC flags trip. The 4th  PFIR flag never seems to trip.

There seems to be little available information to debug the transmit path signals, just the latching error flags.

Any ideas to investigate/fix?