Hello,
I have questions concerning the recently published QPSK-modem example:
1. is there a single bitstream regardless the ADRV9361-Z7035 based platform, e.g. PackRF, FMC carrier, BOB?
2. how can you control the transceiver parameters, e.g. carrier frequency, transmit power level, etc. using the stand-alone version (without Simulink interface)? Is there any app running on linux for this purpose?
BR,
Rafal Krenz
Hi Analog Dedicated Team,
I did some comparison signals between TX-RX 1 and TX-RX 2 on fmcomms2 using GNURadio. This experiment was taken in May 2018 as shown in Fig1 below.
And the result as shown in Fig2 below:
Clearly this variation seem acceptable. Then lately i found some error on my user application. Then I run again this experiment and the result shown high significant different on TX-RX 2 as shown in Fig 3 below( taken by today).
on TX-RX 1 look normal but huge variation on TX-RX 2.
Then I did some sweep on frequency to observe their magnitude consistency as shown in Fig 4 below.
1- Anyone have idea why this symptom happen only on one transceiver (TX-RX 2 only) ? but others receiver TX-RX 1 seems OK?
2-How I can calibrate those TX-RX 2 path ?
Best Regards,
Hi,
We are working on our custom board.
Using ADI kernel, we were able to bring up the JESD interface, as well RF data path. (data path is in progress)
We are now trying to bring up the same on user space, using mykonos library without kernel driver. (ad9371.c)
JESD interface is ok. However when "TX_LO_LEAKAGE_INTERNAL | TX_QEC_INIT" options are enabled in initCalMask, it fails. If we disable these options there are no errors.
This was not the case in kernel driver. (It works fine when these options are enabled)
I have attached the error log which we get from user space.
Kindly provide pointers, if this is configuration issue and which params can have an effect on init cal to fail.
Thanks,
Saravana
Dear Sir/Madam,
I am designing a signal receiving board, and I want to choose an amplifier with low noise and high linearity. I find that I can choose depend on P1dB in RF Amplifiers category, but I can’t find similar parameter in Operational Amplifiers category. So could you give me some suggestions?
Best regards
Chen
Hello.
We have in some trouble about using PVSP and SVSP simultaneously of ADV8005.
Please give us your advise.
Case1
[1080p] -> Primary Input Channel -> PVSP(1080p to 1080p) -> TX1 ==>> No problem
Case2
[1080p] -> Primary Input Channel -> PVSP(1080p to 1080p) -> TX1 ==>> NG(shaking vertically)
-> SVSP(1080p to 1080p) -> TX2 ==>> NG(shaking vertically)
Case3
[1080p] -> Primary Input Channel -> PVSP(1080p to 1080p) -> TX1 ==>> NG(shaking vertically)
-> SVSP(1080p to 1080p)
----------<Bypass>-------------> TX2 ==>> No problem
Case4
[1080p] -> Primary Input Channel -> PVSP(1080p to 1080p) -> TX1 ==>> No problem
-> SVSP(Disable)
----------<Bypass>-------------> TX2 ==>> No problem
<other comments>
-HDMI timing is OK on Astro protocol analyzer in even NG case.
-It seems no problem in following case
PVSP(1080p to 480p) and SVSP(1080p to 480p)
PVSP(1080p to 2160p) and SVSP(1080p to 480p)
-The register settings of PVSP and SVSP are below.
:112 PVSP In-1080p60 Out-1080p60:
1A E828 10 ; Disable VIM, FFS and VOM
1A 1A44 4C ; Default 0x00, Enable Frame Track Mode, vsp3d_freq_sel = 0, vsp2d_freq_sel = 1
1A E884 00 ; Default 0x00, di_lowpower_en = 0
1A E890 00 ; Default 0x00, pvsp_srccal_8bit = 0
1A E883 80 ; Default 0x80, enable autoconfiguration
1A E881 10 ; Default 0x06, pvsp_autocfg_input_vid = 0x10
1A E882 10 ; Default 0x10, pvsp_autocfg_output_vid = 0x10
1A E86C 00 ; Default 0x10, pvsp_dp_subid = 0x0
1A E935 C6 ; Default 0xC6, di_fd_scaler_predict = 0x0C
1A 1A4E 08 ; Default 0x80, Automatic track mode for PVSP
1A E84E 01 ; Default 0x11, pvsp_frc_change_phase_en = 0x0
1A E890 00 ; Default 0x00, srscal_downscaling_blur = 0
1A E828 11 ; Default 0x10, Enable FFS
1A E828 13 ; Default 0x10, Enable VIM
1A E828 17 ; Default 0x10, Enable VOM
End
:72 SVSP In-1080p60 Out-1080p60:
1A E610 08 ; Disable VIM, FFS and VOM
1A E662 81 ; Default 0x80, enable autoconfiguration
1A 1A44 C4 ; Default 0x00, Enable Frame Track Mode, vsp3d_freq_sel = 1, vsp2d_freq_sel = 0
1A 1A00 10 ; Default 0xFE, video_in_id = 0x10
1A E660 10 ; Default 0x00, svsp_autocfg_input_vid = 0x10
1A E661 10 ; Default 0x00, svsp_autocfg_output_vid = 0x10
1A E64A 10 ; Default 0x00, svsp_s_p2i_vid = 0x10
1A 1A4F 08 ; Default 0x80, Automatic track mode for SVSP
1A E649 10 ; Default 0x00, main P2I always enabled
1A E663 00 ; Default 0x00, disable manual configuration
1A E610 88 ; Default 0x00, Enable FFS
1A E610 C8 ; Default 0x00, Enable VIM
1A E610 E8 ; Default 0x00, Enable VOM
End
How should we do to solve this problem?
Could you please give us some advise?
Best regards.
Kikka
We are using AD9364 for Narrow-band FM(24KHz bandwidth) signal, what we observed is that when downconvert it to DC, we are seeing the performance degradation. Instead of directly down-converting to baseband, when we downconvert it to some 24KHz offset, the performance improved. I suspect that the Baseband DC calibration is causing the issue. Is there any way to reduce or mitigate this issue?
I tried changing the update rate in register 0x190 [D7:D5], but nothing improved much.
Hi all,
Following is datasheet comment,
"The only external components required are the input/output ac coupling capacitors, power supply decoupling capacitors, and dc bias inductor."
The general gain block amps need to dc bias inductor and/or dc bias resistor to select dc bias resistor to achieve the supply current.
Is it correct, not need to limit the supply current, with dc bias resistor ?
Best regards,
sss
Hello,i would like to ask you about the type of chips to buy for breadboads.I Want to buy AD8221 to use it for a project but im confused about.There are 2 types as i have found Surface-mount and Through-hole.I have only found the surface mount.Could you suggest me a solution(i found some weird solutions i dont know if its ok to use them)?Or maybe a through hole chip!
Thanks in Advance
In the documentation, page 226/360, I read:
"Note that the phase-locked loop (PLL) unlock bits are not sticky. These bits follow the current status of the PLLs. If the PLL relocks, the status bit clears as well."
I understand for the PLL unlock bits, but I suppose it means also that the other bits are sticky. How can one acknowledge the other bits?
Currently bit 5 (JESD204 deframer interrupt occurred) is set, which is consistent with the DeframerStatus where bit 6 (This bit indicates that the IRQ interrupt was asserted). How to acknoledge?
Réf. UG-992, AD9371/AD9375 System Development User Guide, Rev B.
I have a project using the ADSP 21479 board. I was given the code to try out and imported the project into a new project in my workspace.
I build it in debug mode and it works fine.But I build it in release mode and it Prompt for the following error.
I have tried refreshing, clean, close, opening the project.
The first error I get is the li1050 which in turn causes the linker error of cc3089.
How does select the .doj file in .\release file and .\debug file when linking ? Any ideas on what I can do to resolve the issue?
[Error li1050] '_AD5420ReadControlReg' ('AD5420ReadControlReg'): Multiply defined symbol in processor 'P0'.
Linker finished with 272 errors
,Hello
At the moment we are evaluating the PA performance with the AD9375 DPD.
My question is if the DPD performance will be affected if i will put 1 or 2 SAW filters between the D2A to the PA.
it it is affecting the performance , please explain from what aspect?
Group Delay?
Group Delay Variation?
Ripple?
Regards,
Hi there,
we now added configured the structs of the HMC7044 driver but for some reason I can't see any output. So far it looks like the driver is calculating reasonable values from the settings but if I read the status readback registers I see the PLL1 staying in reset.
Here's the output:
Alarm Readback Reg 0x007B: 0x00
Alarm Readback Reg 0x007C: 0x00
Alarm Readback Reg 0x007D: 0x02
Alarm Readback Reg 0x007E: 0x00
Alarm Readback Reg 0x007F: 0x00
PLL1 Status Reg 0x0082: 0x00
PLL1 Status Reg 0x0083: 0x40
PLL1 Status Reg 0x0084: 0x3F
PLL1 Status Reg 0x0085: 0x03
PLL2 Status Reg 0x008C: 0x10
PLL2 Status Reg 0x008D: 0xFF
PLL2 Status Reg 0x008E: 0x1F
PLL2 Status Reg 0x008F: 0x00
Sysref Status Reg 0x0091: 0x1A
Any chance you guys have an idea what could cause this? If the input reference is not good enough I'd expect the PLL1 not locking to the clock but it doesn't really seam to do anything?! Does it need a sync? From my understanding the sync is only required to synchronize several HMC7044 devices, which we don't have?!
Any hints would be highly appreciated.
Regards,
Lennart
Dear Friends ,
I am going to begin using ade7758 for Vrms , Irms , 3 phase energy measurement .Please let me know how to start communicating.
1. Is there a register reading which, i can assure my mcu is communicating with ade7758.
2. What are the steps required to read Vrms(all 3 phases) , Irms(All 3 phases using ct as transducer) ,Active energy kwh for all 3 phases.
Thx.....
Hi,
We are working on our custom board.
Using ADI kernel, we were able to bring up the JESD interface, as well RF data path. (data path is in progress)
We are now trying to bring up the same on user space, using mykonos library without kernel driver. (ad9371.c)
JESD interface is ok. However when "TX_LO_LEAKAGE_INTERNAL | TX_QEC_INIT" options are enabled in initCalMask, it fails. If we disable these options there are no errors.
This was not the case in kernel driver. (It works fine when these options are enabled)
I have attached the error log which we get from user space.
Kindly provide pointers, if this is configuration issue and which params can have an effect on init cal to fail.
Thanks,
Saravana
Hello,
We have mounted adv7604(hdmi decoder) and adv7340(encoder) on interface board. we have installed appropriate drivers and configured them in device tree but when I connect analog monitor I am not getting anything on that monitor.
Is it because of absence of edid? please let me know how do I configure analog monitor to get the analog output on it.
Thanks in Advance,
Hello,
After reading the Application note (AN-1354) i would like to ask some question that wasn't clear:
1) In order to determine what is the rejection between TX to RX i would like to know what is the attenuation that should be define to the TX signals in order to avoid degradation in the AD9375 performance. Take under consideration that the LNA on the RX can receive up to 2dBm input power .
Example:
TX output power 30dBm LTE 10 MHZ (LTE PAR 8.5dB)
Duplexer Front-End Rejection: 60dB
Guard between TX To RX Bands 38MHz
LNA maximum input power 2dBm
RX Gain : 38dB
In that case the receive power to the LNA will be -30dBm AVG ( -21.5dBm Peak) so i am not compressing the LNA.
Now after 20dB analog gain and 18dB of the AD9375 Gain the Out of band signal will reach up to 8dBm AVG.
I would like to understand if i need to add more filtering (like Duplexer with higher rejection or SAW near the AD9375 RX path) in order to avoid problems.
Please let me know what is the rejection that i need and how did you got in to the number (so i can calculate similar cases by my self).
Also , please let me know if there is any limitation to the AD9375 filters by the Guard between the In-Band to the Out of band.
Let's say that the TX to RX signals is 8 MHz Gourd. It will change your answer regarding to the rejection betwen TX signals to RX ?
Hello,
I am interested to use Ettus B210 for DOA purposes.
According to[1], B210 is using AD9361 2X2 MIMO chipset.
According to AD9361 datasheet, both RX channels are being driven by the same LO[2].
However, according to[3][4], there is a phase difference between the two USRP-B210 channels.
According to[5], the RX channels are aligned in phase.
Would be glad to have a formal answer to the following 2 questions:
1. Is there a phase difference between the two USRP-B210 RX channels?
2. If there is a difference - what causes it?
Thanks in Advance.
[1] https://www.ettus.com/product/details/UB210-KIT
[2] http://www.analog.com/media/en/technical-documentation/data-sheets/AD9361.pdf
[3] http://ettus.80997.x6.nabble.com/USRP-users-Phase-jumps-in-USRP-B210-with-GPSDO-td7260.html
[4] http://ettus.80997.x6.nabble.com/Re-USRP-users-Random-Phase-Offset-Between-Two-Rx-Channels-of-B210-td10094.html
[5] http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/2017-January/023422.html
Hello,
My application requires very high currents (~20A max peaks) and low noise thus I'm looking at the ADP1765 as the LDOs for the job. I would need to parallel 4 or 5 of them, should I just parallel all of them as indicated for 2 devices in the datasheet ?
Is a special arrangement necessary ?
Can I scale the provided Vout equation the same way it has been done for two devices ?
Thanks in advance,
Michael.
This is a question about the operation of the AD9144.
My customers are evaluating the AD9144.
My customer is trying to output sawtooth waves from AD9144.
T = 200 nS, + 100 count → -100 count
The customer inputs the code and evaluates the output waveform.
Strangely, the output slope bounces small around 0 count.
Customers suspect this as miscounts.
Is this due to the nature of T-DAC?
Do you have any views?
Please advise me.
Is this phenomenon called MIDSCALE GLITCH?
Where should I check to isolate it from mistakes in circuit design?
Best regards
