Hi !
I have a question about ADuM128x.
Do you have any test result for ADuM128x?
I already asked for other device at past but now, I want to know ADuM128x's result.
Best regards
Kawa
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(ADuM128x)Do you have some EMI test result for ADuM128x?
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No Os driver on hdl-2016-r1 branch
Hi,
I have build the project using hdl-2016-r1 branch for Arradio+Arrow SOC setup. Project was successfully build and .sof file was generated. When i downloaded the hardware image(.sof) and run the no OS driver, I am getting error that ad9361 init faild with invalid product id. I have probed the SPI_DI, SPI_SCLK and SPI_ENB all signal is normal but part is not giving data (no activity in SPI_DO of Arradio).
Please help me.
Regards
J S Hyanki
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Multiple HMC7043 Synchronization issues
I am attempting to synchronize two parallel HMC7043 evaluation boards that are being driven from the same clock source. I get very inconsistent results from the outputs of both of my HMC7043 devices.
I have verified that my input signals, both system clock and the SYSREF pulses are consistently aligned and meet the JESD204B spec. I have included a screen capture of both CLKIN and RFSYNC inputs for reference.
I have also included a couple screen captures of the results I am seeing. One of my devices seems to perform consistently, where the other does not. I have them both configured the same and am loading the same .py file to both.
I am using LVPECL output buffer, with 150 ohm termination resistors to ground on both the CLK and SCLK outputs. My CLK outputs are divide by 1, so I have a digital step of 1 applied to ensure phase alignment. My SCLK outputs are divide by 12, but also have the digital step of 1 applied for consistency. I have the dynamic output buffer disabled, as I notice very inconsistent outputs with this feature active. I have the SYNC retime MUX set to retime, and my SYSREF timer is currently set to 13.
Is there something drastic I am missing with this setup? Thanks for any help with this issue, I can provide more details if needed.
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Re: VRMS reading greater than VPEAK
I forgot to mention but that issue is on ADE7953.
Em 31 de ago de 2017 12:21, "Victor Oliveira" <victor.rsoliveira@gmail.com>
escreveu:
VRMS register (0x21c or 0x31c) is returning a value greater than VPEAK
register (0x226 or 0x326). I've already checked VRMSOS value and it's 0,
meaning that it adds no offset value to VRMS reading, and also I observed V
register (0x218 or 0x318) for instantaneous values of voltage and I see
that the biggest value is equivalent to VPEAK. What is odd to me is that
VRMS value is giving exactly the peak value expected for my application and
VPEAK is giving the exact voltage value in RMS. Here is an example,
VRMS: 5666625
VPEAK: 3980748
Input voltage is 220V RMS at 60Hz. The circuit for voltage channel input
is the following:
>
GNDA is connected to AC_PHASE because I am using a shunt resistor as a
current sensor. I wonder if there is some error in the circuit, but I've
checked another reference circuits and they're pretty similar.
The calculations to convert VRMS and VPEAK values back to real values are
the following:
For VRMS, 5666625/9032007(max value for VRMS) = 0.627, and then 0.627 *
0.5 (full-scale) = 0.313mV. This is the value applied to VN-VP pins and in
my understanding, 0.313mV is the peak value of this signal, not RMS. If I
do the same procedure to VPEAK value (I assume that the maximum value is
the same, 9032007) I get 0.440 * 0.5 = 0.220, and this should be exactly
the RMS value of the input signal.
Does that make any sense? What am I doing wrong?
PS.: I have made the question in the forum, but because I need an urgent
response I also tried via email. I am sorry for duplicates :/
--
Regards,
Victor Rafael S. de Oliveira
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VRMS reading greater than VPEAK
VRMS register (0x21c or 0x31c) is returning a value greater than VPEAK
register (0x226 or 0x326). I've already checked VRMSOS value and it's 0,
meaning that it adds no offset value to VRMS reading, and also I observed V
register (0x218 or 0x318) for instantaneous values of voltage and I see
that the biggest value is equivalent to VPEAK. What is odd to me is that
VRMS value is giving exactly the peak value expected for my application and
VPEAK is giving the exact voltage value in RMS. Here is an example,
VRMS: 5666625
VPEAK: 3980748
Input voltage is 220V RMS at 60Hz. The circuit for voltage channel input is
the following:
GNDA is connected to AC_PHASE because I am using a shunt resistor as a
current sensor. I wonder if there is some error in the circuit, but I've
checked another reference circuits and they're pretty similar.
The calculations to convert VRMS and VPEAK values back to real values are
the following:
For VRMS, 5666625/9032007(max value for VRMS) = 0.627, and then 0.627 * 0.5
(full-scale) = 0.313mV. This is the value applied to VN-VP pins and in my
understanding, 0.313mV is the peak value of this signal, not RMS. If I do
the same procedure to VPEAK value (I assume that the maximum value is the
same, 9032007) I get 0.440 * 0.5 = 0.220, and this should be exactly the
RMS value of the input signal.
Does that make any sense? What am I doing wrong?
PS.: I have made the question in the forum, but because I need an urgent
response I also tried via email. I am sorry for duplicates :/
--
Regards,
Victor Rafael S. de Oliveira
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About ADV7282-M: Can I revese the angle of its output image data?
Hi there,
My customer is using ADV7282-M in a building intercom product and now they come across a problem.
Sometimes they need to revese the image output from ADV7282-M however their Android APP can't support this function. So they want to know whether can they revese the ouput date of ADV7282-M to realize this function of revese the image in their screen? Their host paltform is snapdragon 410.
If you need more information, pls let me know. Tks!
Best Regards,
Alex
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AD9734-DPG2-EBZ
Do you have AD9734-DPG2-EBZ User Gides?
Need AD9734-DPG2-EBZ and AD-DAC-FMC-ADP, whichare listedin the followingURL?
IfollowingURLwas alsochecked.
AD973x Evaluation Board [Analog Devices Wiki]
But the entire connection configuration even I do not know well.
Please help me.
Thank you.
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AD5421 SPI communication problem.
I have a problem communicating with the chip. Logic Analyzer indicates nice read/write packets but I get zero when I try to read from the chip.
May be my SPI mode is wrong? Currently it’s - Clock idle low, sample on falling edge.
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AD5421 Powering up
Hi,
I have design AD5421 based 4-20mA loop powered system. The schematic is attached. I see following problem:
1. The D_VDD always outputs 4.2V but datasheet says 3.3V but can have 5.5V overdrive.
2. If REG_OUT pin floating instead of tying to D_VDD and IOD_VDD and measure voltage at REG_OUT then it measures 2.7V.
The REG_SEL0 and REG_SEL1 is tied to 3.3V and REG_SEL2 is tied to GND.
3. The range resistors are tied to ground to configure output to 4-2mA.
4. The ADuM1447 is disconnected from the system.
Could anyone guide me what is wrong happening? Did I miss anything?
Regards
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AD5421 SPI Read/Write Data Format
Hello,
We have an AD5421 integrated to our PCB, connected to the SPI4 peripheral of a Ti Hercules RM48L950PGE MCU. Getting a response from the AD5421 is proving to be a problem. As a first step writing and reading the control register is the focus. Can someone confirm that the waveform below looks acceptable for a read and write of the control register? As far as I know it is compliant with what the datasheet asks for. For now the SPI is being polled as opposed to interrupt driven.
I have disabled the auto-fault readback in the initial control register write.
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How do you initialize AD5421? IS something wrong in my code?
Hi,
I am devloping AD5421 based system. The controller is MSP430F2013 which act as a master. The schematic reference to AD5421 is as below:
Note:
1. Resistor R16, R18, R20, R22 and R28 are uninstalled.
2. Resistor R28, and R29 are replaced by 0 Ohms resistor.
So with this configuration AD5421 is placed in 4 - 2mA loop mode.
During booting up the microcontroller initializes AD5421 as using two function call namely, InitAD5421() function and AD5421_SetRegisterValue().
void InitAD5421(void)
{
unsigned int reg;
reg = AD5421_CTRL_WATCHDOG_DISABLE;
AD5421_SetRegisterValue(AD5421_REG_CNTRL, reg); //AD5421_CTRL_WATCHDOG_DISABLE);
}
void AD5421_SetRegisterValue(unsigned char regAddress, unsigned int regValue)
{
unsigned char data[5];
unsigned char byte;
data[0] = AD5421_REG_OFFSET; // Load offeset in first byte
for(byte = 1; byte < 5; byte++) // and initialize rest of the bytes to 0x00
{
data[byte] = 0x00;
}
data[0] = (unsigned char) regAddress; // get the Address/ Command Byte from
//calling function
data[1] = (unsigned char) ((regValue & 0xFF00) >> 8); // Separate out higher bytes and lower byte
data[2] = (unsigned char) ((regValue & 0x00FF) >> 0); // send it to AD5421 as data
SpiWrite(data, 3); // write on the SPI bus
}
and in while loop I continuously sending 0xFFFF so that output is 20mA:
AD5421_WriteDAC(0xFFFF);
When I measure output it is always 3.92mA irrespective of data coming from microcontroller.
Could anyone suggest me what is missing?
Regards,
Girish
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An issue about AD7151
Hi,
I encountered a strange problem while using AD7151 as a capacitance sensor in my current smart hardware design.
AD7151 suffers from serious reading drifting in a specific circumstance where the capacitance should be fixed, but is reported as continuously and slowly increasing (data register increments by one every approximately 5 minutes.)
I wonder if this is normal and what can I do to stress this drifting problem.
Hopefully I made myself clear and feel free to ask me about the configurations of the chip and other design details.
Any comment is appreciated.
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AD7151 noise
Noise seems to be very high when continuously poling I2C
Works fine when no communication or when communication is slow,
but constantly reading STATUS followed (if ready) by DATA or AVERAGE leads to high noise.
Data rate is 400KHz - so polled every 100us aprox.
Is this a device limitation or layout possibly ? VCC is well filtered.
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AD7151/AD7156
Hello All,
I want to use AD7151 or AD7156 C to D Converter. The current consumption is a very critical for the application.
My question is:
What is the current consumption of the AD7151 and AD7156(with one enabled channel) in IDLE MODE?
Best regards,
Ilian
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Capacitive level sensor
Dear all,
I need to design a capacitive continous level sensor for a fuel tank. The sensor it self is a rod placed inside tube having empty capacitance of 47pF and with the tank filled about 150pF. The usual method is to use the capacitance in an RC oscillator and than measure the frequency than convert it to volumetric leveling. The success is unfortunately temperature dependent and should be compensated. Is there any better way to build up this sensor? I would need at least 10bit over 100pF so a definition of 0.1pF is requested. One important remark is, that one of the measuring capacitors armature is grounded to the tank (tank is made out of regular steel sheets). I have looked some of the CDC (AD7151) chips but those seems to work only for feed-in capacintances from excitation to the CDC and the output is only treshold based.
Any hint or advice is welcome!
Thank you , Endre
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AD5685 start up reference setting
Hello.
I have a concern to Vref for AD5685.
Of course I was compliance with the rules of the absolute maximum rating.
In power up sequence, AD5685 internal reference was enable.
But in circuit external 3.0V reference supplied to AD5685.
After a few sec AD5685 internal reference was disable.
But in datasheet Vref impedance was 0.04ohm.
I am concerned about this internal Vref circuit was broken at the power up sequence..
Because, if a current flows into the internal reference
Best regards
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AD5685R, does VDD/Vlogic order affect powerup settings?
I am considering using the AD5685 quad DAC in an application with Vdd=5V and Vlogic=3.3V, where Vlogic is supplied by a linear regulator that has Vdd as its input. Therefore Vdd will come up before Vlogic (although the delay should be brief). Since the powerup settings for gain and default DAC output are referenced to Vlogic, will these settings still take effect or do I need to sequence Vdd to the device so that Vlogic comes up first?
Thanks,
Jason
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Can the 56 MHz channel bandwidth limit be exceeded by bypassing filters?
Our application is a harmonic radar. We can transmit a signal that is band-limited to 56 MHz, but the reflected harmonic will occupy a bandwidth of 2*56 = 112 MHz. Is it possible for us to bypass the filters internal to the AD9361, and replace them with custom external filters in order to use a higher channel bandwidth? Or will we need to limit our transmit bandwidth to 56/2 = 28 MHz?
Note: we would like to occupy as much bandwidth as possible for our application.
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What are the operating and storage altitude specifications of AD9361?
Hey,
What are the operating and storage altitude specifications of AD9361?
Thank you.
Gokhan.
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Different behaviors of AD9361 FMCOMM3 RF cards
Dear Sir, Madam.
I am an engineer at Uurmi systems. In January, 2017 we have purchased ‘3’ Avnet kits (https://www.xilinx.com/products/boards-and-kits/1-45sl7b.html ) which includes (Zc706 FPGA, AD9361 FMCOMMS3 RF card, and other connecting cable).
My goal of the project is to receive and decode MIB bits of live LTE signals in different LTE bands. Specifically, I am interested in LTE Band- 3 frequency (1830.4Mhz carrier frequency).
To achieve this goal, I am using Avnet kit and Mathworks LTE System toolbox. I am using (zynqRadioLTEReceiverAD9361AD9364ML.m) matlab example to configure AD9361 RF card and decode MIB bits.
After properly setting up Zynq FPGA, AD9361 RF card (part number 696662) with Mathworks LTE System toolbox, I can sucessufully receive and decode MIB bits. In this setup I have replaced AD9361 card with another to make sure I will get same results. So, without changing the Zynq board and other configurations I just replaced AD9361 RF card (part number 696662) with another AD9361RF cards (part number 696673)
To my surprise, after changing AD9631 RF card I can receive signals but unable to decode MIB bits because of the poor signal strength at ADC output.
Same behavior is noticed by replacing third AD9361 RF card (part number 696665)
In order to be more specific I am copying RF configuration parameters, PSD plot with 2 AD9631 RF cards and time domain correlation plots.
RF configurations parameters:
'DeviceName': 'ZedBoard and FMCOMMS2/3/4'
'ShowAdvancedProperties': true
'GainSource': 'Manual'
'Device': 'Xilinx Zynq and ADI FMCOMMS2/3/4'
'sdrBlockType': 'SDRRxBlock'
'carrierBoard': 'Xilinx Zynq'
'radioBoard': 'Analog Devices FMCOMMS2/3/4'
'driverLib': 'C:\ProgramData\MATLAB\SupportPackages\R2017a\toolbox\shared\sdr\sdrplug\sdrpluginbase\host\derived\bin\win64\libmwsdrembed'
'MaxNumChannels': 2
'subDeviceList': 'zynqReceiver'
'sdrExecutionMode': 'HW'
'IPAddress': '192.168.3.2'
'dataUDPPort': -1
'ctrlUDPPort': -1
'OutputDataType': 'double'
'SamplesPerFrame': 19200
'EnableBurstMode': true
'NumFramesInBurst': 5
'DataIsComplex': true
'NumChannels': 2
'ChannelMapping': 1
'SampleRate': 3840000
'SourceSelect': 'RF data'
'SourceConfiguration1': 1023
'BypassUserLogic': false
'CenterFrequency': 806000000
'GainControlMode': 'Manual'
'Gain': 50
'BasebandSampleRate': 1920000
'RxChannelPackSelect': 3
'FIRCoefficientSize': [128;128]
'FIRCoefficients': 2x128 double
'FIRGain': [0;-12]
'FIRDecimInterpFactor': [4;4]
'AnalogFilterCutoff': [3152524;3161715]
'FilterPathRates': 2x6 double = 983040000,122880000,61440000,30720000,15360000 and 3840000
'FilterDesignTypeForTx': 'DefaultFilterFromOther'
'FilterDesignTypeForRx': 'DefaultFilter'
'EnableQuadratureTracking': true
'EnableRFDCTracking': true
'EnableBasebandDCTracking': true
'BISTLoopbackConfig': 'No Loopback'
'BISTPRBSMode': 'PRBS Disable'
'BISTToneMode': 'Tone Disable'
'BISTToneFrequency': 'F/32'
'BISTToneLevel': '-6'
'BISTChannelMask': 0
'DMATimeoutValue': 1
I have also made sure that ‘FIRCoefficients (2x128 double)' and above configuration parameters listed above are exactly same for 2 RF cards (AD9361 (part number 696662) working RF card and AD9361 (part number 696673) NOT working RF card)
PSD plots:
Please find below PSD plot taken with samples from AD9361 (part number 696662) working RF card
Please find below PSD plot taken with samples from AD9361 (part number 696673) NOT working RF card
Time domain correlation plots
Please find below time domain correlation plots taken with samples from AD9361 (part number 696662) working RF card
Please find below time domain correlation plots taken with samples from AD9361 (part number 696673) NOT working RF card
With this can I conclude that the two AD9361 RF cards(696673 and 696665) I received with different kits have manufacturing defect? Or I am missing something?
Thanks for help in advance.
Best regards,
Syed Zeeshan Ismail,
Senior Team Leader,
Uurmi Systems.
Hyderabad- India
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