Hi !
I have a question about ADuM128x.
Do you have any test result for ADuM128x?
I already asked for other device at past but now, I want to know ADuM128x's result.
Best regards
Kawa
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(ADuM128x)Do you have some EMI test result for ADuM128x?
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counter0 doesn't work
ADSP-CM408F,Quadrature decoder (with A,B,Vcc,GND);
using counter0 and TIMER0_TMR6, in order to get position and speed .
A,B has pulses output with 90 phase difference , observed with an oscilloscope.
But, counter0 only count (+2) when the motor is open or stop, never counting when the motor is running.
And the TIMER0_TMER6_CNT counts up to 0xFFFFFFFF with an overflow signal. then TMR6 didn't work until I switch the motor.
It feels like no pulse is recognized.
the qep config program is given below , can anyone give some suggestions?
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VRMS reading greater than VPEAK
VRMS register (0x21c or 0x31c) is returning a value greater than VPEAK
register (0x226 or 0x326). I've already checked VRMSOS value and it's 0,
meaning that it adds no offset value to VRMS reading, and also I observed V
register (0x218 or 0x318) for instantaneous values of voltage and I see
that the biggest value is equivalent to VPEAK. What is odd to me is that
VRMS value is giving exactly the peak value expected for my application and
VPEAK is giving the exact voltage value in RMS. Here is an example,
VRMS: 5666625
VPEAK: 3980748
Input voltage is 220V RMS at 60Hz. The circuit for voltage channel input is
the following:
GNDA is connected to AC_PHASE because I am using a shunt resistor as a
current sensor. I wonder if there is some error in the circuit, but I've
checked another reference circuits and they're pretty similar.
The calculations to convert VRMS and VPEAK values back to real values are
the following:
For VRMS, 5666625/9032007(max value for VRMS) = 0.627, and then 0.627 * 0.5
(full-scale) = 0.313mV. This is the value applied to VN-VP pins and in my
understanding, 0.313mV is the peak value of this signal, not RMS. If I do
the same procedure to VPEAK value (I assume that the maximum value is the
same, 9032007) I get 0.440 * 0.5 = 0.220, and this should be exactly the
RMS value of the input signal.
Does that make any sense? What am I doing wrong?
PS.: I have made the question in the forum, but because I need an urgent
response I also tried via email. I am sorry for duplicates :/
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Regards,
Victor Rafael S. de Oliveira
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AD9106 EBZ outputs ~500 mV always
AD9106 EBZ outputs ~500 mV always.
I am trying to load and run the examples from the eval kit. Clock in is clean 1440 MHz. Output of clock divider is clean 180 MHz. 5 volt supply connected. J2 DAC output connected to scope. AD9106 SPI program will not display waveform RAM data. Suggestions to get output running?
Thanks,
Dave
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IIO Osc software can't find AD9361 IIO devices
Dear fellows:
Summary:
I have trouble in using IIO software in connecting to the targeted board, the IIO Software to display the following info.
No IIO devices found
but actually I have installed the linux driver of AD9361 transceiver.
Detail:
I am using a customized zynq 7000-035 FPGA based soc along with AD9361 transceiver.
With the help of the analog open source community, I have successfully built the HDL files and installed the AD9361 linux driver. The ternimal looks like this.
The sysfs of the AD9361 is going well
When I am trying to connect the target board with my IIO Software through network cable, It continue to show things like this.
p.s. The network is working fine, the host can connect to the target board through ping command.
Does anybody know how to make the IIO Osc Software functional, any information could be helpful.
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AD9162 Inconsistent JESD Link Initialization
I am using the AD9162-FMCC-EBZ eval board with the Xilinx KCU105 eval board. The JESD link fails to establish about 90% of the time after initialization and setup, but once it establishes, I get the DAC output I expect. When the link fails to establish, I continually "reset" the entire system (FPGA, Xilinx JESD core, and 9162) until the link establishes. I'm pretty sure all clocks are setup successfully; my sense is that something in the JESD link is marginal.
My startup and initialization process (on power-on and post-reset) is the following:
1. Initialize the onboard ADF4355 to output 5760 MHz. I do not believe this step ever fails.
2. Initialize the onboard AD9508. I do not believe this step ever fails.
3. Initialize the JESD FPGA core. This step involves writing registers to the core and issuing a soft reset. I do not continue past this step until the JESD core informs me that it has successfully reset.
4. Initialize the AD9162. This step involves writing data to all the registers via the SPI interface.
Here are some other data points:
1. The PLL is locking. I have an LED that lights when locked, and it is always lit
2. The values in registers 0x470, 0x471, and 0x473 contain random values when initialization and setup fails, even from retry to retry.
3. The value in register 0x472 tends to be 0xFF even during a failure to setup correctly.
4. The values in registers 0x4B0-0x4B7 are random from reset to reset.
So here is my question: What are the most likely causes of the inconsistent initialization, and what are the fixes most likely to work? Which registers should I monitor or modify? Any advice would be appreciated.
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ADV7511P DE generation
I managed to get the output to come on from our board, but it appears to reset every few seconds, with the output stopping, then starting back up again. I thought that this might be because our LCD does not have a functioning DE signal. so I changed some of the registers in an attempt to get the chip to generate its own DE signal, but it did not seem to make a difference. Have I set these registers correctly and is there any reason why the chip would keep briefly outputting a small burst of data, then stop and repeat?
0xD6, 0xC0 // force hpd on
0x01, 0x00 // Set N for 192KHz sampling and 148MHz pixel clock
0x02, 0x60 // Set N for 192KHz sampling and 148MHz pixel clock
0x03, 0x00 // Set N for 192KHz sampling and 148MHz pixel clock
0x15, 0x00 // Input 444 (RGB or YCrCb) with Separate Syncs, 44.1kHz fs
0x16, 0x60 // Output format 444, 36-bit input
0x17, 0x01 // enable DE generation
0x18, 0x46 // Disable CSC
0x38, 0x02 // 800 pixel width
0x39, 0xe0
0x3a, 0x10 // 480 pixel high
0x3B, 0xFE // Pix Rep x4
0x40, 0x80 // General control packet enable
0x41, 0x10 // power down control
0x48, 0x08 // data right justified
0x49, 0x00 // no truncation
0x4C, 0x06 // 12 bit Output
0x55, 0x00 // Set YCrCb 444 in AVinfo Frame
0x56, 0x08 // Set active format Aspect
0x96, 0x20 // HPD Interrupt clear
0x98, 0x03 // ADI Recommended Write
0x99, 0x02 // ADI Recommended Write
0x9C, 0x30 // PLL Filter R1 Value
0x9D, 0x61 // Set clock divide
0xA2, 0xA4 // ADI Recommended Write
0xA3, 0xA4 // ADI Recommended Write
0xA5, 0x04 // ADI Recommended Write
0xAB, 0x40 // ADI Recommended Write
0xAF, 0x16 // Set HDMI Mode
0xBA, 0x60 // No clock delay
0xD1, 0xFF // ADI Recommended Write
0xDE, 0xD8 // ADI Recommended Write
0xE4, 0x60 // VCO_Swing_Reference_Voltage
0xFA, 0x7D // Nbr of times to search for good phase
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EVAL01-HMC1086F10 EVM Board Fail
Our customer bough 2 set of EVAL01-HMC1086F10 to testing.
But VDD short to GND before power supply.
Do you know what happen the symptom?
Thx!
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ADL5304 Output Slowly Ramps Up When Light is Blocked on Photodiode Input
My question is about the ADL5304 Log Amplifier.
I used this Log Amp on a board design and in general it works fine. I am able to get 8 decades of dynamic range (outstanding!). The input to this Log Amp is a photodiode, an EPM705, similar or identical to the one that is used in the Application Section of the ADL5304 data sheet.
However, I observe that with no light on the photodiode, the output of the log amplifer slowly ramps up to about 2 volts. I am very careful to make sure there is absolutely no light on the photodiode.
Is this due to leakage current in the photodiode? I know that the ADL5304 has "Adaptive Bias Current" control, and I exploited that feature in my design.
I have attached the schematic here.
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BF-561 L1_Code vs L1_Cache (as code) and emulator requirements?
BF-561 running under ICE-2000 and VDSP++ 5.1.2.
My program uses L1_Code, L1_Cache (as code), L2 and Ext memories. When I change the size of a routine residing in L1_Code or L1_Cache (commenting in/out a few unused lines), code placement in L2 and Ext memories appear unchanged, but routines are shuffled between L1_Code and L1_Cache. Surprisingly, this affects the programs performance. Are not L1_Code and L1_Cache (used as code) the same?
I've also noticed that, as the number of unused words gets smaller in L1_Cache (used as code), emulating gets flakier. Does the emulator require L1 resources that are not being reflected in the map file?
Perhaps the above two issues are the same... squeezing the emulator out of resources?
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remove dc offset with servo feedback
Hi
I post a question but not show!!!.
I see some post about REMOVE DC OFFSET OF A SIGNAL.
I manipulate some scheme but can not reach target.
these schemes worked for simple analog signal.(sinusoidal signal).
I get a signal from a sensor in this pic:
this signal have a +12v and a head about 1v.frequency is about 100hz to 500hz.
i want amplify about 10 and dc offset about 5v.
I import up signal to this schematic but get distorted in some area.that area are in yellow circle in end picture. 
IN YELLOW AREA SIGNAL DISTORT.IF SIGNAL IN SOURCE GO UP, IN OUTPUT FROM THAT AMPLIFIER GO DOWN.
PLEASE HELP to solved.
sincerely
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What base OS do you reccomend for buildiing the firmware?
I am having problems building the firmware on debian 9.1 due to incompatibilities with openssl 1.1.0.
What is the linux version you have succesfully build plutsdr-fw on so I can spin up a VM at the same level?
Thanks
Peter (G4DCP)
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AD9915 questions
I looking to use a AD9915 evaluation board in our lab setup. We have a Labview FPGA that has two 48 pin DIO outputs. We were hoping to use four AD9915 boards in our setup, so two per output. From what I understand the AD9915 uses 8 address lines and 8 data lines, plus a few additional lines. Will two boards be able to function off of 48 DIO lines? Is it possible for two boards to share address lines? Also, is the 1.8V power supply required if the USB interface is not being used? Is there Labview code already in place for parallel communication? Thanks.
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AD7768 analog input range in PIN mode
I am using AD7768 in PIN mode, I set the DECx and MODEx then apply a /RESET followed by a couple of /START to set the desired sampling rate and power mode (that seems to work OK), AVDDx=5.0V, IOVDD=3.3V, REF+ = 4.096V. My analog input range is approximately 2Vpp (centered on 2.5V offset), not the expected 8.192Vpp. I have the EVAL kit and it works as expected.
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AD1938 register settings for 192khz @12.288Mhz
Hi there,
i have a custom board with AD1938 with connection to a ADAU1442 board.
MCLKI is connected to CLKOUT with 12.288MHz at ADAU1442.
What are the Register Settings on AD1938 to run the ADC and DAC at 192kHz in slave mode from 12.288MHz from MCLKI?
In DAC Control Register 0[2:1] 10 = 128 kHz/176.4 kHz/192 kHz, ok but what i have to do to select 192kHz?
In DAC Control Register 1[6] 1 = internaly generated, means from PLL in slave mode?
Thanks for your help.
Greetings,
Hans
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ADS-B question
Someone asked on the Analog Dialog Blog (but no one here, looks there), so I'm copy/pasting the question:
Thanks for your articles on " “Four Quick Steps to Production: Using Model Based Design for Software Defined Radio". It is really a great technical document.
I am trying to experiment the ADS-B based on above mentioned articles using ZED board with FMCOMMS3 as a SDR. I followed all the steps you had mentioned and downloaded all the required files from GitHub repository. I used Zynq SDR support package provided by MathWorks and loaded the SD card with the support package data generated by the Matlab 2016a.
1. Inserted the SD card in to the ZED board and powered ON.
2. Able to ping from my PC to the ZED board, configured at 192.168.3.2 and where as the PC is configured as 192.168.3.1
3. I tried to run the ad9361_modeS.m script, and i got error message like "could not connect to the IIO server"
I mailed same query to mike.donovan@mathworks.com, andrei.cozma@analog.com, di.pu@analog.com on Tue, December 27, 2016 9:59 am, But unfortunately didn't received any reply.
Please guide me in solving this issue sir.
A few images of my development are attached.
Awaiting for your reply either positive or negative.
and other pictures here
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ADR130 reference
Hi
I am thinking of using the ADR130 reference. It can supply either 1V or 0.5V depending on how the SET pin is connected (VCC or GND). My application needs 1V sometimes and 0.5V other times. Would it be possible to use an analog mux to connect the SET pin so that I can get either voltage? Or does anyone have another solution?
Thanks
Jon
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Using ADG707 for RTD Application
Hi,
I want to multiplex 8 RTD sensors into a single A-to-D (e.g. AD7124). I considered the ADG707 since it has a low ΔRON.
Do you see any problem with this solution?
thanks
Noam
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ADAU 1452 digital input methods?
Hi Everyone
I am working on the ADAU 1452 evaluation board.
How do I get more than two channels of digital input to this board for signal processing? what kind of connection available? I am wondering if optical input will take ADAT 8 channels?
Thanks
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DEMO-AD5700D2Z HART_CLK connection
Hi,
This is regarding DEMO-AD5700D2Z board. I just started programming and evaluate the performance of the ICs in-order to zero in on them. I see that HART_CLK is connected to both P2.0 and P1.0. Can someone please explain me what is the reason to connect to two pins?
Also, on a custom board, I want to connect HART_CLK to just P1.0 as I want to use P2.0 and P2.1 as I2C lines. Is it feasible?
Thanks,
Spoorthy
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