Hello, teacher, now I use AD9364 card on this chip, and now the problem is that I write the register through the SPI interface, I cannot see the wave output. The baseband section does not output any signals but just wants to measure the output of the local oscillator signal,so what registers should I write to it, please?
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How to transmit tone wave with AD9364
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AD9361 ADC Data phase offset
Hello everyone:
I use zynq and AD9361's TX1 send data , RX1 receive data , baseband data source is the default HDL project DDS , frequency is 480KHz; set internal RX LO frequency 2.3GHz , as same as Tx LO. The data rate of TX path and RX path is all 30.72MHz, so the number of sampling points in a baseband signal period is 30.72e6/480e3=64 .
But when i plot the receive data I and data Q with interval 48 baseband signal periods(3072 sampling points), i find the signal's phase has slowly offset:
when i plot the receive data I and data Q with interval 3075 sampling points, there is no phase offset.
I guess the cause of this issue is because the ADC clock and DDS clock phase offset, but when I set the DDS frequency to 0, TX LO - RX LO = 480kHz, the issue still exists, and someone can help me analyze
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AD9361 with microcontroller
Dear Dragos;
As per our new design we are trying to configure our AD9361 with micro-controller . The main problem we are facing is that the connector of AD9361 that is FMC connector we are not able to make a connection between them if there is any solution for this please let me know.
Regards
Parvez
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AD9361 data_clk始终存在相位噪声
我们现在配置AD9361，DATA CLK出现了一个问题。我需要的数据采样率为40MHz，端口模式为DUAL Port，数据速率为SDR。按照Evaluation Software生成的配置文件配置，得到的DATA_CLK频率正确，但是始终存在相位噪声，导致数据采样不准确。示波器采集的DATA_CLK信号如下：
把DC Calibration和TX Quanture Calibration去掉之后，DATA_CLK的相位噪声较小。但是校准无法完成。
按照原配置，DC校准能够完成。我想问下，为什么DC校准和TX Quanture校准会导致我DATA_CLK质量下降？
配置的文件见附件。
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Turn off power to AD9361 transmitter(s)
We have an application using the AD9361 that is receive only. We want to turn off the power to the transmitter(s) to save battery power. We have gone through the ad9361 source code, but haven't found a way to turn off the transmitter(s) power. Can someone explain which API (or code we need to write) that will turn off the transmitter(s) power on the AD9361? Thank you.
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why I can not use external reference clock ?
when use DXCO ,there is no problem, now I use external reference clock by setting 0x09[5]=1 to bypassing XO. now,I observe the pll ，they are not locked. except for 0x09， what should I do?
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AD9361 Filtering
Hello
I transmit a phase modulated (Barker modulation) signal that has a 5 MHz -3 dB frequency.
I try to filter this signal using the AD9361 FIR in order to clean the spectrum out of the Tx permitted frequency.
For some reason the AD9361 FIR does not have any effect on the Tx signal as can be observed below. I have tired several FIR variations with different bandwidth values.
What can be the reason for this issue?
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AD9361 RF VCOs tunning voltage (vtune)
Hello,
We are having trouble with some individual frequencies where the SNR is very poor (maybe 12 out of 100 for 5MHz channels). A subset of those we tracked to poor phase noise on the transmit side (using external equipment). We assume similar problems exist for the rcv and hope this accounts for all 'bad' frequencies.
In some cases we could get good SNR by using the bleed circuit (Regs 0x23c/0x27c) to move the VCO operating point away from signal ground. We monitor this by means of the thresholds in regs 0x24b/0x28b and the comparator output in regs 0x247/0x287.
There are 2 problems with this:
1) the settings are not consistent: xmt & rcv within the same unit have different vtune for the same frequency and bleed and there are differences across units as well. So the 'correct' bleed value needs to be found on the fly for each individual synthesizer.
This brings us to the second problem:
2) the steps of the comparator are very coarse, specially around signal ground (500 to 800mV), so most of the time we really can't see the effect of the bleed setting.
We did play a little also with the VCO cal offset (regs 0x238/0x278), but we weren't able to find a reliable solution.
Other than those tests, we are using the ADI table for FDD, 80MHz reference without modification. Most of the problem frequencies are between 5250 and 5450 MHz.
We need a document where the Synthesizer theory of operation is detailed so that we are able to control the cal process, or an algorithm to modify the parameters so that good performance is guaranteed for all frequencies.
Thanks, Yaron
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who can give me a synthesizer table
AD9361 RF and BB PLL Synthesizer User Guide Table 7 - Table 12 display the synthesizer tables.The value is different form that calculated by AD9361 Evaluation software(My version is 2.1.3) . who can give me a table same as calculated by Evaluation software?
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About AD9361 LNA Input Dias
Dear Support Engineer,
In AD9361 Reference Manual, it states that "The LNA input pins have DC bias (~ 0.6 Vdc) present on them and may need to be ac-coupled depending on the common-mode voltage level of the external circuit". First of all, I can not find a pin named Vdc on the data sheet, so what is the Vdc value on AD-FMCOMMS3-EBZ eval board? I use a signal generator to send a 300MHz single frequency to the AD9361 receiver - does the signal from the generator needs to be AC biased like (-2dBm to +2dBm), or should it be (0 to +4dBm)?
Thank you for your time,
Ming
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AD9364 TX/RX path latency
We have an application that is very sensitive to latency in both the TX and RX paths.
The AD9364 Reference Manual explains the latency due to the digital filters, but in addition to this latency, we are measuring an additional latency that is not explained in the data sheet or reference manual.
Our clock setup using the no-os drivers is as follows:
ad9361_set_trx_clock_chain: 960000000 480000000 240000000 120000000 60000000 60000000
ad9361_set_trx_clock_chain: 960000000 240000000 120000000 60000000 60000000 60000000
Looking at the AD9364 users guide "DIGITAL Rx BLOCK DELAY" it looks like I should be seeing a delay contribution from the digital filters of approx:
HB3 HB2 HB1
RX path (2/240M) + (2/120M) + (7/60M) = 8.3ns + 16.6ns + 116ns = 140ns
TX path (2/120M) + (2/60M) + 0 = 16.6ns + 33.8ns = 50.4ns
= 190.4ns total delay for digital filters
I am using an ILA (logic analyzer) in our FPGA to capture the TX and RX data just before clocking in/out to the AD9364. I am seeing a delay of approx. 800ns.
I know that the 190ns is only the digital filter delay. Is there a description somewhere of what the source might be for the additional ~600ns delay I am measuring?
Most importantly for our application, is there anything that can be done to reduce the latency below the 800ns we are currently seeing?
Thank you for any assistance.
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AD9361 calibration about external LO
Hello,
I am using AD9361 with external LO, dose it still need the calibration when changing the LO frequency? and what kind of calibration shoud i do ?
Best Regards
Peter You
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Question of AD9364
Hello, I used the AD9364 board on the chip used to achieve a collection of the function. Not long ago just solved the clock related issues. Now want to control the AD9364 through the ARM to send and receive functions. Will the AD9364 should be how What is the auxiliary software? Thank you!
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AD9361 can rf loopback?
By BIST document,
AD9361 can Digital data loopback like Figure 5
I wonder, RX Chain to TX Chain loopback available. like...
If data interface are perfect, this loopback can by data path connecton.
BUT, because my b'd have some problem in data path, I want to rf loopback.
I want to verify RX,TX chain, before b'd revision,
Help me.
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ADRV9361-Z7035 SDR 2x2 System-On-Module infomation
Can you tell me ADRV9361-Z7035 SDR 2x2 System-On-Module more infomation? URL is as follows:
http://www.analog.com/cn/design-center/evaluation-hardware-and-software/evaluation-boards-kits/ADRV9361-Z7035.html#eb-ov…
What is the frequency of the crystal oscillator on the board? Can the board connect the external clock? What kind of interface do the board have?
Thanks.
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Does AD9361 support outer space applications?
Does AD9361 support outer space applications? Such as picosat or micro sat?
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the AGC of AD9361 have a phase reverse problem
We found the AGC of AD9361 have a phase reverse problem,so we set D6 of the Reg 0x022, but found another problem.
when set the register 0X022= 0A , we found the phase of the Rx signal rotated by 180 degrees . see the picture next :
when set the register 0X022= 4A (D6=1) we found the signal volatile 。see the picture next :
Are there any other registers that have not been set ?
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AD9361 test
Hi! AD9361 initial success, dual port,ddr,cmos,and reg 0x017 = 1A.the DATA_CLK signal is right,but the RX_FRAME signal is always low. please help me figure out the possible reason.Thank you!
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About single-ended impedance of AD9361
As descripted In AD9361 Reference Manual UG-570， the Rx differential input impedance varies over frequency. Then what about the Rx single-ended input impedance? Is it relative to differential input impedance ---- for example, 1/2 of differential impedance, ----- or equal to about 50ohm? We need to know how to make RF single-ended input match for a dimension limited and wideband design. Thank you!
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The transmit power of AD9361 is less than normal
Hello everyone
When the AD9361 transmits a single carrier signal, the transmit signal is attenuated to 7db. Tested the power of the transmitted is 4.6dbm（my PCB board have a 15dB amplifier）, and that is smaller than the power value in the normal case . I have modified the frequency word register, the RX gain table register, the BB DC and RF DC calibration register, the TX Quadrature register, the Transmit power register. SO, In addition to the above registers, which AD9361 registers also have effect on transmit power?
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