Hello!

We are using an FMCOMMS4 board with the Zedboard SoC.

For our application, we're writing our software in C using libiio. Most of the work is based off the provided sample code, found here: libiio/ad9361-iiostream.c at master · analogdevicesinc/libiio · GitHub 

Here's the problem: if another program that uses the libiio buffers gets run (and even if it is closed, or even force-quit) then our program ceases to open buffers. Furthermore, if our program crashes or gets force-quit, the buffers are still rendered unavailable.

The only solution we've found is to reboot the SoC.  Reloading the iio kernel module is impossible (I think it was compiled into the kernel), and restarting iiod does not fix the problem. Killing all processes that could possibly be using libiio doesn't help.

Does anyone know how to fix this problem without rebooting the system?

P.S. For prosperity, I have attached our C code to this post.

Just asking before buying parts: is there a way to make a frequency division(by 10, for example) in sigma studio for the Adau1701? It seems to be doable by cutting out 9/10th of the signal by a counter, and maybe joining the parts with keeping the level, but i'm quite amateur in sounds, so it would be better to hear it from a pro! Thanks!

Hello,
I am trying to use Libiio to control the output of an AD9144 DAC. The following is a graph of the waveform I want to output (a modulated Gaussian, consisting of 4000 samples):

Target waveform: a modulated Gaussian waveform consisting of 4000 samples.
I used Libiio, to create the buffer data and pushing it to the hardware successfully:
1) Creating buffer data for 2 output channels.
2) Disabling all channels expect the ones I want to use as outputs (voltage0 and voltage1).
3) Creating a buffer for the device using iio_device_create_buffer.
4) Copying buffer data to buffer using memcpy.
5) Pushing buffer using iio_buffer_push.
I get the following from scope (I give identical data to both channels so they overlap and you see only one wave):

As you can see, the repetition period is 4 microseconds which make sense since 4000 samples sampled at 1GSPS gives a period of 4 microseconds. So far so good.
At the end of my program, I destroy the buffer using iio_buffer_destroy.

The problem comes when I want to upload another wave after outputting the first one. For example, I changed my waveform to contain 2000 samples (I also changed the standard deviation so it is easier to distinguish it from the first wave):

Now when I run my program again, I see the following on the scope:

So it seems like I am not clearing the buffer properly. A portion of the buffer being used still contains the samples from the previously uploaded data.

Now if I re-run my program several times with the new waveform (2000-sample waveform), I finally get the following outcome:

As you can see the period is now 2 microseconds which correctly corresponds to 2000 samples sampled at 1GSPS.

The problem is I want to be able to get clean signal from run to run if I change my waveform or its length. So I have three questions:
1) How can I properly clear the buffer?
2) Is there a maximum size for buffer?
3) Should I use private functions of libiio library for this purpose?

In addition, I tried to upload the waveforms using iio-oscilloscope and experienced the same problem. But the problem is not deterministic. Sometimes, it works, sometimes it doesn't.

I also used iio_buffer_cancel function, but still the problem exists.

AD9144 is hosted AD-FMCDAQ2 evaluation board hosted on Virtex-VC707 evaluation board. A microblaze hosting an IIO linux is controlling the DAC.

Thanks,
Mohsen

Hello,
I am trying to use Libiio to control the output of an AD9144 DAC. The following is a graph of the waveform I want to output (a modulated Gaussian, consisting of 4000 samples):

Target waveform: a modulated Gaussian waveform consisting of 4000 samples.
I used Libiio, to create the buffer data and pushing it to the hardware successfully:
1) Creating buffer data for 2 output channels.
2) Disabling all channels expect the ones I want to use as outputs (voltage0 and voltage1).
3) Creating a buffer for the device using iio_device_create_buffer.
4) Copying buffer data to buffer using memcpy.
5) Pushing buffer using iio_buffer_push.
I get the following from scope (I give identical data to both channels so they overlap and you see only one wave):

As you can see, the repetition period is 4 microseconds which make sense since 4000 samples sampled at 1GSPS gives a period of 4 microseconds. So far so good.
At the end of my program, I destroy the buffer using iio_buffer_destroy.

The problem comes when I want to upload another wave after outputting the first one. For example, I changed my waveform to contain 2000 samples (I also changed the standard deviation so it is easier to distinguish it from the first wave):

Now when I run my program again, I see the following on the scope:

So it seems like I am not clearing the buffer properly. A portion of the buffer being used still contains the samples from the previously uploaded data.

Now if I re-run my program several times with the new waveform (2000-sample waveform), I finally get the following outcome:

As you can see the period is now 2 microseconds which correctly corresponds to 2000 samples sampled at 1GSPS.

The problem is I want to be able to get clean signal from run to run if I change my waveform or its length. So I have three questions:
1) How can I properly clear the buffer?
2) Is there a maximum size for buffer?
3) Should I use private functions of libiio library for this purpose?

In addition, I tried to upload the waveforms using iio-oscilloscope and experienced the same problem. But the problem is not deterministic. Sometimes, it works, sometimes it doesn't.

I also used iio_buffer_cancel function, but still the problem exists.

AD9144 is hosted AD-FMCDAQ2 evaluation board hosted on Virtex-VC707 evaluation board. A microblaze hosting an IIO linux is controlling the DAC.

Thanks,
Mohsen

Hello,

I am using the attached register file with an HMC832 PLL in an attempt to lock an 80 MHz reference input to an 80 MHz output. I'm trying to get the PFD frequency to 10 kHz (as low as possible) so that I can test oscillators for micro-jumps. Having a low PFD frequency increases the time to lock, which is what I want, however my PLL never locks to 80 MHz with the attached register file, and rather hovers around 82 MHz.

Below are the outputs I get when varying the divider parameters:

• R-divider = 8000, N-divider = 288000, VCO output divider = 36  --> 82 MHz output
• R-divider = 100, N-divider = 3600, VCO output divider = 36        --> 82 MHz output
• R-divider = 50, N-divider = 1800, VCO output divider = 36          --> 80 MHz output
• R-divider = 1, N-divider = 36, VCO output divider = 36                --> 80 MHz output

Any advice as to how I can get the HMC832 to converge to an 80 MHz output with the PFD Frequency at 10kHz would be much appreciated! 

I am using ADF7030-1 EZ-KIT which has a ADuCM3029 processor on board. I am simply setting up everything so that I can actually start coding. I followed all the instructions on this webpage -

CrossCore Embedded Studio Quickstart User Guide [Analog Devices Wiki] 

The evaluation board itself does not have a debugger on-board. It needs a J-Link lite emulator for debugging. I have established all the connections and I have given the 'power on perm' command as well, to power up the board over J-Link connection.

I imported "LED_button_callback" example code from CMSIS pack manager, as instructed in above webpage instructions, for a test run and when I am trying to debug it, the console reads as follows -

Case 1: 

Open On-Chip Debugger (Analog Devices CCES 2.6.0 OpenOCD 0.9.0-g21dc5ad) 0.9.0
Licensed under GNU GPL v2
Report bugs to <processor.tools.support@analog.com>
0
Info : select transport "swd"
adapter speed: 1000 kHz
cortex_m reset_config sysresetreq
Error: unable to find CMSIS-DAP device

Since, I am using a J-Link emulator, I tried changing the interface in Debug Config to Segger J-Link.

When I did that, the console read as follows - 

Case 2:

Open On-Chip Debugger (Analog Devices CCES 2.6.0 OpenOCD 0.9.0-g21dc5ad) 0.9.0
Licensed under GNU GPL v2
Report bugs to <processor.tools.support@analog.com>
0
Info : select transport "swd"
Info : JLink SWD mode enabled
adapter speed: 1000 kHz
cortex_m reset_config sysresetreq

Error: libusb_open() failed with LIBUSB_ERROR_NOT_SUPPORTED
Error: Cannot find jlink Interface! Please check connection and permissions.

Conclusion which I have drawn are - 

Case 1: I am importing a code which is written for CMSIS adaptor interface and my laptop is not able to find that interface over J-Link emulator connection.

Case 2: I am trying to debug CMSIS code over J-Link interface that is creating those errors.

Please tell me what am I doing wrong or what am I missing?

#PS : Please keep in mind that this is my first time using this evaluation kit.

I am trying to control the AD9915 Eval board using SPI from labview. I write all registers, toggle IOUPDATE, calibrate the PLL, toggle IOUPDATE, calibrate the DDS, toggle IOUPDATE and nothing. I've been trying to replicate the process I gathered by sniffing the SPI bus with the cypress controller active, but I'm not seeing success in replicating it. Am I missing a step or a process to getting output?

I'm trying to get the ADV7612-7511P eval board to be recognized by AVES3, and Windows says the device has no driver.  The user guide says that if your board uses Advantiv USB you need the driver.  When I downloaded the zip file that supposedly contains the driver though, there is no driver there.  It is only an .inf and a .cat file, and Windows ( 7 ) does not think it is a driver.

I'm trying to get the ADV7612-7511P eval board to output some kind of HDMI signal.  I tried running the HDMI-HBR Audio ADV7612 scripts ( both 1080p and 480p ) and plugged my monitor into the output port and it just says there is no HDMI cable connected.  What am I doing wrong?

We have an ADRV9361 and an ADRV1CRR FMC carrier card.  We have a number of demos running including the FM receiver and the walkie talkie transmitter.   We also have the AD IIO scope control and can run Simulink and Matlab demos.

We would like to boot and load the ADRV9361 from power up with NO ethernet and NO JTAG connections and need some DETAILED guidance.  Questions: 

• Can you give us a simple example design that will send out a SINE wave to TX1 on the ADRV9361 at board powerup (with NO ethernet and NO JTAG connections)?
• What is read from the SD card to load the parts at powerup?  ARM code?  FPGA code?  Boot.bin?
• Do we need to use Vivado to write the flash parts on the ADRV1CRR  or ADRV9361 to get it to boot? 
• What is the exact power-up sequence of a "run from boot" scenario?  e.g. this is a guess:

1. ARM wakes and waits for fpga to program from flash. 
2. ARM Boots from SD card.  
3. ARM Writes AD9361 part with initialization.  
4. Clock from AD9361 starts and drives Zync FPGA fabric.
5. FPGA fabric starts up.

Please give us detail.  Thank you.

Hi,

I have build the project using hdl-2016-r1 branch for Arradio+Arrow SOC setup. Project was successfully build and .sof file was generated.  When i downloaded the hardware image(.sof) and run the no OS driver, I am getting error that ad9361 init faild with invalid product id.   I have probed the SPI_DI, SPI_SCLK and SPI_ENB all signal is normal but part is not giving data (no activity in SPI_DO of Arradio).

Please help me.

Regards

J S Hyanki

The ref divider output is clean (17MHz) and the N divider shows a slightly low frequency. The tuning voltage will usually be around 0.5 volts (when locked it is ~ 2.2 volts) and it draws ~ 0.5 ma. The charge pump is set for full current output but does not seem to be able to overcome the bias current.

There is a fan on the board and the chip top is ~ 35 C.

Hi.

I want to Mount the ADXRS453 LCC_V in horizontal PCB board for sensing the YAW angel.

As I detected, i need a vertical board for Yaw angel, while i have just a horizontal board !

What's your idea?

Best regards

1.I downloaded a routine from company's official website, read the program, I want to know if the gyroscope of the self-test is completed in the startup？

2.When the host receives the data of from gyroscope, how to analyze the data, whether each data to be based on the status bit to determine whether the data is valid？

3.wherther the Gyro fault  is checked  by continuous inquiries？

4.how to set the sampling frequency is suitable？

5.Can provide a practical application of the angular rate of the sample program, including self-test, data filtering etc.

I am using the AD9467 with the interposer card and the Xilinx ML605 and I want to save such a big data set with a ML605. I need to have a DMA in my system. I have the analog project running using a core DMA 5.0 but it is not posible to capture up to 80000 samples. Analog developers (csoml) have the same issue  where It is not possible to capture a so big stream with that DMA.  They think that the problem is with the Xilinx core DMA 5.0 used and recommend to use other DMA with not guaranty.   Other option could be the use of AXI DMAC.

The problem is that as I am using ML605, the Xilinx tool is fixed to 14.7 EDK. So,  I need to port the AXI DMAC to EDK14.7. I am wondering if I could try to create a new peripheral as a peripheral source, and try to integrate it into the design. (change my Xilinx DMA to the AXI_DMAC). In that case, I am not familiar with the procedure and I asking for some help

could  anybody please help me create the IP core DMAC in 14.7?

Hello,
I may have a problem with one of my PicoZed SDRs.  It seems the Ethernet PHY has an issue.  Linux boots the PHY without a problem and can read/write from/to the PHY, but anything external doesn't see any activity.  For example, basic network functions such as ping won't work.
We tried multiple carrier cards, and the problem appears to follow the SOM.  Using a new SOM fixes the problem.
Thank you for your time.

-Justin

Hi, I'm currently running the AD9371 No-OS software with the ZC706 board. Based on the behavior of the transmitter using the reference no-os code, it repeatedly transmits the data loaded in the dac_write_custom_data function similar to a cyclic dma configuration. The reference headless.c file however sets the dma type to DMA_PLDDR_FIFO which I have no idea what it does. Where can I find information about this mode of DMA?

What I'm trying to do is to time stamp the exact time when the transmitter is sending a frame (hopefully without much modification) so I'm planning to test whether the DMA_PLDDR_FIFO raises periodic interrupts every end of cyclic transfer. If it doesn't, I would like to know how this dma type work so please direct me to any documentation.

Hi All,

              We were able to create ADI reference design and test it, So, now we are planning to imrovise the design by adding some extra modules like 1G Ethernet Subsystem or 10G Ethernet subsystem, CFR, DPD Xilinx IP core, Would you recommend us to moved forward with this approch? If No, What is the way forward? 

      Please need your help, looking forward for you reply.'

Thank you

Naveen 

Good day all,

We have two AD-FMCOMMS3 FMC’s to be used on a ZC702-ADV7511 (alternatively a ZCU102). We have access to the latest software: MathWorks tools R2017a and Vivado 2017.2. The proposed MBD workflow for SDR applications shown in this 4-part article (i.e. using an IIO system object in Simulink to first stream data so as to prototype an algorithm, and thereafter using the Analog Devices BSP for MathWorks HDL Workflow Advisor to do HW/SW partitioning etc.) seems very promising to us as there is no out-of-the-box solution in the MathWorks toolchain. I do have a few concerns that might cause some problems down the line.

Here’s a few questions that I have:

1. I’ve noticed that the ZC702-FMCOMMS2/3 reference design is missing from the 2017a branch of the hdl_wa_bsp repository. Do we usually have to build our own reference design from the libraries provided or is there potential that this reference design will be added to the repository?
2. I see Vivado 2016.2 is used in the hdl_wa_bsp 2017a branch, will there be any problems upgrading this to Vivado 2017.2? Otherwise Vivado 2016.2 will do fine.
3. As part of a validation step prior to production it is useful to test the algorithm by streaming live data into your Simulink model – I’m specifically trying to run the qpsktxrx model in your Git repository (2017a branch). When running the default model (i.e. only changing the target’s IP) it connects to the target and streams data for a few second until Simulink/MATLAB freezes (similar to this thread, although the solution didn’t work for me). I cannot interrupt it once it is in this state – I stop the process using the Task Manager.
   1. Here’s the diagnostic viewer output during run-time (containing libiio versions):
      libiio_if: Connected to IP 192.168.1.76 libiio_if: Remote libiio version: 0.10, (git-dfeae09) libiio_if: Local libiio version: 0.10, (git-11b871b) libiio_if: Found 5 devices in the system libiio_if: cf-ad9361-dds-core-lpc was found in the system libiio_if: Found 4 output channels for the device cf-ad9361-dds-core-lpc libiio_if: cf-ad9361-dds-core-lpc output data channels successfully initialized libiio_if: Connected to IP 192.168.1.76 libiio_if: Remote libiio version: 0.10, (git-dfeae09) libiio_if: Local libiio version: 0.10, (git-11b871b) libiio_if: Found 5 devices in the system libiio_if: cf-ad9361-lpc was found in the system libiio_if: Found 4 input channels for the device cf-ad9361-lpc libiio_if: cf-ad9361-lpc input data channels successfully initialized libiio_if: Connected to IP 192.168.1.76 libiio_if: Remote libiio version: 0.10, (git-dfeae09) libiio_if: Local libiio version: 0.10, (git-11b871b) libiio_if: Found 5 devices in the system libiio_if: ad9361-phy was found in the system
   2. I noticed that the iio_sys_obj used in the model points to: C:\ProgramData\MATLAB\SupportPackages\R2017a\3P.instrset\analogdevices9361filterwizard.instrset\ad936x-filter-wizard-2016_R1\libiio. Although there’s a newer version available. Is that fine?
4. Will there be any issues applying the same workflow (both streaming and hw/sw co-design) for the case where we want to interact with two FMC’s simultaneously?
5. In general, are there any other potential issues that we can run into for the specific hardware/software under consideration?

Thank you in advance,

Jason