Hi, I am using the LDO Voltage Regulator ADP162 but I do not find in the datasheet if it is necessary to use a pull-down external resistor in the enable pin. In principle, this enable pin will be controlled by a GPIO pin of the MSP430G2553 MCU. Thank you.
Best regards,
Fran Martin.
Hi,
I have build the project using hdl-2016-r1 branch for Arradio+Arrow SOC setup. Project was successfully build and .sof file was generated. When i downloaded the hardware image(.sof) and run the no OS driver, I am getting error that ad9361 init faild with invalid product id. I have probed the SPI_DI, SPI_SCLK and SPI_ENB all signal is normal but part is not giving data (no activity in SPI_DO of Arradio).
Please help me.
Regards
J S Hyanki
Using ADE 7858, I am trying to read an RMS voltage for phase A, I tested this input with a 0.25V DC at PIN VAP, and I read this value: 06F10A6C after I send this command: Read_Phase_VRMS(&I2c2Handle,AVRMS,2,&RxBuffer[0],0x04,1000);
Data I read back is stored in RxBuffer, and I am using a gain of 1.
The above value( 06F10A6C) is more than the maximum value mentioned on the data sheet which is: 0x3FF6A6. Any comments on this ?
Here is how I initialized ADE7858:
Write_ADE7858_I2C(&I2c2Handle,CONFIG2,2,3,1000); //Read CONFIG2 to make sure I2C is the communication protocol used
//2-- RUN DSP
Write_ADE7858_I2C(&I2c2Handle,RUN,1,3,1000);
Write_ADE7858_I2C(&I2c2Handle,STOP,0,3,1000);
Write_ADE7858_I2C(&I2c2Handle, WTHR0,0x00FF6A6B,6,1000); //bit(2:0)=001 2 bytes for registers+ 4Bytes of data
Write_ADE7858_I2C(&I2c2Handle, WTHR1,0x00000001,6,1000); //bit(2:0)=001 2 bytes for registers+ 4Bytes of data
I need help to understand why we consistently get 1 less pixel when outputting NTSC or PAL at each resolution we have tried? When NTSC and PAL are set to 720 active pixels we only see 719 pixels on the screen. When setting NTSC to 710 we only see 709 pixels. When setting PAL to 702 we only see 701 pixels. We are sending an image that has a single pixel border outline in white with a grey background. When I reduce the image by 1 pixel I see the whole border.
We have no issues when running RGB video in graphics mode. We only have this issue in SD mode.
Thanks,
Mike
Hi,
We integrated AD9361 drivers with Petalinux 2016.2 and could get FMCOMMS3 work with ZCU706. We are now working on upgrading the development tools to Petalinux 2017.2 and we are encountering some errors while building and request you to kindly provide your inputs.
We downloaded ADI linux kernel “xcomm_zynq” from the link https://github.com/analogdevicesinc/linux. We configured the kernel as mentioned in the link http://www.wiki.xilinx.com/PetaLinux+Getting+Started and could see the device AD9361 in Device driver -> Industrial IO support->Analog to Digital converters tab. But when we build, we got the following errors:
ERROR: linux-xlnx-4.9-xilinx-v2017.2+git999-r0 do_kernel_version_sanity_check: Package Version (4.9-xilinx-v2017.2+git999) does not match of kernel being built (4.6). Please update the PV variable to match the kernel source.
ERROR: linux-xlnx-4.9-xilinx-v2017.2+git999-r0 do_kernel_version_sanity_check: Function failed: do_kernel_version_sanity_check (log file is located at /home/sat/Desktop/petalinux/memory_test/build/tmp/work/plnx_aarch64-xilinx-linux/linux-xlnx/4.9-xilinx-v2017.2+git999-r0/temp/log.do_kernel_version_sanity_check.24513)
ERROR: Logfile of failure stored in: /home/sat/Desktop/petalinux/memory_test/build/tmp/work/plnx_aarch64-xilinx-linux/linux-xlnx/4.9-xilinx-v2017.2+git999-r0/temp/log.do_kernel_version_sanity_check.24513
ERROR: Task (/home/sat/Desktop/petalinux/components/yocto/source/aarch64/layers/meta-xilinx/recipes-kernel/linux/linux-xlnx_4.9.bb:do_kernel_version_sanity_check) failed with exit code '1'
To maintain same kernel version, we downloaded ADI linux kernel version 4.9 i.e., “xcomm_zynq_4_9” and tried to configure and build the kernel. we got several errors as shown in error_log2.txt. Tried to define XILINX_DMA_IP_DMA and XILINX_DMA_IP_VDMA based on some earlier kernel version, but it resulted in even more errors.
Based on the errors and log files, could you please suggest a way of resolving them? In case any supporting information or screenshot is required, please let me know.
Best regards,
Satish
Hi,
I want to implement an Over The Air upgrade on my bare metal solution which is based on BF707 DSP.
Request to point me in correct direction and share some relevant documentation.
Thanks,
Abhishek
Attached is our measure report by the AD9363 transceiver output port, that are only reduce register 0x75 index and measure output
you will see the nonlinear curve draw ,the power control resolution is not qualified 0.25dB.
How can we get good linear?
power control resolution
I use my No-OSdriver,the ext ref clk in is10M,the 10M clk signal can be captured from clk out pin.
After config the bbpll (983.04MHz), the BBPLL is not locked.0x5e=0x00,the bbpll calibration timeout always.
what should I check?
when I run the qpsk example in ad9361_benches.slx, the EVM is bad and about -15dB. I bypass the ad9361 model and connect the baseband module directly, the EVM is about -50dB. I didn't change any default value in simulink models。How to setup the parameter or do anythingothers to promote the EVM？Thank you
I am using HMC830 PLL. I am generating 60MHZ from 100MHz source frequency. Output is locked but the power level is only -22dBm. How to increase the output power level?
Hi all,
I bumped into this IC when doing research for a MIDI project (digital 5V serial communication at 31250 baud), where I need to connect different MIDI ports to one another. The IC seemed a godsend, but then I realized that it is for analogue signals. Is there an alternative that allows this? Or is this kind of digital communication possible with this ship?
Thanks,
BC
hi,
I am using zc706 and fmcomms 4 board with no os driver for my design , i have been working on the fagc for quite some time now, i just wanted to know hoe to control the enable_agc pin that is present on the card as well as connected to the gpio module in the hdl design which can be found in system.v file . From the the reference manual it can be understood that the user can manually control this pin in order to control the lock and unlock agc . i want to try something similar to this, so can anyone help me as to how i can use this pin in no os code as i cannot find any pins describing this in parameters.h or xparameters.h file and how do i send signal on this pin. pls help me with this,thanks
regards
rahul
i am trying to implement uart project in picozed sdr kit. I am facing errors in iostandard definition in xdc though i am defining them in xdc file. Any help ?
First I need to run VCO calibration(which chooses suitable LUT available in Header file) and after that what should I do?
User Guide gave details on using SPI write instead of APIs.
I'm still struggling with the serial download for the ADuCM350.
I have now revision 0 of AN-1262. On page 3, CS is defined as
0x00 - NumberOfBytes - SumOfDataBytes
According to what I sniffed from the CM3WSD, CS should rather be defined as
0x00 - NumberOfBytes - CommandByte - SumOfAddressBytes - SumOfDataBytes
This is also what the sentence "Expressed differently, the 8-bit sum of all bytes excluding the
start ID must be 0x00." implies. It looks like there are two different definitions in the same paragraph.
Best regards, Enpa
Now I can't connect zynq7000-ADRV9371 to pc through TES, I have two question.
1.If I don't connect 30.72Mhz signal to ADRV9371-W-PCBA wether I can connect zynq7000-ADRV9371 board to pc through TES.
2. How to ensure that Port 22 (SSH) and Port 55555 (evaluation software) are not blocked by firewall software on the Ethernet connection used to communicate with the ZYNQ platform. In other word, How to set port 22 and 55555 to acces the zynq7000-ADRV9371 visit the pc.
Thank you.
The SD card need image. Is this contents in SD card right? In the second picture.
Dear Staff
I have FMCOMMS5 board along with ZC702 Xilinx FPGA. I nead to measure the phase difference between two signals at the 4 different receiver channels of the FMCOMMS5. How is this possible in Linux? Any help is Appreciated.
Regards
Hello,
I may have a problem with one of my PicoZed SDRs. It seems the Ethernet PHY has an issue. Linux boots the PHY without a problem and can read/write from/to the PHY, but anything external doesn't see any activity. For example, basic network functions such as ping won't work.
We tried multiple carrier cards, and the problem appears to follow the SOM. Using a new SOM fixes the problem.
Thank you for your time.
-Justin
This is a continuation on discussion AD9144 and Libiio - How to Clear the Buffer?
Yesterday, your team solved the problem of clearing the buffer on linux (git commit c352b21d2354d0e198c1a5da5b351682ae80e986 on branch 2016_R2:dbogdanmicroblaze: dts: vc707_daq2: Enable the PL FIFO for TX) by modifying the corresponding devicetree.
My next question was the buffer size. It was mentioned that for now, it is configured to be 16K bytes. This configuration is set in the HDL code for AD9144 (/hdl/projects/daq2/vc707/system_bd.tcl) which reads:
source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/sys_adcfifo.tcl
source $ad_hdl_dir/projects/common/xilinx/sys_dacfifo.tcl
p_sys_adcfifo [current_bd_instance .] axi_ad9680_fifo 128 16
p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 128 10
source ../common/daq2_bd.tcl
It was mentioned that p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 128 10 is setting the buffer size to be 128 * 2^10 bits = 16K bytes. daq2: zc706: Increase DAC FIFO size · analogdevicesinc/hdl@db459d9 · GitHub suggests to increase 10 to say 16 to increase the buffer size.
So I wanted to give it a try and see if I can increase the buffer size. Since, the zip file sent to me on the AD9144 and Libiio - How to Clear the Buffer? discussion was a compiled version of HDL code (system_top.bit) and a compiled version of IIO linux (simpleImage.vc707_fmcdaq2), I decided to recompile the HDL code (regenerate system_top.bit) with the same settings as 2^10 bit buffer depth (reproducing the same bitstream) and if it works then I would change it to say 2^16 bit and recompile.
So this is what I have done:
$ git clone GitHub - analogdevicesinc/hdl: HDL libraries and projects
$ cd hdl
Since the compiled buffer-cleaning-corrected linux version was 2016_r2, I tried to compile the HDL code on the master branch (which was merged from hdl_2016_r2) since I assumed they need to be compatible:
$ make daq2.vc707
Resulted in the following error (logged in the /hdl/library/axi_ad9144/vivado.log file):
# adi_ip_create axi_ad9144
ERROR: This library requires Vivado 2016.2.
while executing
"adi_ip_create axi_ad9144"
I am using Vivado 2017.2. Following some suggestions on the web, I tried to change the following two files:
/hdl/library/scripts/adi_ip.tcl: set REQUIRED_VIVADO_VERSION "2017.2"
/hdl/projects/scripts/adi_project.tcl: set REQUIRED_VIVADO_VERSION "2017.2"
This changed made compiling the library successful, but the project compilation stopped with the following error message (logged in the hdl/projects/daq2/vc707/vivado.log file):
ERROR: [BD 5-390] IP definition not found for VLNV: xilinx.com:ip:microblaze:9.6
Searching for such error, it was mentioned that IP configuration is different from Vivado version to version. But I really do not want to downgrade my Vivado to 2016.2.
Next step I did, was to checkout "hdl_2017_r1" branch:
$ git clone GitHub - analogdevicesinc/hdl: HDL libraries and projects
$ cd hdl
$ git checkout hdl_2017_r1
Although the required Vivado version for both scripts is set to "2016.4", it completed the compilation without errors:
$ make daq2.vc707
Resulted in the bitstream file /hdl/projects/daq2/vc707/daq2_vc707.runs/impl_1/system_top.bit.
So I programmed the FPGA using this bitstream and downloaded the compiled 2016_r2 linux version on the microblaze (which correctly clears the buffer):
$ xmd
XMD% fpga -f system_top.bit
XMD% connect mb mdm
XMD% dow simpleImage.vc707_fmcdaq2
XMD% con
XMD% disconnect 0
The microblaze recongnizes the DAQ, since if I ssh to the linux and ls the /sys/bus/iio/devices/ I see the devices. Using my program (or iio-oscilloscope), if I change any settings (like changing single tone frequency, scale, etc. ), I can see the changes reflected on the microblaze linux. However, I get no output from the DAC.
I though this should be a miss match between "hdl_2017_r1" and the "linux 2016_r2". Is that correct?
Is it possible to update one of the HDL branches to be compatible with Vivado 2017.2 and the linux c352b21d2354d0e198c1a5da5b351682ae80e986 commit?
Thanks,
Mohsen