i am trying to implement uart project in picozed sdr kit. I am facing errors in iostandard definition in xdc though i am defining them in xdc file. Any help ?
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uart project
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Problem debugging ADV7511 reference design with Segger J-Link
Hello everyone,
I am using your ADV7511 HDL reference design on ZC702 evaluation kit. I can't use the onboard debugger that's why I am using J-Link for downloading software on PS. For programming PL with your reference bit stream, I am using a bootable SD card created using FSBL template in Xilinx SDK.
The problem is that if I try to connect J-Link with PS after FSBL completes programming of PL (DONE LED goes green), it can't reset target with following error:
Reset delay: 0 ms
Reset type NORMAL: Toggle reset pin and halt CPU core.
Info: Cortex-A/R (reset): Re-initializing debug logic.
****** Error: Bad JTAG communication: Write to IR: Expected 0x1, got 0xF (TAP Command : 10) @ Off 0xB.
Cortex-A/R (connect): Core internal signal DBGEN is not asserted. Debugging is not possible.
If I do it without programming the PL, J-Link successfully connects and download/run the software on the PS. I want to ask that is there a way to debug your reference software on PS with JLink. Remember I am connecting J-Link cable at J58. I earlier contacted Xilinx and they replied that its Analog electronics design so they can better help.
Thanks,
Umair
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No response from KCU105 DAQ2 Bare-Metal no-OS
I successfully cloned and compiled the database for the KCU105 and FMCDAQ2 using the following:
GitHub - analogdevicesinc/hdl at hdl_2016_r2
GitHub - analogdevicesinc/no-OS at 2016_R2
Everything compiled correctly. I am just getting up to speed with SDK, so I am not sure what else I am supposed to do to see a waveform on a spectrum analyzer. I am assuming that once I program the FPGA from SDK, that a waveform shows up on OUT_1 of the DAQ2 board. Are there any other instructions other than what is briefly mentioned at the end of the bare-metal quick start guide?
Thanks,
Craig
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Changing ADC sample frequency FMCDAQ2 R2017_R1
Hi,
I got the FMCDAQ2 R2017_R1 + NO-OS dev working with DDS as source DATA, ADC and DAC are sampled at 1Ghz,
I have changed the register Clock devider register 0x10B of AD9680 (=0x01) to devide the sampling frequency of the ADC by 2, when I capture the Data from the DRAM, it is equal to zero, I tried to change also ad9680_param.lane_rate_kbps = 10000000; (putting 5Gsps instead), It didn't work also .. May be you have not checked that. Since I use the latest NO-OS dev which is not released yet, I can expect that, this soft is still not mature. My objective is to sample the ADC with mimimum sampling clock possible, I think 300 Mhz according to the datasheet. Please can you tell me how to proceed giving me kindly the list of registers I have to set .. thanks for your help, many thanks to all of you for your great support specially Istvan, Lars and Rejeesh .;
Best regards, Daoudi
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fmcDAQ2 NoOS new Release (compatible with hdl R2017_r1)
Hello,
I'm waiting for NoOS fmcdaq2 new release with (ADI Jesd204b IP) so the equivalent to HDL R2017_r1, I'm using the dev branch which is still not working completely in Loop back mode ..
thanks for your feedback
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Is AD-FMCDAQ2-EBZ DC couple or AC couple?
Is AD-FMCDAQ2-EBZ DC couple or AC couple?
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ADRV9361-Z7035 overheating issue
We have designed a custom carrier card for the ADRV9361-Z7035 that we house in a rack-mount chassis. When the chassis is closed the board overheats even though there is a fan on the chassis. We mitigated the issue by mounting a dedicated fan to blow directly on the 7035. We would like to explore the option of using a heat sink but I am having trouble locating one and I would like to avoid having to build one. Does anyone know of any good heat sink options for the ADRV9361-Z7035?
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Number of MCLK to make AD7766 reset
Hello,
I have a question about AD7766, from our customer.
The customer asks us how many MCLK clock need before /SYNC to make AD7766 reset.
Please see the attached figure.
It looks like that the /SYNC signal does not need MCLK cycle before the /SYNC goes to low.
Is this collect ?
Best regards,
ysuzuki
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VHDL code for AD5791
In my application , i am using ad5791 DAC with zc702 . please provide me any example code vhdl for ad5791 is available.
thank you in advance.
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AD9956 communication issues
I’m using an eval-AD9956 in a Windows 7 pro 32 bits box. I’m facing communication issues. Whenever I make changes on the evaluation software I load the data to the device, nevertheless if I try to read the data back, the dialog box goes back to the initial value. The I/O automatic update is enabled. The jumpers W2, W3 and W4 are set for PC control. When I start the evaluation software the initial window shows that the software is up and running. Also the ADI development tools are recognized in W7 control panel.
The USB status CR1 red led keeps blinking and the VBUS CR2 Led is always glowing green. What am I doing wrong? How can I fix this?
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Can't read data from AD7795 with Linux driver
I have a similar problem.
{
.modalias = "ad7793",
.max_speed_hz = 1000000,
.bus_num = 0,
.chip_select = 0,
.platform_data = &ad7793_pdata,
.mode = SPI_MODE_3,
.irq = gpio_to_irq(9), // Raspberry Pi SPI0_MISO is GPIO9.
}
cat /sys/bus/iio/devices/iio\:device0/name
I get "ad7793".
But
cat in_voltage0-voltage0_raw // connect 0.5v
cat in_voltage1-voltage1_raw // null
cat in_voltage2-voltage2_raw // null
I always get the same thing(7502040).
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ADuCM322i absolute ratings
I have a question about ADuCM322i.
#1, Looking at ABSOLUTE MAXIMUM RATINGS Table 9,
It says that "Any I Type Ball to GND 2 ?0.3 V to IOVDDx + 0.3 V ".
What is" Any I Type Ball ?
Best regards,
Tarzan
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ADuCM322i Reset pin
Hi there, I have a question about Reset pin.
Is it better to add external pull up resister for Reset pin or not?
According to Table 10. Pin Function Descriptions on the datasheet,
An internal pull-up resistor is included.
Please give me your opinion on this.
Best regards,
Tarzan
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How to Program AD 5781 DAC?
I would like to generate an arbitrary waveform, say a square wave or sine wave, using the AD 5781 DAC. How can I program the DAC in order to do this? I'm not sure where to start...
Thank you for the help.
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ADF4159 and ADF5901 can not lock to 24GHz
I use ADF4159 and ADF5901 to generate 24GHz signal, but it still can not lock. The structure and test result are attached below. The PFD frequency of ADF4159 is 100MHz, AUX of ADF5901 is 12GHz, the settings are attached below. I use the ADIsimPLL4.20 to design the second order or third order passive loop filter, and I tried so many times, but it is still not work. Could you give me some recommended values? Thank you very much.
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AD5933 Calibration - Bioimpedance 4 electrodes with Analog Front-End
Hi, I'm developing an circuit with AD5933, I known I need to calibrate it to get a gain factor.
I am doing a bioimpedance system, with 4 electrodes, and a frequency sweep from 50KHz to 100KHz.
These are the characteristics of my sistem:
VDD in AD5933 = 5V.
Range = Nº 1
My signal = 3Vpp
Typical Output Impedance, ZOUT = >100 Ohms
Maximum Ratio = x45
PGA gain = 1
Internal oscillator: MCLK = 16.776 MHz
fSTART = 50K Hz
∆f = 1K Hz
Increments = 50
RFB = 1K Ohm
My Questions are:
1) How do I position my Known Impedance? This Way? (Image 1), with R1 and R2. Since I have 2 current outputs and 2 inputs of the Instrumentation Amplifier.
2) How do I choose the correct value for my Known Impedance (R1 and R2)? Ideally, it's just a resistor, right? The formula of the AN-1252 does not fit for me because I do not have Zmin.
The "Current-to-voltage amplifier gain" of the AD5933 datasheet is RFB resistor?Does it need to be equal to my Known Impedance Resistor? As in AD5933 datasheet? If this is true the value of my known impedance must be 1K Ohm?
Image1
3) How do I set the gain of my Instrumentation Amplifier (INA118) for Calibration? Since I am using only 2 resistors (R1 and R2), as in the Image 1.
4) I will only use 2 frequencies in my bioimpedance calculations, 50KHz and 100KHz. Do I need to calculate 2 different gain factors for each frequency? Or should I make an average as in AD5933 datasheet?
Thank you!!
Best Regards!
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ADuCM322i power up sequence
Hi there,
I have another question on ADuCM322i.
The datasheet says that " The power-up sequence must be VDD1, IOVDDx, and AVDDx, but no
delays in the sequence are required".
Does this mean that
VDD1, IOVDDx, AVDDx shoud start up at the same time?
It's okay to start up with the following orders: 1st: VDD1, 2nd: IOVDDx, 3rd:AVDDx?
Please let me know if my understanding is correct or not.
Best regards,
Tarzan
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ADE Vpeak detection issue
Hi,
My ADE7953 is reading a lower value of Vpeak compared to VRMS. It is reading Vpeak as 148V and Vrms as 227V. I measured with multimeter and found that the RMS voltage is indeed 227V
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Debugger errors
I am using ADF7030-1 EZ-KIT which has a ADuCM3029 processor on board. I am simply setting up everything so that I can actually start coding. I followed all the instructions on this webpage -
CrossCore Embedded Studio Quickstart User Guide [Analog Devices Wiki]
The evaluation board itself does not have a debugger on-board. It needs a J-Link lite emulator for debugging. I have established all the connections and I have given the 'power on perm' command as well, to power up the board over J-Link connection.
I imported "LED_button_callback" example code from CMSIS pack manager, as instructed in above webpage instructions, for a test run and when I am trying to debug it, the console reads as follows -
Case 1:
Open On-Chip Debugger (Analog Devices CCES 2.6.0 OpenOCD 0.9.0-g21dc5ad) 0.9.0
Licensed under GNU GPL v2
Report bugs to <processor.tools.support@analog.com>
0
Info : select transport "swd"
adapter speed: 1000 kHz
cortex_m reset_config sysresetreq
Error: unable to find CMSIS-DAP device
Since, I am using a J-Link emulator, I tried changing the interface in Debug Config to Segger J-Link.
When I did that, the console read as follows -
Case 2:
Open On-Chip Debugger (Analog Devices CCES 2.6.0 OpenOCD 0.9.0-g21dc5ad) 0.9.0
Licensed under GNU GPL v2
Report bugs to <processor.tools.support@analog.com>
0
Info : select transport "swd"
Info : JLink SWD mode enabled
adapter speed: 1000 kHz
cortex_m reset_config sysresetreq
Error: libusb_open() failed with LIBUSB_ERROR_NOT_SUPPORTED
Error: Cannot find jlink Interface! Please check connection and permissions.
Conclusion which I have drawn are -
Case 1: I am importing a code which is written for CMSIS adaptor interface and my laptop is not able to find that interface over J-Link emulator connection.
Case 2: I am trying to debug CMSIS code over J-Link interface that is creating those errors.
Please tell me what am I doing wrong or what am I missing?
#PS : Please keep in mind that this is my first time using this evaluation kit.
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What is the best way to make a typical 10 band EQ
I made a 10 band stereo EQ with a medium size EQ peaking and grew the algorithm for 10 bands. I then download the filter values that I created from the filter table tool to set them to +/- 15db in 20 steps. when grown to 10 bands are the bands connected in series or parallel? if in series does it make a difference if the bands go from low to high. And, what should the Q factor be? all the same Q or different for each band (my Q's are set to 1.8 for all not sure where i got that number). Also, is it better for me to put 10 general 2nd order bandpass filters in parallel, each with a +/- 12b volume control and then merge them to make the EQ? that would be easier from a front end control to just send a volume control for each band instead of using a filter table. 
This may be just a matter of preference, but i would like to get an idea of which way is best and what type of filters to use. Thanks, PaulB
#10 Band EQ
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