Hello,
I am interested in finding an FMC board with ADC and DAC for a low latency application. I am using the FMC-DAQ2 board, and I am seeing a combined latency from ADC internal FPGA loopback to the DAC of around 400 ns. This is using a DAC and ADC sample rate of 1Gsps. The JESD204B is great for higher sample rates, but it adds a lot of cycles of latency. Please advise if you have a lower latency solution.
Thanks
I have bought the AD FMCOMMS3 module for a software defined radio for my ZC706 board and wanted to start running example designs. I installed the xilinxzynqbasedradio.mlpkginstall downloaded from here http://www.mathworks.com/matlabcentral/fileexchange/48491-communications-system-toolbox-support-package-for-xilinx-zynq-based-radio
I then ran the setup by running the commands:
>>dev = sdrdev('ZC706 and FMCOMMS2/3/4')
>>launchSetupWizard(dev)
I followed the instructions here https://www.mathworks.com/help/supportpkg/xilinxzynqbasedradio/ug/guided-host-radio-hardware-setup.html and got an error that looked like this:
I have tried looking at the common problems FAQs but none of those seemed to help. I tried to do an info and the results were:
I am unsure of what is wrong at this point if it can read data from the Zynq device but does not get data from the RF card. Is this a problem with my setup or something wrong with the RF card?
Any help would be greatly appreciated.
Hello,
In my project I get the samples (in time domain) from the receiver SDR AD9364 and I want to perform an FFT on it. So I downloaded the following projects:
https://github.com/analogdevicesinc/no-OS/ + Analog Devices Inc. HDL libraries and projects (hdl 2016r2)
https://www.xilinx.com/support/answers/58582.html
and I have run them separately with success. Afterwards I have inserted the FFT project and in particular the FFT and DMA blocks in the no-OS project, updating both FPGA block diagram (attached figure) and SDK project.
In this case the FFT is not performed and using the debug view would seem that the problems are the interrupts. In particular, the application doesn’t enter in the mm2s_isr(void* CallbackRef) and then enters in the s2mm_isr(void* CallbackRef) but the irq_status:
// Read pending interrupts
irq_status = XAxiDma_IntrGetIrq(p_dma_inst, XAXIDMA_DMA_TO_DEVICE);
is equal to zero and therefore the application remains blocked in the dma_accel_xfer function, because the g_mm2s_done flag remains to zero in the infinite loop. Attached .rar file contains the sdk No-OS project folder (with the source files).
I don’t understand the reasons because the added blocks don’t interact with Analog AD9361 blocks but they are linked to the Zynq like in the original project (https://www.xilinx.com/support/answers/58582.html).
Could you help me ? I don't know if I'm missing some steps or configurations.
Thank you, L.A.
Hello, everyone. My situation is as follows: I need to use 16 Tx channels and 16 Rx channels, but there are 2 Tx channels and 2 Rx channe in one AD9371. And, AD9371 use JESD204B to connect to FPGA board. So I need to combine 8 AD9371 boards.
However, by my requirement, I have to let all JESD204B lanes of all the 8 AD9371 boards are lane synchronization. So my question is ...
1. Can all the JESD204B lanes be lane synchronization for different AD9371 board ?
2. Does AD9371 provide any pin or function for lane synchronization on different AD9371 board ?
Thanks
Hello,
I 'm using FMCDAQ2 reference design hw R2017_R1 with no-OS (dev branch) on KC705 carrier.
The RX path (adc testmodes until data captured) seems to be correct, (automatic check of PN sequences, and I recognise the samples on the captured data.
When when I Loop back one DAC to one ADC (1 channel), I could'nt get out on the captured data, the pattern I put in the lut table defined in the dac_buffer.c. (sine_lut_1 and sine_lut_2). This Lut has a size of 2 x 1024 samples, the DAC fifo has size of 8192 samples, please can you tell me what could be the problem ? The pattern I used for example 1 tone of 50 Mhz
sine_lut_1 odd samples , sine_lut_2 even samples (total samples 2048).
Best regards
Hello,
We are using the 9371 board and are trying to configure a 2TX, 2RX lane system (no observation required). We can get the default 4TX and 2RX going using the NO-OS code.
We noticed that the FPGA JESD IP is hard coded to 4 lanes. Can we reconfigure this using software? If so, what steps are required to do this?
We have tried hard coding the FPGA JESD IP to use only 2 lanes, is this the correct method? This method did not work for us, we may be missing a configuration step.
We have changed the 9371.c file to reflect the use of only 2 deframer lanes. Does the crossbar need to be changed? Are there other parameters that need to change in the Mykonos in order to use only 2 TX lanes?
Any help on the matter would be greatly appreciated.
Thanks
I am trying to use the AD9278 with Zynq and have downloaded the reference design ML605. I can see that there's a DMA interface in the code. However, I am not able to find SPI interface for configuration, and I have implemented that.
I also would like to use the LVDS data acquisition from the reference design in ZYNQ. I do not understand what sections do I have to use. Also, if the bit alignment routine is running all the time, it seems to be based on the PN sequence. For this, I think the PN sequence test would have to be enabled in the AFE. I think this is done via the PC utility, but in my case, I guess I will have to do it via the FPGA. Please help me to understand what part of the reference code I need to use.
I have access to ZCU102 board with ES2 engineering sample and another with production silicon that would like to test with an FMCOMMS5. The provided boot files in the MPSoC Quick Start Guide seem to support ES1, and I haven't been able to get those files to boot on either board.
I opened the SDK workspace and tried to create an ARM Trusted Firmware project, and was prompted for
U-Boot Base Address
EL1 Secure Application Base Addr
EL1 Secure Application Size
Console
Is there a guide process? Will the provided U-boot and kernel work on either of my boards?
I have been trying to interface DAC AD9122-M5372-EBZ with Zynq ZC702. I find quick guide
and reference designed for ML605 with AD9122
AD9122 Evaluation Board, DAC-FMC Interposer & Xilinx ML-605 Reference Design [Analog Devices Wiki]
but both are insufficient.
I am getting 40 MHz output at y4 how default value of io_00_34_ad9361_clksel is high? How to configure ad9361 clkout?
Hello everyone,
I am using your ADV7511 HDL reference design on ZC702 evaluation kit. I can't use the onboard debugger that's why I am using J-Link for downloading software on PS. For programming PL with your reference bit stream, I am using a bootable SD card created using FSBL template in Xilinx SDK.
The problem is that if I try to connect J-Link with PS after FSBL completes programming of PL (DONE LED goes green), it can't reset target with following error:
Reset delay: 0 ms
Reset type NORMAL: Toggle reset pin and halt CPU core.
Info: Cortex-A/R (reset): Re-initializing debug logic.
****** Error: Bad JTAG communication: Write to IR: Expected 0x1, got 0xF (TAP Command : 10) @ Off 0xB.
Cortex-A/R (connect): Core internal signal DBGEN is not asserted. Debugging is not possible.
If I do it without programming the PL, J-Link successfully connects and download/run the software on the PS. I want to ask that is there a way to debug your reference software on PS with JLink. Remember I am connecting J-Link cable at J58. I earlier contacted Xilinx and they replied that its Analog electronics design so they can better help.
Thanks,
Umair
Hi
I have a question for ELECTRICAL CHARACTERISTICS at different supply voltage of ADuM141E1.
The customer need to use ADuM141E1 at VDD1=3.3V and VDD2=5V.
How can I understand for ELECTRICAL CHARACTERISTICS at this condition?
I understand that ADuM141E1 works well at different supply voltage from 1.7 to 5.5V on the data sheet.
But regarding ELECTRICAL CHARACTERISTICS in the data sheet, the condition of supply voltage is same voltage(VDD1=VDD2).
I compared ELECTRICAL CHARACTERISTICS and assumed as follow.
Is my understanding correct?
I compared ELECTRICAL CHARACTERISTICS between VDD1=VDD2=3.3V(table 3) and VDD1=VDD2=5V(table 1).
The difference of these are SWITCHING SPECIFICATIONS and Quiescent Supply Current.
The case of VDD1=3.3V and VDD2=5V:
Regarding primary side(VDD1=3.3V), IDD1(Q) refer to the max value of table 3.
Regarding secondary side(VDD2=5V), IDD2(Q) refer to the max value of table 1.
Regarding SWITCHING SPECIFICATIONS(Propagation Delay, Propagation Delay Skew and Jitter) ,these refer to larger maximum or typical value (table 3).
Please see to attachment.
Best regards
Nozawa
Hi,
I am using the ADM3077E component in harsh environment an I am concerned about indirect lightning protection.
Is there an application note including details about lightning protection of the data ports (TVS reference example...)? What is the maximum voltage that the component can withstand on its differential ports (TX & RX) without damage?
What is the maximum resistance that could be implemented in series on the diff ports without impacting the nominal operation?
Thanks for your help.
When i am trying to run plutoradioSpectralAnalysisExample always the overflow is 1 . What should I do?
hi, we have a small independent board with Hmc988 on it, which is programmed by Arduino. The input power is 0-6dBm on 50Ohm input, AC coupled which is within spec. The part programs fine but we see ~180KHz (and harmonics) spurs at the divided output (regardless of input frequency). Is this normal or was the part damaged? The supply line is well filtered.
Thanks,
Matan
Hi all,
I bumped into this IC when doing research for a MIDI project (digital 5V serial communication at 31250 baud), where I need to connect different MIDI ports to one another. The IC seemed a godsend, but then I realized that it is for analogue signals. Is there an alternative that allows this? Or is this kind of digital communication possible with this ship?
Thanks,
BC
The datasheet for the ADP8866 is very clear on part internal registers and how to read/write from them. What is missing is simple direction on which specific registers to read/write to turn on or off an LED. Usually, with parts like the ADP8866, the challenge is understanding specific register read/write sequences for standard functions (e.g. what register values to write and in what sequence to turn on an example LED or turn off an example LED). These are commonly provided in example apps or pseudo code. Is this kind of info available for the ADP8866? We plan to use the part to very simply turn on and off LEDs and (if possible) set intensity.
I have the following version of AD9671EBZ and HSC-ADC-EVALEZ boards. My software versions are:
I have the following setup files and the "AD9671 Setup Instructions Nov2014.pdf"guide to follow the steps
I use VisualAnalog to program FPGA with the “ad9671_evalez_09292014_1025am.mcs”, and the SPIController software can read and write AD9671 registers correctly.
But I cannot use VisualAnalog software to get the waveform from AD9671EBZ to PC. Here is the error I got from the software “ADC Data Capture Error: Timed out while attempting to fill FIFO(s)”.
I want to ask anybody had this similar problem before. I have followed the similar guide and steps to setup the AD9670EBZ with HSC-ADC-EVALCZ successfully with no problem at all.
I am not sure if I miss something or the board and the FPGA program have been changed. The only difference between my own setup and the guide is that I used "ad9671_evalez_09292014_1025am.mcs" instead of “ad9671_evalez06132014_0921am.mcs” to program the FPGA Virtex-6, which I can only find from this website, and I thought my version is the newer version.
Please help me to find out the problem, or send me your setup files if you have the exact setup files as the guide "AD9671 Setup Instructions Nov2014.pdf".
If there is any more information you want from me, please let me know.
Thank you very much!
I am trying to use the example MATLAB code - plutoradioSpectralAnalysisExample.
It is trying to use a JIT cache located in the Firefox C:\Program Files (x86)\Mozilla Firesfox\.... Writing to C:\Program Files (x86) causes problems with modern Windows :-
Failed to serialize JIT engine to file C:\Program Files (x86)\Mozilla Firefox\slprj\_jitprj\uj4PngAW8O3q1d7aQmmPGE.l. Make sure the disk is not full or write-protected. 'Caught exception writing bitcode to "C:\Program Files (x86)\Mozilla Firefox\slprj\_jitprj\uj4PngAW8O3q1d7aQmmPGE.l" - last system error was: Permission denied'.
Component:Simulink | Category:Model warning
An error was encountered while writing the cache for MATLAB System blocks in model 'plutoradioSpectralAnalysisExample'.
How does one control where it puts the JIT files because the side effect of this is the code runs slowly severly reducing the baseband max sample rate.
Your advice would be much apreciated.
- Peter D Hull (g4dcp)
Hi,
I am working on a project which has two decodes ADV7180 and and the outputs goes to FPGA. From the FPGA then it goes to encoder ADV7391, I am able to track the inputs(decoder) and outputs(fpga) until the encoder inputs(FPGA inputs, but the DAC output there is no waveform .Also only DAC 1 and DAC 2 is there in my design schematic. There is no DAC3
The clock is 28.6363
I have set all the registers using the I2C bus
one of the decode and the other decoder with address as 0x42
/* TX Slv Sub */
/* CntAddrAddr data */
//{0x02, 0x40, 0x11, 0x1E}, /*48 PIN*/
//{0x02, 0x40, 0x13, 0x04}, /* disable the voltage output on the XTAL1 pin and allow the ADV7180 to be clocked by a 28.63636 MHz oscillator */
{0x02, 0x40, 0x00, 0x00},
{0x02, 0x40, 0x14, 0x30}, /* ADI required write (after any INSEL write) reset clamp circuitry */
{0x02, 0x40, 0x04, 0x57}, /* enable SFL output */
{0x02, 0x40, 0x17, 0x41}, /* select SH1 chroma shaping filter */
{0x02, 0x40, 0x31, 0x02}, /* enable NEWAVMODE */
{0x02, 0x40, 0x3D, 0xA2}, /* ADI required write (optimize windowing function step 1) */
{0x02, 0x40, 0x3E, 0x6A}, /* ADI required write (optimize windowing function step 2) */
{0x02, 0x40, 0x3F, 0xA0}, /* ADI required write (optimize windowing function step 3) */
{0x02, 0x40, 0x0E, 0x80}, /* ADI required write (enable ADC step 1) */
{0x02, 0x40, 0x55, 0x81}, /* ADI required write (enable ADC step 2) */
{0x02, 0x40, 0x0E, 0x00}, /* ADI required write (enable ADC step 3) */
{0x02, 0x40, 0x52, 0x0D} /* recommended AFE Ibias setting for CVBS mode */
};
encoder register settings
/* CntAddrAddr data */
{0x02, 0x54, 0x17, 0x02},
{0x02, 0x54, 0x00, 0x12},
{0x02, 0x54, 0x01, 0x00},
{0x02, 0x54, 0x02, 0x60},
{0x02, 0x54, 0x80, 0x10},
{0x02, 0x54, 0x82, 0xC9},
{0x02, 0x54, 0x84, 0x4E},
{0x02, 0x54, 0x87, 0x20},
{0x02, 0x54, 0x88, 0x00},
{0x02, 0x54, 0x8A, 0x0C}
Please suggest if the register settings are fine