I am using the ADRV-DPD1/PCBZ Reference Design platform. This is the standard 3 card evaluation setup - Radio Card, FMC Interposer Card and the Xilinx ZC706 platform. When communicating with the AD9375 TES GUI (version 0.3.8), I can successfully control Tx 1 (I can see a tone on a spectrum analyzer, control the attenuation, etc.) However when I exit the GUI and switch to the AD9375 Embedded DPD Interface GUI (v 3.000), I can connect, load waveform but cannot turn on the Tx - i.e. I dont see anything on the spectrum analyzer. I have tried to follow the step-by-step instructions in the AD9375 SUG but no success. Any idea as to what I am doing wrong??
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AD9375 Embedded DSP Interface Issue
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UK usage of ADALM-PLUTO
I have just received my ADALM-PLUTO and have problems during the driver install.
I am in the UK on a normal Windows 10 Professional install. This stops any driver for the IIO or RNDIS being installed.
Advice on solving this would be apreciated as changing form UK settings to American ones is not really useful.
Thanks Peter D Hull (G4DCP)adalm-pluto
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Can all the JESD204B lanes be lane synchronization for different AD9371 board
Hello, everyone. My situation is as follows: I need to use 16 Tx channels and 16 Rx channels, but there are 2 Tx channels and 2 Rx channe in one AD9371. And, AD9371 use JESD204B to connect to FPGA board. So I need to combine 8 AD9371 boards.
However, by my requirement, I have to let all JESD204B lanes of all the 8 AD9371 boards are lane synchronization. So my question is ...
1. Can all the JESD204B lanes be lane synchronization for different AD9371 board ?
2. Does AD9371 provide any pin or function for lane synchronization on different AD9371 board ?
Thanks
(PS: I have post this question once, but they want me ask this question to transceiver group. I don't know is this the right way?)
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Controlling AD5372 Using 64-bit MATLAB
Hi,
I am trying to control the DAC EVAL-AD5372 from the MATLAB software environment.
I was able to do this successfully from 32bit MATLAB using the loadlibrary function and DLL ADI_CYUSB_USB4.dll found from http://ez.analog.com/thread/11105 and a wrapper I created.
However, when I try to do the same for 64bit MATLAB, the board fails to be detected. Has anyone been successful using this DLL in a 64bit application? Is it a problem of MATLAB using a specific compiler?
Thanks,
Luke
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What are the audio differences between ADV7612 and ADV7619?
Hi,
We've observed an issue when ADV7612 is fed audio/video from a certain HDMI 2.0 Source device, when the Source is outputting 1080p60 at 8bpc RGB, with 48kHz 2 channel LPCM audio. We can't reproduce this same issue with an ADV7619-based Sink device.
The ADV7619-based unit is one we have developed, and the ADV7612-based one is from another manufacturer we're working with to resolve this issue. The HDMI 2.0 Source is also a device we have developed.
- According to the developers involved on the ADV7612 device, when video + audio are sent from this device, they see DE_REGEN_LCK_RAW getting unset. However, on the ADV7619-based unit, we don't see this. (The ADV7619 is rock solid and stable, and audio/video are constant and functioning normally.)
- DE_REGEN_LCK_RAW (and the corresponding video) is stable until audio is enabled on the Source.
- DE_REGEN_LCK_RAW continues to toggle even after audio is disabled.
- If we change the Hsync pulse's front porch by 4 pixels in either direction, the ADV7612 begins to work.
- We only see this with a single Source device -- other Sources with the Hsync in the nominal location don't have this issue.
- We've tried this with two different ADV7612-based devices and two different Source units.
Is there something we should look at on the ADV7612/ADV7619 settings that we should be comparing between them that would potentially cause this? The fact that video DE becomes unstable is puzzling to us. Thanks for any help you can provide!
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HMC499LC4_Bias on/off for TDD
Dear team,
Customer is using HMC499LC4 for TDD solution(Korea 5G:28GHz band) .
She wants to control on/off using Vgg voltage for TDD and Vdd is always On.
Is there best way for device on/off?
We are looking for a your advice.
thanks
Best regards,
Josh
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AD9375 IIO scope plugin not visible
Hi, I am currently evaluating the ADRV9375 eval board. It comes with 2 SD cards:
1. One for use with Windows GUI. It runs as a Linux on my ZC706. IIO scope is installed. However, it can be used to connect the Windows GUI to the AD9375. (Image name: "AD9371 Image 20161130.img")
2. One for use as standalone with the Zync ZC706. As the version shipped was outdated, I used the newest version 2016-R2. (Image name: "2016_R2-2017_06_29.img") I prepared the SD card for use with ZC706 and AD9375. IIO Scope is installed.
In both environments, if I start IIO Scope and click "connect", I can see the ADRV9375 card. However, the plugin (basic and advanced) are not displayed. Am I doing something wrong?
With the Windows GUI, the TRX is working.
Thank you very much for your help!
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ADE9000 Temperature
I'm having a problem when reading the temperature from the ADE9000.
Following the guide on the User Guide, it says I have to read the values of temp gain, temp offset and temp rstl. Here are the following values:
temp gain: 18814
temp offset: 33444
temp rslt: 3757
The equation is: temp_rslt * ( -temp_gain / 65536) + temp_offset/32
= 3757 * ( - 18814 / 65536) + (33444/32)
= - 33.43ºC
Minus 33.43ºC is not the actual temperature so I guess either I did something wrong or the IC was not properly calibrated by the manufacturer.
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Vector FIR filter in the SHARC library
The vector FIR filter in the SHARC library has a state vector that is N+1 elements where N is the number of FIR coefficients. The first element is used as a pointer into this state delay line. My customer needs to get to the center delay element. The documentation does not tell him enough to be able to know how he might do this. Can someone please explain how to get this done
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What does setting PPI_DELAY = 0x0000 do?
Hi All,
According to the ADSP-BF537 Blackfin Processor Hardware Reference page 7-34 "It contains a count of how many PPI_CLK cycles to delay after assertion of PPI_FS1 before starting to read in or write out data."
I'd like a delay of 0, but the document says that "reset = 0x0000". So what does `PPI_DELAY = 0x0000;` actually do? What is the correct setting for a delay of 0?
FYI, I'm using a BF537, but I expect this probably applies to many BF chips.
Thanks in advance.
-Matt
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The PlutoSDR drivers don't install on my 32-bit Win-10. "The current language is not supported..." Tried US & UK English, and the .exe file claims to be language neutral.
The PlutoSDR drivers don't install on my 32-bit Win-10. "The current language is not supported..." Tried US & UK English, and the .exe file claims to be language neutral.
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Sigma Studio for Sharc move array to different section
Hi,
I'm trying to create plug in for my algorithm in which I have big static array (big delay line) which by default is put in Coeff section during linking by SigmaStudio and because of it's size it's not fit there. I wanted to move it to Data32 section. It's done via LDF or in Algorithm Designer? I try to achieve it by reserving required space in memory tab in algorithm designer but in result my array still is placed in Coeff section by SS4SH.
I use SigmaStudio 3.12 and SS4SH 2.2.0 (CCS 2.6). Target DSP ADSP-21489.
Thanks in Advance
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How to Use AD1939 and SC589?
Hi guys.
I wanna use sc589 and AD1939 hardware platform.
And I try to use AD1939 hardware initation. So I just change some code to inite sport standlone.
But it's can't work.
If i output 3khz sine wave by I2S to 4 dac, the sound work fine.
Something would be wrong, but I just can't find the problem. please give me some tip.
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ADALM PLUTO SDR
When i am trying to run plutoradioSpectralAnalysisExample always the overflow is 1 . What should I do?
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BF538 PPI first data is missing
Hi all,
I use PPI interface of BF538 processor for coomunication with FPGA. 1 frame sync GP TX mode is used. PPI clock and FS1 are generated by FPGA. 12bit width words are generated by BF processor on rising edge of clock signal.The data length is 64. There are 8 extra clocks at the communication beginning. I have set the first and the second word to 0xFFF. The rest words are 0x000.
I have an following issue. When the delay register is set to 0, all data words are OK. But if the delay register is set to not zero value, the first data generated by BF are always 0x000.
Fig1 shows signal chart with delay register set to 0. You can see that both first and second MSB bit of Tx word is set to 1. It is OK.
But in the Fig2, where the delay register is set to 1, the first data is missing, the data pulse is only 1 clock period width. All other words are correct and delayed as expected. If I set e.g. last but one word to 0xFFF, it is on its expected position. It seems the PPI DMA is not able correcty drive PPI data pins if the delay register is set to non zero value.
The PPI clock frequency is about 1.5 MHz, SSCK frequency is set to about 115 MHz.
Here is part of my code in VDSP:
*pDMA0_PERIPHERAL_MAP = PMAP_PPI;
*pDMA0_START_ADDR = (void *)led_drv_cpld_video_buff; // buff of 16bits data
*pDMA0_X_MODIFY = 2;
*pDMA0_X_COUNT = LED_DRV_CPLD_VIDEO_BUFF_SIZE;
*pDMA0_CONFIG = FLOW_AUTO | DI_EN | WDSIZE_16 | DMAEN;
ssync ();
*pPPI_CONTROL = (1 << 14) | (3 << 11) | (3 << 2) | (1 << 1);
*pPPI_COUNT = LED_DRV_CPLD_VIDEO_BUFF_SIZE - 1;
*pPPI_DELAY = 1;
ssync ();
*pSIC_IMASK0 |= DMA0_IRQ;
*pSIC_IMASK0 |= DMAC0_ERR_IRQ;
ssync ();
*pPPI_CONTROL |= (1 << 0); // start
I feel hopeless, please help.
Thank you.
Milan
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How can I install µC/USB Device Stack for CrossCore Embedded Studio
Hi all
One of my customer wants to use USB Device HID class.
So she downloaded μC/USB Device Class HID for CrossCore Embedded Studio Software via below link
http://www.analog.com/en/search.html?q=USB%20Device%20HID%20class
But when run the file asked for the serial number.
When click "Yes", license input window appears. (my PC also same situation)
She uses licensed CCES
Does she need a new license to use it?
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I have made the circuit as in CN-0217 .could any one help me with the code in which switching of ADG 849 is involved
Code regarding CN-0217
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iiod failing with unable to create buffer
I'm using IIOscilloscope to configure and debug the RF on my board. I'm using the xcomm_zynq_4_9 kernel. Now I'm getting an error when I try to do a plot.
iiod:
ERROR: Unable to create buffer
Client exited
New client connected from 0.0.0.0
ERROR: Unable to create buffer
IIOOscillos:
Error: Unable to create buffer: No such file or directory
Error: Unable to create buffer: No such file or directory
Error: Unable to create buffer: No such file or directory
Error: Unable to create buffer: No such file or directory
Error: Unable to create buffer: No such file or directory
Error: Unable to create buffer: No such file or directory
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Error "The flash loader program reported an error"
Hi support team,
I use IAR, and i got many board ( all exactly the same ) with sensors control by an ADUCM3029. All cards work very well, but two of them give me an error when i want to flash the code on the board :
"The flash loader program reported an error"
"A fatal error has occurred, the debugger will terminate"
I use a J-Link debugger, and i checked on J-link commander software ( and also manualy) the voltage of different pin, and the supply voltage, and all is correct, and the device is identified correctly.
I also tried to erase flash memory, but i didn't solve the problem.
The following line are my error message on IAR worspace :
Tue Aug 01, 2017 16:36:01: Loaded macro file: C:\Program Files (x86)\IAR Systems\Embedded Workbench 7.2\arm\config\flashloader\AnalogDevices\FlashADUCM3029.mac Tue Aug 01, 2017 16:36:01: JLINK command: ProjectFile = C:\Users\avouaill\Desktop\workspace\Puck_project_debug_Beacon_Juillet_2017\Puck_project\settings\second_test_Debug.jlink, return = 0 Tue Aug 01, 2017 16:36:01: Device "ADUCM3029" selected. Tue Aug 01, 2017 16:36:01: DLL version: V6.10c, compiled Sep 28 2016 18:45:15 Tue Aug 01, 2017 16:36:01: Firmware: J-Link Lite-ADI Rev.1 compiled Jan 7 2013 17:58:04 Tue Aug 01, 2017 16:36:01: Selecting SWD as current target interface. Tue Aug 01, 2017 16:36:01: JTAG speed is initially set to: 1000 kHz Tue Aug 01, 2017 16:36:01: Found SWD-DP with ID 0x2BA01477 Tue Aug 01, 2017 16:36:01: AP-IDR: 0x24770011, Type: AHB-AP Tue Aug 01, 2017 16:36:01: Found Cortex-M3 r2p1, Little endian. Tue Aug 01, 2017 16:36:01: FPUnit: 2 code (BP) slots and 0 literal slots Tue Aug 01, 2017 16:36:01: CoreSight components: Tue Aug 01, 2017 16:36:01: ROMTbl 0 @ E00FF000 Tue Aug 01, 2017 16:36:01: ROMTbl 0 [0]: FFF0F000, CID: B105E00D, PID: 000BB000 SCS Tue Aug 01, 2017 16:36:01: ROMTbl 0 [1]: FFF02000, CID: B105E00D, PID: 003BB002 DWT Tue Aug 01, 2017 16:36:01: ROMTbl 0 [2]: FFF03000, CID: B105E00D, PID: 002BB003 FPB Tue Aug 01, 2017 16:36:01: Hardware reset with strategy 3 was performed Tue Aug 01, 2017 16:36:01: Initial reset was performed Tue Aug 01, 2017 16:36:02: -I- execUserFlashInit! Tue Aug 01, 2017 16:36:02: 904 bytes downloaded (18.78 Kbytes/sec) Tue Aug 01, 2017 16:36:02: Loaded debugee: C:\Program Files (x86)\IAR Systems\Embedded Workbench 7.2\arm\config\flashloader\AnalogDevices\FlashADUCM3029.out Tue Aug 01, 2017 16:36:02: Target reset Tue Aug 01, 2017 16:36:02: Unloaded macro file: C:\Program Files (x86)\IAR Systems\Embedded Workbench 7.2\arm\config\flashloader\AnalogDevices\FlashADUCM3029.mac Tue Aug 01, 2017 16:36:02: The flash loader program reported an error.
Any idea let me know,
Best regards,
Florent
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AXI I2S S2MM tlast Issue on Zynq UltraSCALE+
I am using the axi_i2s_adi (hdl_2017_r1 branch) IP block in a Zynq Ultrascale+ (ZCU102 ES1 Board) Vivado 2017 design and finding tlast is always asserted. From the VHDL code I can see there is a PERIOD_LEN_REG register and modifying the values to 0x0004 0x0010 did not resolve this issue.
BCLK_DIV_RATE = 3
LRCLK_DIV_RATE = 24
The AXI I2S is configured as shown below.
PERIOD_LEN_REG = 0
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