Hello,
I try to configure UART in DMA mode by using driver coming with CCES. It works when I use the RAM version of the driver.
But it does not work when I try to use UART driver in ROM through UTILITY_ROM_UART option.
But if I configure the UART in interrupt mode, the driver still works. The silicon version of processor is 1.0.
I would like to know if anyone else has encountered same problem. Is there any solution for that?
Best Regards,
Bo Peng
Hi!
We are studying the possibility to use ADRV9364 SDR 1x1 SOM in our upcoming product.
On a product page "Pre-Release" status mentioned. What is an estimated time when comes out of pre-release phase? What price is expected?
From the data sheet:
Note 4 warns these are design figures.
I am using the 20k version in a network that has some capacitors connected to the digipot, to calibrate the phase of the circuit. The problem is the capacitances of the network the digipot is connected to are on the same order of magnitude as the digipot's.
So here are my questions:
1- What are the tolerances of such capacitances?
2- Do they vary with wiper position? If so, how much?
3- How do they vary with temperature?
Thank you in advance.
Elder.
Hello All,
I will use only the RX path of AD9363. What should I do with the unused TX related pins? Should I left them unconnected or connect to ground? Some of them are mentioned in the datasheet but not all.
I'm using Aduc7122 micro controller and wanted to test it using sample code provided for DAC.I use Keil software and Ulink2 for programming and loading code respectively. When loaded it showed Programming done,Verify OK, Flash load finished but there is no signal generated at respective DAC pin.Kindly let me know what could possibly go wrong. I have maintained same schematic connections w.r.t demo board schematic for the board designed.
I tried programming GPIO pins but that also didn't gave any output.
@Aduc7122 @ADuC71XX @ARM7TDMI
Hi.
We're a speaker company and have a new power amplifier application that's using ADAU1446 DSP with AD1939 CODEC. The amp has 4 x analogue inputs, 4 x Class D power amplifier outputs and 2 x line level outputs. We've just reached pre-production phase and have started using Sigma Studio to work out some signal routing and EQ profiles to use with our speakers. In doing that we've discovered that the noise floor of all amplifier channels will intermittently increase when cold-booted or when the DSP is reset (in our topology this causes a profile to be loaded from an EPROM). In normal operation the terminal noise of the amplifier is around 600uV, but can be as much as 4-5mV when re-booted with some profiles. If we upload any profile live to the DSP or change any parameters while the amp is running we never see this problem. Would appreciate any help you can give as we are not DSP engineers, just using Sigma Studio to get the profiles we need for our speakers.
Schematic for DSP and CODEC is attached.
Hi,
I'm trying to provide variable resistance output using AD5252( 1K Variant) to a third party device which can read the resistance output using voltage divider bias. What is the issue was I can able to see the resistance output accurately(using multimeter across B1 & W1) which was expected when no third party device connected.
But, While connecting with the third party device, the resistance getting amplified. [Eg: If i write RDAC with step 24 with the initial error of 89 Ohms. I see (89+(24x4) = 185) ohms using a multimeter across B1 & W1. But after connecting the third party device, it reads around 205 Ohms]. The increase in resistance is not linear in nature. It increases with increase in each steps of RDAC.
What may be the reason behind this kind of increase in resistance if i connect B1 & W1 with the other devices?
Hello,
I have a question about ADV8005.
I will use ADV8005 in 4K(YUV4:2:0 60P) input mode.
In this mode, is the overlay of OSD also possible?
In this mode, can 4K image with OSD overlaid output from the TTL parallel port?
Is it possible to output 4K image with OSD overlaid and FHD from HDMI in addition to the output of the TTL parallel port and to output CVBS?
Best Regards,
Mr.K
Hi:
i have some question about adv7611 audio.
video is ok but audio is not ok,it does not have voice.
the HDMI reg value 0x36——0x3a is 0x4,0x80,0x10,0x2,0x2
the bclk is 3.071M.
BUT the voice is not appear!
can you give me some suggestion!
i do not have evaluate board!!
I am getting 40 MHz output at y4 how default value of io_00_34_ad9361_clksel is high? How to configure ad9361 clkout?
I can't control the DAC correctly. Could you help me?
----------------------------------------------------
module DAC (clk1, sw, sclk, sync, sdin); input clk1; input sw; output reg [0:0] sclk; output reg [0:0] sync; output reg [0:0] sdin; reg [15:0] sdin_reg; reg [7:0] seq; reg [7:0] cnt1; reg [7:0] cnt2; always @ (negedge clk1 or negedge sw) begin if (!sw) begin
sclk <= 1;
sync <= 1;
sdin <= 1;
sdin_reg [15:0] <= 16'b0010000000000000;
seq <= 0;
cnt1 <= 15;
cnt2 <= 15;
end
else begin
case (seq)
0:begin
sync = 0;
sdin_reg [15:0] = 16'b0010000000000000;
cnt1 <= 15;
seq = seq + 1;
end
1:begin
sdin = (sdin_reg [15:0] >> cnt1) & 1;
cnt1 = cnt1 - 1;
seq = seq + 1;
end
2:begin
sclk = 0;
seq = seq + 1;
end
3:begin
sclk = 1;
if (cnt1 == 0) begin
seq = seq + 1;
end
else begin
seq = 1;
end
end
4:begin
sync = 1;
seq = 0;
end
endcase
end
end
endmodule
Hello! I have a problem with ad420 voltage output. I need VOUT=0-10V.
In my scheme i have 4 independent AD420.
From 0 to 3 volts on the AD420 (6 volts after the amplifier) everything works stably. Increasing the voltage, the output signal starts to somehow jitter (as shown on the oscillogram). I use VLL for power ADUM1401.
Why is this happening?
PS In the current version of this scheme, everything works stably and without problems.
P.S.1 I have a video - DAC AD420 problem - YouTube
Hi Engineer :
We are now debugging the ADV7611 but facing some problems,
the input source with GOPRO is fixed to 1920x1080@30,
we expected the output should be the same setting with 1920x1080@30,
but as I measure output VSync pin, the clock still measured as 60HZ,
what is the possible cause of this issue ?
all the register and edid info are programmed as attachment,
the IO & HDMI register are read as below
1. IO Map R0x6F : 01
2. IO Map R0x6A : 53
3. HDMI Map R0x04 : 23
4. HDMI Map R0x05 : B0
5. HDMI Map R0x07 : A7
VID_STD and PRIM_MODE are read as below
6. IO Map R0x00 : 08
7. IO Map R0x01: 06
If the HDMI is detected automatically, the PRIM_MODE should be set automatically ? or need manually set ?
the IO 0x00 with the value 0x08 seems not match 1920x1080P30 ?
Hello,
Can I get the output drive capability information of HMC914 ?
I am struggling with the circuit as attached since HMC914's are dying
after short time of operation. As can be seen from the attached schematic,
HMC914 is driving CML output to CML receiver. The receiver device has
50 ohm pull-up resistor to VCC3V3 power. These output and input pins
are directly connected. As a result, the output transistor of HMC914 will
experience 25ohm pull-up to the 3.3V power. If HMC914 tries to swing
0.5V, the output transistor should sink 20mA (i=V/R=0.5/25=0.02).
Is 20mA allowed current output for HMC914 ?
I cannot find any information about the rated current sink from the datasheet.
Any advice will be appreciated.
Thanks in advance.
Tae-Han
hi,
I would like to connect RF output of HMC833LP6GE to the clock in (pin CLKP and CLKN) of HMC987LP5E, please recommend the interface in between them (my frequency band is 25MHz to 6GHz).
Can I use 50MHz as clk reference for HMC883?
Since the HMC987LP5E fanouts are LVPECL interface, how can I transform them into LVDS interface?
thank you.
Could you please help on below question:
I ported my custom BF531 board's code into my custom BF514 board but I never manege to run 2D PPI DMA receive interrupt.
Here below is my custom board's Blackfin pin connections;
PORT F
PF0 - PF15 -> PPI0 - PPI15 (16 bit)
PORT G
PG5 -> PPI CLK
PG6 -> PPI FS1
PG7 -> PPI FS2
I looked https://ez.analog.com forums but there is no solved issue or I could not have found it.
You can see my sample code in the attachment.
Hi everybody,
For a university project I am currently trying to implement the famous Dattorro plate reverb (see additional info below) in C on a ADSP-21369 EZKit board.
So I started with the instructions from the EZKit manual to write the code in CCES, based on the block-based Talkthrough example code from the Board support package.
I have shared the code with you in the attachment. Please take a look at it.
(Please note that 1) I am a newcomer to DSP programming and 2) the code is not optimized in its current state.
So here and there are variables, which are not necessarily needed for the signal process, but they make it a lot easier for me to analyze in debug mode.)
I have written all the code in the files with the "_DSP"-prefix myself.
And some small edits in main.c, ADDS_21369_EzKit.h and blockProcess.c.
Everything else remains unchanged from the block based talktrough example.
Now let's get to the problem:
Like in the block based talkthrough, the basic signal processing is happening inside blockProcess.c
The function processBlock() again calls functions from the DSP_reverb.c file, where the initialization of all the filter modules and the signal processing in detail takes place and so on.
When building and debugging the program in its current state (as attached), the Debug mode seems to be working fine.
Once I comment out the remaining struct-inits inside DSP_init(), the Debug mode prevents me from stepping through breakpoints like before and randomly gives me error messages like:
"Core Hang detected on Device 0: CORE Access to a SPORT/LINK Port is hung at PC.0x090183"
Only by resetting the DSP, CrossCore is letting me into Debug mode again.
As the filter modules worked fine for me before (by having a look at several variables inside the "Expressions" view), I currently guess this is some memory-related issue.
I have activated the "External Memory" setting inside system.svc, but still there is no improvement.
Besides, the board is not putting out any sound signal on DAC4 anymore after the memory change in the svc-file.
Do you have an idea, how this could be solved?
Thank you and BR,
Martin
Additional Info:
You can find the paper of J. Dattorro here: https://ccrma.stanford.edu/~dattorro/EffectDesignPart1.pdf
(the schematic for the block signal chain can be seen on page 3)
Hi,
I want to sweep between 2100 and 2180 Mhz, 100 kHz intervals, 500 us period. I use AD 9956 synthesizer for this. And my crystal is 25 MHz. I use the TM4C123GXL DSP as a microcontroller. When I get a value of 500us, the required Vtune for Vco (CVCO55BE 2100-2200) should be between 2.00 and 3.50 volts, but I can not. When I get 500us value, I can not make a change in peak to peak value. I can not change the Period of the Vtune signal and amplitude of the Vtune signal at the same time.How can I get this signal?
Thanks.
PS: I can send my code, if you need for the answer.
Hi
i immediately need spice model for AD539
1.can Analog help in providing one, ? or if it is not
2. or if it is not avialable , is there any alternate multiplier IC which can do the same job with same bandwidth
3. or even if alterative is not available, can anyone help in actually creating a macro model for it ?? or can anyone provide me a simulation model of it ??
Hardware - ADRV-DPD1/PCBZ + Xilinx ZC-706 + Interpolator Card.
Issue - I can control the transmitter (see tone on spectrum analyzer, control attenuation, etc) using the AD9375 TES GUI (version 0.3.8). However when I connect with the AD9375 Embedded DPD Interface GUI (version 3.000), I can only connect to the setup but CANNOT turn on the transmitter.
Any idea what I am doing wrong?
Thanks
Dusty
Attached is a picture of my Hardware setup...