I use ADV7513.
Input – bt.565: 8bit on ADV7513:D[15..8], embedded sync, 576i@50 (PAL).
Settings for formatting of Video Input must be (“ADV7513_Programming_Guide.pdf”):
ID=4 // YCbCr 4:2:2, 2X clock, even dist., Embedded syncs (p.26, Table 15 )
Style=1 // 8bit, Cb/Y/Cr/Y[7:0] => Data[15:8], R0x48[4:3] = ‘00’ (evenly distributed) (p.29, Table 18)
Settings of registers (from “ADV7513_Programming_Guide.pdf”) must be:
0x15[3:0] = 0100 // 8, 10, 12 bit YCbCr 4:2:2 (2x pixel clock, embedded syncs) (p.141)
0x16[6] = 0 // Reserved. Must be set to Default Value (0)
0x16[5:4] = 11 // 8 bit
0x16[3:2] = 10 // style 1
0x16[0] = 1 ??? // ??? “Register Name” = “Output Colorspace for Black Image”
// ??? “Function”= “Input Color Space Selection”: 0 = RGB, 1 = YCbCr
Questions:
1. In your scripts “bt656-ADV7842_7511-cvbs.txt” I see for ID=4 next settings:
“72 16 71 ; 8 bits, Style 1”
That is:
0x16[6] = 1 // in Programming_Guide it is “Reserved. Must be set to Default Value (0)”
0x16[3:2] = 00 // in Programming_Guide it is “00 = Not Valid”
0x16[0] = 1
Function from Library API “ADV7513_API_Library-Rel1.55.2.1”:
ADIAPI_TxSetInputPixelFormat(8, SDR_422_EMB_SYNC_2X_CLK, 1, ALIGN_EVEN, true, false);
make settings:
72 16 32 // 0x16[3:2] = 00, in Programming_Guide it is “00 = Not Valid”
// 0x16[0] = 0
What settings for 0x16[6],[3:2],[0] must be in my case?
2. My mode is 576i, 2x pixel clock. “Programming_Guide” tell (p.32): “When using an input format where the clock is 2 or 4 times the frequency of the data, such as 480i at 27MHz, CLK Divide register bits (0x9D[3:2]) and the CLK Divide Reset Register bit (0xA4[6]) need to be set accordingly.”
What does mean “accordingly”? In all your scripts 0xA4[6]=0 – CLK divider in reset. In Main Map Table this register (0xA4) is “Fixed”…
3. Figure 6 “Sync Processing Block Diagram” (p.45).
Do is table for 0x15[3:1] correct? Mode 110x, 111x is absent in description of register 0x15[3:0] on p.141.
4. Figure 6 “Sync Processing Block Diagram” (p.45).
I use embedded sync, 0x15[3:0]=0x4(0100), 0x17[0]=0, 0x41[1]=0. That is I must have DE, Hsync, Vsync. Why it necessary to configure registers 0x30…0x34? I got video (DVI) only after configuring these registers.
5. Do is description of register 0xFA[7:5] correct (p.165)? This register mentioned with registers 0x30..0x34 in “4.3.6.2 Hsync and Vsync Generation” (p.46). What settings must be for register 0xFA in my case?
6. I didn’t find any API-functions in library “ADV7513_API_Library-Rel1.55.2.1” for settings of registers 0x30..0x34 (only macros from “ADV7513_main_map_fct.h”, like “HTX_set_VFE_HS_PLA”)… “UG-556.pdf” tell, that it must be enough only API-functions…
Thanks,
Alexander