Hello AD audio team,

There are already a couple of class-d amplifiers with o/p sense like the SSM4321 and the SSM4567.

As per the datasheet, the sensed parameters go to a 16-bit ADC. That is quite high resolution for just supervisory or house keeping.

What is the sensed parameter data used for? Output correction based on load impedance variation, by any chance? Or is it for supervisory?

I am using Class-AB amplifiers with load current sensing to drive full-range speakers. They sound very warm and 'tube' like.

I would love to have a digital engine (platform) that does this.

A sigmaDSP processor in co-ordination with a power amplifier (with output current and voltage sense) can be used to linearize loudspeaker sound variation due to its impedance variation.

I believe there was something to this tune mentioned with the SSM3525 in the AD CES 2016-17 bulletins.

Where is SSM3525? Can I get to sample it?

Thanks and regards,

Karagir.

Good Day Sir,

I am working on a project that will require deployment of a number of energy metering ICs. I used ADE7953, Single Phase, Multifunction Metering IC for the first design.
It worked very well, using RS232 interface. while looking for Polyphase Metering IC, I came across ADE9000. I was impressed with its specifications; and I found out that it met all the requirements of the system being developed.
I interfaced the chip, ADE9000, to ATMEGA328P running at 10Mhz, 3.3V. I used the driver firmware (ADE90xx_drivers) downloaded from Analog Device site. Upon power up, all the registers were read and their default values were correct.
Write-Read operations to all the registers were successful.
Writing 0x01 to register RUN (located at address 0x480) started the measurements; however, after one or two samples, the sampling would stop and the measured current, voltage, power and energies (AIRMSONE, AVRMSONE, AIRMS1012, AVRMS1012, e.t.c) would retain the last measured value.
If the RUN register is cleared and set again, the chip would pick one or two samples and stop acquisition again.
STATUS1 register was constantly read; and it always consistently returned the following values: Immediately the acquisition stopped, the MSB of STATUS1 would read 0x54; and after few seconds it would read 0xD4. And it continued to return 0xD4 until the RUN register is cleared. or reset command is issued (both Soft and hard)
This implies the following error flags were being raised: ERROR3, ERROR2, ERROR1 and ERROR0.
The datasheet recommends resetting the chip when those errors occur (especially, ERROR3, ERROR1 and ERROR0), which I did, but the problem persists. I tried to check for similar issues on EngineerZone forum. I saw that someone has raised similar issue, but the advice given is the same you have in the datasheet.
Specifically, I would be very glad if the causes, effects and solutions to these errors are comprehensively explained.
I notice that the function(s) of CONFIG5 is not captured at all in the datasheet. Also, in the firmware supplied in ADE90xx_drivers there was reference to a register named PSM2_CFG at address 0x4B8; this register was not captured in any of the documentations provided on ADE9000.

All these omissions in the documentations are understandable considering the fact that ADE9000 is an advanced metering IC and it is relatively new.
It would be highly appreciated if detailed information and solutions about the errors are provided as soon as possible.
Thanks.

Oladosu, Jamiu.

Hello,

I have a question about a calculation of a value of MOD2 and FRAC2 of ADF5355.

We can see the calculation method of them in the datasheet of ADF5355 (page 16 ~ 17 and page 34). On the other hand, we can get the value of MOD2 and FRAC2 from GUI of ADF5355 Evaluation Board Control Software by Automatic mode.

However, we got different value of MOD2 and FRAC2 from the calculation result by the datasheet and GUI software. Could you please advise me the reason of it? I understand there are many combinations of MOD2 and FRAC2 for getting same output frequency of VCO.  But, I think we should get same value of MOD2 and FRAC2 by calculate same method.

Does the GUI software use different way from the datasheet of ADF5355?

Best regards,

Akira

I have an evaluation board (model PCB 105809) for a Hittite HMC439QS16G digital phase-frequency detector.

The board behaves in a different way than specified in the data sheets and I would like to ask what can be the problems.

In particular, I'm testing it by sending two input signals, LO and RF, one of them at 5 dBm and the other one at 7 dBm. LO is at 350 MHz, while I can change the frequency of RF from about 250 MHz to 500 MHz. I have a frequency tuning resolution of 1 kHz so I can also set RF to be 350.001 MHz. My problem is that NU is always at 5 V while ND oscillates between around 3.5 V and 4.5 V. These levels are independent of the frequency difference, while the period of the oscillation of course depends on it.

My questions are:

- shouldn't the two outputs switch at some point? In the sense that NU should start to oscillate while NU should stay at 5 V?

- Shouldn't the oscillations be between 3 V and 5 V? In principle, because of the frequency difference, the phase should be swept by 2Pi.

In order to further understand the problem I have switched the two inputs, LO and RF and I saw that in this case both NU and ND are at 5 V and there is no oscillation at all. Does this mean  something doesn't work?

I have also noticed another thing that seems weird to me. The current that the board absorbs from the power supply depends on the load resistance I set on the oscilloscope on which I observe the outputs NU and ND. In particular if the load resistance is 1 MOhm I see the signal levels I mentioned before and the current going to the board is 87.9 mA, whereas if I set a load resistance of 50 Ohm for both the outputs, the current the board absorbs becomes 155 mA. Note that the board has two 5 V supply terminals and this is the global current flowing to them. Why does this happen?

Thank you very much.

Best,

Francesco

Hi there. I am having trouble defining timing constraints (Vivado 15.4, z7045 on zc706 evb) for the AD9364 digital interface. I am using the CMOS interface, have imported the Verilog into a piece of custom IP, but am having difficulty with the DDR interface. I need to operate DDR, since my bandwidth is 56MHz, and am open to using also the LVDS option, although, having only 7 cm of trace, I suspect CMOS should be reliable.

The timing diagrams in the reference manual suggest to me that the falling edge of rx_clk_in, followed by the rising edge, might be the appropriate way to acquire data, offering ample setup time, data able to be delayed by the IDELAYE2 primitive to guarantee hold time. However, the IP uses the rising edge. Delay to the clock is not implemented, suggesting stale data might be exchanged at the beginning of a burst. In CMOS mode, the device operates at the relatively low frequency of 61.44MHz, so timing should not be particularly critical. Are the constraints available, or a trade secret? :-) I notice the data is qualified, in CMOS mode, 1R1T, on both phases of rx_frame_in, 10 and 01. Can somebody explain this?

I am also puzzled by the transmit path. The valid signal does not seem to be forwarded coherently with the data, bypassing the IQ correction, for example. The receive path is implemented as expected. My system architecture requires the DMA interface to be substituted with a pair of AXI4 stream FIFO's, valid on the rx side corresponding with tvalid. On the tx side, it appears that valid data is signalled to the device interface before it has been processed.

On the other end of the FIFOs, the rx and tx streams run at 100MHz, so should maintain the feed and consumption of data. They are not stallable, in their interface to the axi_AD9361 core. They form the start and end points of typical COFDM signal paths.

Best regards

Geoff

Hi,

Would like to ask regarding on AD9361 code below. Is the first column on TX and the 2nd column on RX? If not, what are they represent?

Thank you.

ad9361Design Support AD9361/AD9363/AD9364

I want connect 3 converters AD7779 to dsp AD21478. I connected SPI of converters interface to DPI/SPI. It works good. For receiving data I would like to use interface DPI/SIP. I connected signals: DCLK, /DRDY, DOUT0, DOUT1 to DAI ports. I configured SRU, I configured DMA in Ping-Pong mode, I configured DMA IRQ - it all work good.
But I can't see data in buffer memory. I think, that problem is in configuration in register IDP_CTL0. My converters do not give dates in I2S mode, and same mechanics in SIP interface do something strange with them.
Is there any posibilities to configure this interface in such way, they do nothing with dates ? Simply store them in memory.

Regards

Grzegorz

Dear team,

Refer to the attached file(HMC598_assembly).

After assembly, Voltage was applied according to  the bias sequense.

4pcs were tested and all was over current issue.

we are looking for your advise.

thansks.

Best regards.

Josh

How i can properly terminate the pins which oscillates at the frequency fo/2 so that unwanted spurs will not occur?

Hey Guys,

i am using for a custom evaluation board the ADF5355 as a LO for a QAM modulator/demodulator. Allthough I use the programming software there is something wrong.

I want the ADF5355 to give a LO at 8,571428GHz using RFOutB and a 20MHz reference. Here is my programming sequence. Sadly I don't see my error:

/**
 * @brief          ADF5355 for 8,5714 GHz operation configuration function during power up
 * @author          Benjamin Brammer
 * @date          15.05.2017
 *
 * This function configures the ADF5355 for 8,5714 GHz operation during power up.
 *
 */
voidADF5355_8_5714GHz_config_startup(void)
{
     /* asserting CE */
     ENABLE_ADF5355;

     /* configure register 12 (default value) */
     adf5355_data[0]=1;
     adf5355_data[1]=0x041C;

     CS_ADF5355_LOW;
     HAL_SPI_Transmit_DMA(&hspi2,&adf5355_data[0],2);//transfer
     while(HAL_SPI_GetState(&hspi2)== HAL_SPI_STATE_BUSY_TX);
     CS_ADF5355_HIGH;

     /* configure register 11 (reserved! don't change!) */
     adf5355_data[0]=0x0061;
     adf5355_data[1]=0x300B;

     CS_ADF5355_LOW;
     HAL_SPI_Transmit_DMA(&hspi2,&adf5355_data[0],2);//transfer
     while(HAL_SPI_GetState(&hspi2)== HAL_SPI_STATE_BUSY_TX);
     CS_ADF5355_HIGH;

     /* configure register 10 (ADC_CLK_DIV = 50) */
     adf5355_data[0]=0x00C0;
     adf5355_data[1]=0x0CBA;          //ToDo: maybe there is a mistake here!

     CS_ADF5355_LOW;
     HAL_SPI_Transmit_DMA(&hspi2,&adf5355_data[0],2);//transfer
     while(HAL_SPI_GetState(&hspi2)== HAL_SPI_STATE_BUSY_TX);
     CS_ADF5355_HIGH;

     /* configure register 9 (VCO Band Division = 9 ;
      * ALC = 30 ; Synth lock timeout = 12 ; timeout = 34) */
     adf5355_data[0]=0x0908;
     adf5355_data[1]=0xBCC9;          // ToDo: maybe there is a mistake here!

     CS_ADF5355_LOW;
     HAL_SPI_Transmit_DMA(&hspi2,&adf5355_data[0],2);//transfer
     while(HAL_SPI_GetState(&hspi2)== HAL_SPI_STATE_BUSY_TX);
     CS_ADF5355_HIGH;

     /* configure register 8 (reserved! don't change!) */
     adf5355_data[0]=0x102D;
     adf5355_data[1]=0x0428;

     CS_ADF5355_LOW;
     HAL_SPI_Transmit_DMA(&hspi2,&adf5355_data[0],2);//transfer
     while(HAL_SPI_GetState(&hspi2)== HAL_SPI_STATE_BUSY_TX);
     CS_ADF5355_HIGH;

     /* configure register 7 (LE sync = 1 ; LDC = 2048 ;
      * LOL = 1 ; LDP = 12ns ; LDM = Fractional N) */
     adf5355_data[0]=0x1200;
     adf5355_data[1]=0x0067;          // ToDo: maybe there is a mistake here!

     CS_ADF5355_LOW;
     HAL_SPI_Transmit_DMA(&hspi2,&adf5355_data[0],2);//transfer
     while(HAL_SPI_GetState(&hspi2)== HAL_SPI_STATE_BUSY_TX);
     CS_ADF5355_HIGH;

     /* configure register 6 (gated bleed = 0 ; negative bleed = 1 ;
      * feedback select = 1 ; divider select = 1 ; CPbc = 15µA ;
      * Mute till lock = 0 ; RFoutB = On ; RFoutA = Off ; Output Power = -4dBm) */
     adf5355_data[0]=0x3500;
     adf5355_data[1]=0x8036;          // ToDo: maybe Output power is too weak and Register is double buffered!

     CS_ADF5355_LOW;
     HAL_SPI_Transmit_DMA(&hspi2,&adf5355_data[0],2);//transfer
     while(HAL_SPI_GetState(&hspi2)== HAL_SPI_STATE_BUSY_TX);
     CS_ADF5355_HIGH;

     /*DOUBLE BUFFERING!!!!!*/
     /* configure register 0 (AUTOCAL = 1 ; PrescalerValue = 1 ; INT = 214)  */
     adf5355_data[0]=0x0030;
     adf5355_data[1]=0x0D60;

     CS_ADF5355_LOW;
     HAL_SPI_Transmit_DMA(&hspi2,&adf5355_data[0],2);//transfer
     while(HAL_SPI_GetState(&hspi2)== HAL_SPI_STATE_BUSY_TX);
     CS_ADF5355_HIGH;

     /* configure register 5 (reserved! don't change!) */
     adf5355_data[0]=0x0080;
     adf5355_data[1]=0x0025;

     CS_ADF5355_LOW;
     HAL_SPI_Transmit_DMA(&hspi2,&adf5355_data[0],2);//transfer
     while(HAL_SPI_GetState(&hspi2)== HAL_SPI_STATE_BUSY_TX);
     CS_ADF5355_HIGH;

     /* configure register 4 (MUXOUT = Three-state ; RefDoubler = 0;
      * RDIV = 0 ; R Counter = 1 ; Doublebuffer = 0 ; CPcs = 0,9mA ;
      * RefMode = single ended ; Lvlselect = 3,3V ; PDp = 1 ; PWRDown = 0 ;
      * CPThree-state = 0 ; CounterReset = 0) */
     adf5355_data[0]=0x3000;
     adf5355_data[1]=0x8984;          // ToDo: maybe there is a mistake here!

     CS_ADF5355_LOW;
     HAL_SPI_Transmit_DMA(&hspi2,&adf5355_data[0],2);//transfer
     while(HAL_SPI_GetState(&hspi2)== HAL_SPI_STATE_BUSY_TX);
     CS_ADF5355_HIGH;

     /*DOUBLE BUFFERING!!!!!*/
     /* configure register 0 (AUTOCAL = 1 ; PrescalerValue = 1 ; INT = 214)  */
     adf5355_data[0]=0x0030;
     adf5355_data[1]=0x0D60;

     CS_ADF5355_LOW;
     HAL_SPI_Transmit_DMA(&hspi2,&adf5355_data[0],2);//transfer
     while(HAL_SPI_GetState(&hspi2)== HAL_SPI_STATE_BUSY_TX);
     CS_ADF5355_HIGH;

     /* configure register 3 (SDLoadReset = 0 ; PhaseResync = 0 ; PhaseAdjust = 0 ;
      * PhaseValue = 0) */
     adf5355_data[0]=0x0000;
     adf5355_data[1]=0x003;          // ToDo: maybe there is a mistake here!

     CS_ADF5355_LOW;
     HAL_SPI_Transmit_DMA(&hspi2,&adf5355_data[0],2);//transfer
     while(HAL_SPI_GetState(&hspi2)== HAL_SPI_STATE_BUSY_TX);
     CS_ADF5355_HIGH;

     /*DOUBLE BUFFERING!!!!!*/
     /* configure register 0 (AUTOCAL = 1 ; PrescalerValue = 1 ; INT = 214)  */
     adf5355_data[0]=0x0030;
     adf5355_data[1]=0x0D60;

     CS_ADF5355_LOW;
     HAL_SPI_Transmit_DMA(&hspi2,&adf5355_data[0],2);//transfer
     while(HAL_SPI_GetState(&hspi2)== HAL_SPI_STATE_BUSY_TX);
     CS_ADF5355_HIGH;

     /* configure register 2 (FRAC2 = 571 ; MOD2 = 2000) */
     adf5355_data[0]=0x9C77;
     adf5355_data[1]=0xFFF2;

     CS_ADF5355_LOW;
     HAL_SPI_Transmit_DMA(&hspi2,&adf5355_data[0],2);//transfer
     while(HAL_SPI_GetState(&hspi2)== HAL_SPI_STATE_BUSY_TX);
     CS_ADF5355_HIGH;

     /*DOUBLE BUFFERING!!!!!*/
     /* configure register 0 (AUTOCAL = 1 ; PrescalerValue = 1 ; INT = 214)  */
     adf5355_data[0]=0x0030;
     adf5355_data[1]=0x0D60;

     CS_ADF5355_LOW;
     HAL_SPI_Transmit_DMA(&hspi2,&adf5355_data[0],2);//transfer
     while(HAL_SPI_GetState(&hspi2)== HAL_SPI_STATE_BUSY_TX);
     CS_ADF5355_HIGH;

     /* configure register 1 (FRAC2 = 571 ; MOD2 = 2000) */
     adf5355_data[0]=0x0492;
     adf5355_data[1]=0x3A21;

     CS_ADF5355_LOW;
     HAL_SPI_Transmit_DMA(&hspi2,&adf5355_data[0],2);//transfer
     while(HAL_SPI_GetState(&hspi2)== HAL_SPI_STATE_BUSY_TX);
     CS_ADF5355_HIGH;

     /* configure register 0 (AUTOCAL = 1 ; PrescalerValue = 1 ; INT = 214) */
     adf5355_data[0]=0x0030;
     adf5355_data[1]=0x0D60;

     CS_ADF5355_LOW;
     HAL_SPI_Transmit_DMA(&hspi2,&adf5355_data[0],2);//transfer
     while(HAL_SPI_GetState(&hspi2)== HAL_SPI_STATE_BUSY_TX);
     CS_ADF5355_HIGH;
}

With this sequence I get a LO at 4,71394GHz at RFOUTB . Why?

I would really appreciate some help, because I don't see my fault here..

best regards

Benbjamin

Dear Support Team,

I have inserted my own IP into the existing HDL design from the Analog Devices and adapted it to my custom board. I am only concern in receiving samples so the DAC chain is left as it is. So the connection is:

ADC AD9361 IP > adc_fifo > Custom IP > adc_pack > adi dma

All works good! 

But when reading the samples in real time using the IIO i get some samples lost as the processor cannot keep up with the buffer refilling. Again, i need all this to happen in real time.

My relevant data (frame) contains 14 bytes only and i extract those bytes from the iio buffer when there is a valid flag (ie. valid message). But to get those 14 bytes i have to read thousands of samples from the buffer to get my 14 bytes (this is because the buffer is constantly refilled and i have no means to tell it to refill only at specific time instance as i dont know when is the valid flag). In other words if for example i set the buffer size to 4M samples i need to go through all those samples (in a for loop for instance) in order to extract my message even if there are maybe 1 or 2 valid messages in that buffer. Of course, i can reduce the buffer size but that doesnt help much as i will increase the overhead. 

What i really would like to be able to do is to only send the message to the buffer when that valid flag is up. I wouldnt want anything else to be sent in the meantime. This way i can significantly reduce the buffer size and make the system more optimal for real time application that i have. 

So my question is, I dont necessary fully understand how the ADC_PACK works but what is the best way to achieve that? Can this be done? Do I need to modify the ADC_PACK IP? Or can i do it more efficiently in the software?

Any comments/suggestions will be appreciated.

Many thanks

Milos

will this AD-FMCMOTCON2-EBZ motor control design be suitable for 220V 7.5Kw PMSM if we customize the driver board? The power MOSFET are rated for max 60V and suitable for driving 12-48V motors. For my motor rating, i want to know that if i replace MOSFET by power IGBT with little circuit corrections will I be able to use the same reference design( source code) given by analog device ..?

Hello,

I am looking at using the AD8436 for an application that measures RMS of both DC and DC+AC sources centered at 2.5V. I did some simulations with the AD8436 in DC coupled, single supply setup, and I am getting an unexpected result. I am not sure if it's the simulation or if this is the expected result of the part itself. I will need to better understand before continuing with the part in my design.

First, I will show an expected result: 2.5V DC input produces 0V output. That makes sense. 2.5V DC corresponds to 0V RMS: 

Now, if I apply a 3.5V DC input, I would expect a 1V output, since 3.5V DC corresponds to 1V RMS. However, I do not get this, and I have a strange value on the IGND pin. I would expect the IGND pin to be midscale 2.5V, however it is sitting at 3.362V:

Now, if I tie the IGND pin directly to a midscale 2.5V supply, I do in fact get the expected 1V output. 

I have two questions:

1. Is this the expected result? Maybe it's just a problem with the SPICE model.

2. Is it ok to drive the IGND pin to half VCC (2.5V) in the application? 

Thanks,

Mark

Hi !

I've a customer that is working with the AD9371 evaluation boards together with ZC701...

Is there any timeline to make Matlab support the COMMS5 as seamlessly as the COMMS3? I guess most of the codes should be provided by ADI although it will be a part of  Mathworks' product release

They have a temporary solution using the COMMS3 so that the project can move on. But our target is to use COMMS5 with Matlab SDR tool chain since it is more powerful especially the MIMO features.

BR Patrik

Hi support team,

   I use IAR as IDE, and I have several boars on which there are several sensors, all controls by the the ADuCM3029. I have done several tests on different boards (which are all the same), and some of them work correctly, but the others, after several tests gives me the following error message  : "Failed to get CPU status after 4 retries".

So i have this error or not, depending of the board i use.

I use a J Link debuger, and I am in CPU debug.

The following is my Error LOG.

Mon Jul 31, 2017 13:43:49: Loaded macro file: C:\Program Files (x86)\IAR Systems\Embedded Workbench 7.2\arm\config\flashloader\AnalogDevices\FlashADUCM3029.mac
Mon Jul 31, 2017 13:43:50: JLINK command: ProjectFile = C:\Users\avouaill\Desktop\workspace\Puck_project_debug_Beacon_Juillet_2017\Puck_project\settings\second_test_Debug.jlink, return = 0
Mon Jul 31, 2017 13:43:50: Device "ADUCM3029" selected.
Mon Jul 31, 2017 13:43:50: DLL version: V6.10c, compiled Sep 28 2016 18:45:15
Mon Jul 31, 2017 13:43:50: Firmware: J-Link Lite-ADI Rev.1 compiled Jan  7 2013 17:58:04
Mon Jul 31, 2017 13:43:50: Selecting SWD as current target interface.
Mon Jul 31, 2017 13:43:50: JTAG speed is initially set to: 1000 kHz
Mon Jul 31, 2017 13:43:50: Hardware reset with strategy 3 was performed
Mon Jul 31, 2017 13:43:50: Initial reset was performed
Mon Jul 31, 2017 13:44:15: Fatal error:    Session aborted!
Mon Jul 31, 2017 13:44:15: Unloaded macro file: C:\Program Files (x86)\IAR Systems\Embedded Workbench 7.2\arm\config\flashloader\AnalogDevices\FlashADUCM3029.mac

Any idea to solve this let me know,

Thank by advance.

I design electrodrive micromotor. Micromotor supply 3 sinusoid with
variable-amplitude and frequency (0-53 Hz or 0-106 Hz; 540 point on
period). Configuration chanel(1 faze): DAC AD7538 with AD8675,summarize
AD8675, filter 1 or 2 degree on AD8675, power op amp OPA549E. Amplitude
control DAC AD7538 with AD8675(supply on Ref faze DAC chanel). /LDAC use to
simultaneous generation point sinusoid.
Please verify delay your device (if delay bad, repair):
-chanel(1 faze): DAC AD7538 with AD8675 (1,5mks max DAC current rise+
(1/10MHz)*5=0,5mks AD8675); summarize AD8675
(1/10MHz)*5=0,5mks; filter on
AD8675 (1/10MHz)*5=0,5mks + setup time filter
-chanel change amplitude: DAC AD7538 with AD8675 (1,5mks max DAC current rise+
(1/10MHz)*5=0,5mks AD8675)
What is approximately nonsimultaneous in work chanel?
What is recommended for simultaneous generation point sinusoid and
more qualitative generation sinusoid?
Is there change input Ref resistance on change code DAC?
Is there error DAC AD7538 with AD8675 through line A-G AD7538 not R-2R?
AD7538 work with negative Ref?

Hi Everyone,

I would like to evaluate the AD7779 ADC, it fits my requirements perfectly and before buying the eval board I am curious how slow I can configure the ADC using the EVAL-AD7779FMCZ + EVAL-SDP-CH1Z + AD7770/AD7771/AD7779 Evaluation Software Setup?

The lowest figure I could find in the datasheet was 250Hz, is that possible to acquire data from the ADC that slow using the above mentioned setup? Does anyone have the components at hand to give it a quick try?

Many thanks,

Josef

Hello everyone,

Might you tell me what is the absolute maximum rating of IF Power Input of HMC557A mixer (when it is used in upcoversion mode)?

Many thanks.

Regards,

Antonio L.

Hi

We are using ADAU7002 with INMP621 microphones. Occasionally we have found an unusual DC offset introduced. We've also found that the condition can be forced to happen by interrupting the clock signal briefly.

The data is serialised with a number of other microphones using an Altera device. I do not know enough about that process to know if that could introduce the problem - that is a possibility that we are discussing.

Are there any know issues that could cause this? We have noticed a DC offset is normal (around 3%) but when this situation occurs there can be many different offsets (thinking about that, perhaps that suggests the serialiser?).

I am building a detector that has two output voltages that I need to divide. The numerator could have positive or negative voltage depending on the location of a laser beam on the detector. The denominator will always be positive. 

I have been trying to build a circuit to divide two voltages using the AD538 Real-Time Analog Computational Unit (ACU). The circuit diagram for two quadrant division using the AD538 is shown below and the data sheet is attached.

The trimming potentiometer labeled R2 10kOhms, should this have a center at 10kOhms or a maximum at 10kOhms? In the data sheet it says that the center of the trimming potentiometer should give a gain of 1.4, and I am not sure if that means set the resistance to 5kOhms or 10kOhms. 

Further, I have tried many values for the R2 potentiometer, but have not been able to accurately divide two voltages consistently. I am able to get a correct value for negative numerator voltages when I adjust R2, but when I change the fraction I do not get the correct value. And when I test with positive numerator voltages, I am never able to get an accurate value. The output voltage is a small negative value (I don't know why it would be negative if both voltages in the fraction are positive?) and doesn't change when I vary the input voltage values. 

Any help with the two quadrant division circuit would be greatly appreciated.

Thank you!