When I input Vcc,How much vcc current？.

The time of line voltage rising is use bigger current  than usually time.

What is the difference between the 　”Dominant State”　 and the ”TxD/RxD Data Rate 1 Mbps”?

（I　think　”Dominant State” is a transmission,and　”TxD/RxD Data Rate 1 Mbps”　is Max speed of transmission.

 So Why Current of ”Dominant State” is bigger than ”TxD/RxD Data Rate 1 Mbps” mode?)

Hi,

I could not derive this from the datasheet, but can this DSP be used as a oscillator (sinus, square, sawtooth ...) in a synth setup?

Cheers,

BC

I would like to know thermal resistance(j-b), thermal resistance(j-c) and maximum junction temperature for

Hello.

In the datasheet  P10 BW_SEL (BANDWIDTH SELECTION) MODE.
Driving the BW_SEL input signal to logic high, the amplifier provides a 3.8 GHz bandwidth. Driving the BW_SEL input
signal to logic low, the amplifier accepts input signals through a 1.5 GHz, 2-pole, low-pass filter that improves receiving
sensitivity.
The low-pass filter reduces the possible relaxation oscillation of low speed, low cost laser source by limiting the input signal bandwidth.
The BW_SEL pin has a 100 kΩ, on-chip pull-up resistor. Setting the BW_SEL pin open disables the low-pass filter.

But AN-761 ADN2892 Evaluation Board P2.

BW_SEL Mode
Driving the BW_SEL input to logic high will enable the internal 1.5 GHz low-pass filter. Switch S5 should be left
in the factory default setting position (Logic 0) for normal operation up to 4.25 Gbps or at the upper position
(Logic 1) to enable the on-chip low-pass filter.

Is the application note inconsistent with the data sheet?

Thanks

Hi all,

In the datasheet page 23 @ ADF4150HV, it say following.

MICROWAVE PLL
For best performance and to achieve maximum power transfer,
it is recommended that a differential connection be used.

In generally, what is the difference specific PLL performance between single-ended and differential connection from vco to RFin +/- ?

What is the point (superiority / inferiority) when choosing single ended input or differential input configuration with priority on PLL characteristic performance without considering physical condition (device)?
harmonics? noise? Output level? Other?

Can you give us a general comment on a simple comparison of both PLL configuration ?

Best regards,
sss

Dear Sir:

                Does ADI has provide non-OS driver of ADXL700( such as ADXL362) to our for reference?

https://github.com/analogdevicesinc/no-OS/blob/master/drivers/ADXL362/ADXL362.h

Best Regard

Jason

Hi,

I'm trying to modify ad9361_iostream.c for AD9371. Below is the modified code, when i run the elf on zc706, i get following error

Error -13 writing to channel "rf_port_select"
value may not be supported.

Please help me here to know the changes required for AD9371.

***Code***

/*
 * libiio - AD9371 IIO streaming example
 *
 * Copyright (C) 2014 IABG mbH
 * Author: Michael Feilen <feilen_at_iabg.de>
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2.1 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 **/

#include <stdbool.h>
#include <stdint.h>
#include <string.h>
#include <assert.h>
#include <signal.h>
#include <stdio.h>

#ifdef __APPLE__
#include <iio/iio.h>
#else
#include <iio.h>
#endif

/* helper macros */
#define MHZ(x) ((long long)(x*1000000.0 + .5))
#define GHZ(x) ((long long)(x*1000000000.0 + .5))

/* RX is input, TX is output */
enum iodev { RX, TX };

/* common RX and TX streaming params */
struct stream_cfg {
    long long bw_hz; // Analog banwidth in Hz
    long long fs_hz; // Baseband sample rate in Hz
    long long lo_hz; // Local oscillator frequency in Hz
    const char* rfport; // Port name
};

/* static scratch mem for strings */
static char tmpstr[64];

/* IIO structs required for streaming */
static struct iio_context *ctx   = NULL;
static struct iio_channel *rx0_i = NULL;
static struct iio_channel *rx0_q = NULL;
static struct iio_channel *tx0_i = NULL;
static struct iio_channel *tx0_q = NULL;
static struct iio_buffer  *rxbuf = NULL;
static struct iio_buffer  *txbuf = NULL;

static bool stop;

/* cleanup and exit */
static void shutdown()
{
    printf("* Destroying buffers\n");
    if (rxbuf) { iio_buffer_destroy(rxbuf); }
    if (txbuf) { iio_buffer_destroy(txbuf); }

    printf("* Disabling streaming channels\n");
    if (rx0_i) { iio_channel_disable(rx0_i); }
    if (rx0_q) { iio_channel_disable(rx0_q); }
    if (tx0_i) { iio_channel_disable(tx0_i); }
    if (tx0_q) { iio_channel_disable(tx0_q); }

    printf("* Destroying context\n");
    if (ctx) { iio_context_destroy(ctx); }
    exit(0);
}

static void handle_sig(int sig)
{
    printf("Waiting for process to finish...\n");
    stop = true;
}

/* check return value of attr_write function */
static void errchk(int v, const char* what) {
     if (v < 0) { fprintf(stderr, "Error %d writing to channel \"%s\"\nvalue may not be supported.\n", v, what); shutdown(); }
}

/* write attribute: long long int */
static void wr_ch_lli(struct iio_channel *chn, const char* what, long long val)
{
    errchk(iio_channel_attr_write_longlong(chn, what, val), what);
}

/* write attribute: string */
static void wr_ch_str(struct iio_channel *chn, const char* what, const char* str)
{
    errchk(iio_channel_attr_write(chn, what, str), what);
}

/* helper function generating channel names */
static char* get_ch_name(const char* type, int id)
{
    snprintf(tmpstr, sizeof(tmpstr), "%s%d", type, id);
    return tmpstr;
}

/* returns ad9371 phy device */
static struct iio_device* get_ad9371_phy(struct iio_context *ctx)
{
    struct iio_device *dev =  iio_context_find_device(ctx, "ad9371-phy");
    assert(dev && "No ad9371-phy found");
    return dev;
}

/* finds AD9371 streaming IIO devices */
static bool get_ad9371_stream_dev(struct iio_context *ctx, enum iodev d, struct iio_device **dev)
{
    switch (d) {
    case TX: *dev = iio_context_find_device(ctx, "axi-ad9371-tx-hpc"); return *dev != NULL;
    case RX: *dev = iio_context_find_device(ctx, "axi-ad9371-rx-hpc");  return *dev != NULL;
    default: assert(0); return false;
    }
}

/* finds AD9371 streaming IIO channels */
static bool get_ad9371_stream_ch(struct iio_context *ctx, enum iodev d, struct iio_device *dev, int chid, struct iio_channel **chn)
{
    *chn = iio_device_find_channel(dev, get_ch_name("voltage", chid), d == TX);
    if (!*chn)
        *chn = iio_device_find_channel(dev, get_ch_name("altvoltage", chid), d == TX);
    return *chn != NULL;
}

/* finds AD9371 phy IIO configuration channel with id chid */
static bool get_phy_chan(struct iio_context *ctx, enum iodev d, int chid, struct iio_channel **chn)
{
    switch (d) {
    case RX: *chn = iio_device_find_channel(get_ad9371_phy(ctx), get_ch_name("voltage", chid), false); return *chn != NULL;
    case TX: *chn = iio_device_find_channel(get_ad9371_phy(ctx), get_ch_name("voltage", chid), true);  return *chn != NULL;
    default: assert(0); return false;
    }
}

/* finds AD9371 local oscillator IIO configuration channels */
static bool get_lo_chan(struct iio_context *ctx, enum iodev d, struct iio_channel **chn)
{
    switch (d) {
     // LO chan is always output, i.e. true
    case RX: *chn = iio_device_find_channel(get_ad9371_phy(ctx), get_ch_name("altvoltage", 0), true); return *chn != NULL;
    case TX: *chn = iio_device_find_channel(get_ad9371_phy(ctx), get_ch_name("altvoltage", 1), true); return *chn != NULL;
    default: assert(0); return false;
    }
}

/* applies streaming configuration through IIO */
bool cfg_ad9372_streaming_ch(struct iio_context *ctx, struct stream_cfg *cfg, enum iodev type, int chid)
{
    struct iio_channel *chn = NULL;

    // Configure phy and lo channels
    printf("* Acquiring AD9371 phy channel %d\n", chid);
    if (!get_phy_chan(ctx, type, chid, &chn)) {    return false; }
    wr_ch_str(chn, "rf_port_select",     cfg->rfport);
    wr_ch_lli(chn, "rf_bandwidth",       cfg->bw_hz);
    wr_ch_lli(chn, "sampling_frequency", cfg->fs_hz);

    // Configure LO channel
    printf("* Acquiring AD9371 %s lo channel\n", type == TX ? "TX" : "RX");
    if (!get_lo_chan(ctx, type, &chn)) { return false; }
    wr_ch_lli(chn, "frequency", cfg->lo_hz);
    return true;
}

/* simple configuration and streaming */
int main (int argc, char **argv)
{
    // Streaming devices
    struct iio_device *tx;
    struct iio_device *rx;

    // RX and TX sample counters
    size_t nrx = 0;
    size_t ntx = 0;

    // Stream configurations
    struct stream_cfg rxcfg;
    struct stream_cfg txcfg;

    // Listen to ctrl+c and assert
    signal(SIGINT, handle_sig);

    // RX stream config
    rxcfg.bw_hz = MHZ(100);   // 2 MHz rf bandwidth
    rxcfg.fs_hz = MHZ(122.88);   // 2.5 MS/s rx sample rate
    rxcfg.lo_hz = MHZ(760); // 2.5 GHz rf frequency
    rxcfg.rfport = "A_BALANCED"; // port A (select for rf freq.)

    // TX stream config
    txcfg.bw_hz = MHZ(100); // 1.5 MHz rf bandwidth
    txcfg.fs_hz = MHZ(122.88);   // 2.5 MS/s tx sample rate
    txcfg.lo_hz = MHZ(760); // 2.5 GHz rf frequency
    txcfg.rfport = "A"; // port A (select for rf freq.)

    printf("* Acquiring IIO context\n");
    assert((ctx = iio_create_default_context()) && "No context");
    assert(iio_context_get_devices_count(ctx) > 0 && "No devices");

    printf("* Acquiring AD9371 streaming devices\n");
    assert(get_ad9371_stream_dev(ctx, TX, &tx) && "No tx dev found");
    assert(get_ad9371_stream_dev(ctx, RX, &rx) && "No rx dev found");

    printf("* Configuring AD9371 for streaming\n");
    assert(cfg_ad9371_streaming_ch(ctx, &rxcfg, RX, 0) && "RX port 0 not found");
    assert(cfg_ad9371_streaming_ch(ctx, &txcfg, TX, 0) && "TX port 0 not found");

    printf("* Initializing AD9371 IIO streaming channels\n");
    assert(get_ad9371_stream_ch(ctx, RX, rx, 0, &rx0_i) && "RX chan i not found");
    assert(get_ad9371_stream_ch(ctx, RX, rx, 1, &rx0_q) && "RX chan q not found");
    assert(get_ad9371_stream_ch(ctx, TX, tx, 0, &tx0_i) && "TX chan i not found");
    assert(get_ad9371_stream_ch(ctx, TX, tx, 1, &tx0_q) && "TX chan q not found");

    printf("* Enabling IIO streaming channels\n");
    iio_channel_enable(rx0_i);
    iio_channel_enable(rx0_q);
    iio_channel_enable(tx0_i);
    iio_channel_enable(tx0_q);

    printf("* Creating non-cyclic IIO buffers with 1 MiS\n");
    rxbuf = iio_device_create_buffer(rx, 1024*1024, false);
    if (!rxbuf) {
        perror("Could not create RX buffer");
        shutdown();
    }
    txbuf = iio_device_create_buffer(tx, 1024*1024, false);
    if (!txbuf) {
        perror("Could not create TX buffer");
        shutdown();
    }

    printf("* Starting IO streaming (press CTRL+C to cancel)\n");
    while (!stop)
    {
        ssize_t nbytes_rx, nbytes_tx;
        void *p_dat, *p_end;
        ptrdiff_t p_inc;

        // Schedule TX buffer
        nbytes_tx = iio_buffer_push(txbuf);
        if (nbytes_tx < 0) { printf("Error pushing buf %d\n", (int) nbytes_tx); shutdown(); }

        // Refill RX buffer
        nbytes_rx = iio_buffer_refill(rxbuf);
        if (nbytes_rx < 0) { printf("Error refilling buf %d\n",(int) nbytes_rx); shutdown(); }

        // READ: Get pointers to RX buf and read IQ from RX buf port 0
        p_inc = iio_buffer_step(rxbuf);
        p_end = iio_buffer_end(rxbuf);
        for (p_dat = iio_buffer_first(rxbuf, rx0_i); p_dat < p_end; p_dat += p_inc) {
            // Example: swap I and Q
            const int16_t i = ((int16_t*)p_dat)[0]; // Real (I)
            const int16_t q = ((int16_t*)p_dat)[1]; // Imag (Q)
            ((int16_t*)p_dat)[0] = q;
            ((int16_t*)p_dat)[1] = i;
        }

        // WRITE: Get pointers to TX buf and write IQ to TX buf port 0
        p_inc = iio_buffer_step(txbuf);
        p_end = iio_buffer_end(txbuf);
        for (p_dat = iio_buffer_first(txbuf, tx0_i); p_dat < p_end; p_dat += p_inc) {
            // Example: fill with zeros
            // 12-bit sample needs to be MSB alligned so shift by 4
            // https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/software/basic_iq_datafiles#binary_format
            ((int16_t*)p_dat)[0] = 0 << 4; // Real (I)
            ((int16_t*)p_dat)[1] = 0 << 4; // Imag (Q)
        }

        // Sample counter increment and status output
        nrx += nbytes_rx / iio_device_get_sample_size(rx);
        ntx += nbytes_tx / iio_device_get_sample_size(tx);
        printf("\tRX %8.2f MSmp, TX %8.2f MSmp\n", nrx/1e6, ntx/1e6);
    }

    shutdown();

    return 0;
}

Hello,

I used HMC914 for high speed clock input stage circuit as attached.

When there is no input (no signal connected to the input), the RSSI value is 2.0V and

the LOS is high (3.3V). Then, I tied the two INP & INN pins with jumper cable, but the

RSSI value is the same (2.0V). I replaced the HMC914 device, but the same result I checked.

Any recommendation to debug the current status ?

Thanks in advance.

Tae-Han

Hello,

I am looking at using the AD8436 for an application that measures RMS of both DC and DC+AC sources centered at 2.5V. I did some simulations with the AD8436 in DC coupled, single supply setup, and I am getting an unexpected result. I am not sure if it's the simulation or if this is the expected result of the part itself. I will need to better understand before continuing with the part in my design.

First, I will show an expected result: 2.5V DC input produces 0V output. That makes sense. 2.5V DC corresponds to 0V RMS: 

Now, if I apply a 3.5V DC input, I would expect a 1V output, since 3.5V DC corresponds to 1V RMS. However, I do not get this, and I have a strange value on the IGND pin. I would expect the IGND pin to be midscale 2.5V, however it is sitting at 3.362V:

Now, if I tie the IGND pin directly to a midscale 2.5V supply, I do in fact get the expected 1V output. 

I have two questions:

1. Is this the expected result? Maybe it's just a problem with the SPICE model.

2. Is it ok to drive the IGND pin to half VCC (2.5V) in the application? 

Thanks,

Mark

We have an application using the AD9361 that is receive only.  We want to turn off the power to the transmitter(s) to save battery power.  We have gone through the ad9361 source code, but haven't found a way to turn off the transmitter(s) power.  Can someone explain which API (or code we need to write) that will turn off the transmitter(s) power on the AD9361?  Thank you.

Hi,

I just created a new project in CCES 2.5.1 for ADI-21573 platform. Then I wrote a sample application which reads the contents of a file and displays it. This was working fine. The LDF file was automatically generated for this application. Then I wrote another application which requires some amount of additional memory. So I was in need of modifying the LDF file. Previously the heap was mapped to L1 memory of the processor, now I modified the LDF file in such a way that, the heap is mapped to the SDRAM, since I need some extra memory for the application. For this application I'm not getting any 'printf' statements and the 'fscanf' function is not working properly. Is this the issue with SDRAM (L3 interface) of the processor ? Because previously 'printf' statements and the 'fscanf' function was working fine (when the heap was mapped to L1 cache). Can anyone please help me with this issue ?

The Linker Description File (LDF) which I'm using is attached herewith.

Hi all,

@ ADF4150HV, 

Customers are suffering from choice either a single ended configuration or a differential configuration for the RFIN connection circuit.

What is the point (superiority / inferiority) when choosing single ended input or differential input configuration with priority on PLL characteristic performance without considering physical condition (device)?
harmonics? noise? Output level? Other?

Can you give us a general comment on a simple comparison of both PLL configuration ?

Best regards,
sss

I have been using the ADE7858A chip for a particular monitoring application. Now when the configuration is used to monitor a 3 phase Delta system(Phase B is the reference) I understand that the Phase A & Phase C registers read out the Line to Line voltage, current, etc. However I am a bit puzzled about the values that I observe in the Phase B registers. If the value is meaningful, I would like to calibrate this and use it in my application.

Hello everyone

I am currently evaluating the AD9683 on a custom HW and have problems getting the data transmission going.

The FPGA seems to not properly receive the data from the ADC or at least I am not able to interpret the incoming data stream. I have used the SPI interface to debug the status flags of the AD9683 and have a question regarding a special bit.
When reading register 0x0A "PLL status" I get the value 0x81. A quick look in the datasheet tells that both "PLL locked status" and "JESD204B link is ready" bits are asserted. How is the later flag specified? What does "link is ready" mean? Does it mean that all the three SYNC phases have been completed (CGS, ILAS and Data transmission)?

I also tried to activate the "Test Mode Cycle" (register 0x0D) but I was not sure if I did it properly. I couldn't find the expected pattern in the RX stream of the FPGA transceiver. Could someone provide me with a quick explanation how the test mode is activated.

The AD9683 datasheet specifies a maximum lane rate of 5 Gbps (AD9683-250). I assume this is the total bandwidth together with the 8b/10b? The FPGA is also configured for 5Gbps. The ADC receives a reference clock of 250MHz (CLK+-) and the FPGA Transceiver receives a 125MHz reference. This should not be an issue I guess because both clocks are generated by a clock generator HW so they are related (common source)?

I was able to track the behavior of the transceiver and saw that a link is established for a short time (the FPGA claims that IDLE characters have been received) but at some later time the elastic buffer within the transceiver signals Overflow. The AD9683 datasheet chapter "JESD204B Synchronization Details" tells that the ADC transmits /K28.5/ during the CGS phase. Does this mean that every character sent has this value? The Xilinx IP Core has a 32-bit data interface so I would expect that the output of the IP Core should be 0xBCBCBCBC during this phase. Or am I totally wrong on that?

Any hints or tips would be much appreciated.

FPGA: a Kintex-7 implement the Xilinx JESD204B IP Core

SW: Vivado 2016.3

Regards,

Valko

Hi

I would like to ask if the AD2S1200 can support below resolver or which product can support it. Thanks for help~

above OFFSET Voltage ±200μV　means,

When I input -IN and +IN same Voltage,Output Voltage is ±200μV☓20(Gain) or　 ±200μV？

I have a question about AD5791.
We noticed that input to the control register was refused immediately after RESET was entered.
According to the measurements, this time is as short as 1 ms or less.
We focused on the parameter "RESET pulse activation time".
Will the input to the control register be rejected during this period?

Best regards

I downloaded the spice model from the AD website for ADG612. I need to run an ac sweep with the part as part of a larger simulation. I am starting with just a basic simulation of the part to show that it works. When I run the simulation in PSpice, I get the following error: "ERROR(ORPSIM-15159): RON or ROFF greater than 1/GMIN for VSWITCH model X_U1.X1.x1.SMOD2."

The same error comes up several times in a row in the simulation window with different SMODs, for example: "ERROR(ORPSIM-15159): RON or ROFF greater than 1/GMIN for VSWITCH model X_U1.X2.X2.SMOD4."

I am new to PSpice, so my apologies if I am missing something basic. 

Many thanks for any tips. 

-JR

I design the AD8232 circuits following the datasheet (measuring heart rate by two hands). The band pass filter is 7-25Hz. When I stands statically it's OK to get a clean waveform, but there is a lot of noise when I am running, looks like the noise is from friction of hands and stainless steel electrode. Attached are the schematics except changing one 1Mohms resistor to 200Kohms (I believe it's a typo of the schematic because it determines the frequency of low-pass filer).

How can I filter the noise? Its amplitude can cover the R wave.