Dear All,
I would like to generate a pulse from DAC with 10ns - 48ns pulsewidth and a very fast sampling rate 1GSPS and controllable voltage levels with a DC offset. I would like to know if any of ADC parts supports this.
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ADC part support this ? Any suggestions
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Industrial Vibration Monitoring for Bearing Defects
Hi , We want to do vibration monitoring on 6000 RPM speed motors for predictive maintenance. We are planning to use ADIS16228. Is this a suitable sensor for these kind of applications?
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Half Bridge CN0196 FH.
HI, two questions:
I have bought two boards EVAL-CN0196-EB1Z Half Bridge and AMuD7061-MKZ and I am for testing now according to the Operation Guide:
- On the side 6 Point 5 there are the Isolated PWM Pulse Check on PWM_Q4 and PWM_Q3 and I would like to know the Connection Pins with the nummers for the ground and on wich boards there are for connecting the oscilloscope.
- The inductor load is connecting on pin OUT1 and OUT2 and in which range in Henry (H) or MilliHenry (mH) is the best for the function for the CN0196.
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EVAL-8005 and 7842
I'm trying to explore the minimum necessary I2C commands needed to configure the 7842 on the EVAL-8005 board. As a baseline when using AVES Blue if I perform a capture all and then feed those settings back into the 7842 as a script, I don't get any output, even if the ADV8005 is reconfigured.
This procedure works with the ADV8005, why does it not seem to work with the 7842?
Thanks.
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ADRV9371 on mitx100
Hi,
I'm trying to get a Mykonos/ADRV9371 to work on a Mini-ITX Zynq Z-7100 board. I started with the hdl_2016_r2 branch, created a new mitx100 board based on the mitx045 and then tried to port everything AD9371 related over from the zc706 to the mitx100. Unfortunately transmitting data from a buffer doesn't work, and I can't figure out why.
Most things do work. The transmit path works using the DDS synthesizer code in the FPGA and the receive path works so the AD9371 related stuff and the JESD204 links seem to be up. But nothing happens if I try to play back a file using the GUI. The same image built for a ZC706 board does work and can play back data.
I'm a really a software guy, so the FPGA side is a bit confusing still. It's probably some silly thing that I have missed. Are there any debug hooks in the ADI HDL that I can get to from Linux to help. Or does someone have time to look at my HDL changes and see if you can spot something obvious?
I've uploaded my changes to github and they are quite small. First one change which creates a mitx100 project which is identical to the mitx045 project except for targeting the xc7z100-ffg900 instead of the xc7z045-ffg900. Next a change which imports the mitx100 MIG configuration downloaded from the zedboard site. Finally a change which tries to port the AD9371 support from the zc706 to the mitx100.
https://github.com/wingel/adi-hdl
Any help would be appreciated,
Christer
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Synchronous PPG and ECG measurement for time difference
Dear all,
My knowledge of electronics is rather theoretical and not very practical. I am faced with a project in which I want to read 2 types of biometrical data and record them synchonous.
I want to record PPG waveform synhronious with ECG. I want to measure the time between the ECG peak and the PPG peak. My first problem would be, how can i measure both data into my pc ( into LABVIEW ) synchronous. I can find different developement boards for ECG and PPG, can i start from these boards or is this not possible?
Thank you in advance.
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What OS should we use with the AD9371
I have a KC705 Kintex-7 Board. I'm going to put Microblaze on the FPGA but I'm wondering which Linux OS would be best to compile for it. The AD9371 is on it's way so I don't have the SD card. Is there a special ADI Linux OS flavor I should use?
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Request schematic check for the AD9665. Pulsing 30ns 800ma pulses that ride on a 50ma bias current.
Request schematic check for the AD9665. Pulsing 30ns 800ma pulses that ride on a 50ma constant current.
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AD737 example needed
We purchased couple AD737 in order to measure the RMS of a high frequency sine wave (e.g. 500 kHz), but could not make it work. So we would like to see an example of the chip connection measuring the RMS of a sine wave precisely.
Thanks.
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How do you reduce the effective sampling rate of the DAQ2 noOS project for the KCU105 with analog JESD204B?
Hello,
I am working on a project that utilizes the DAQ2 noOS ad_fmcdaq2_ebz project for the KCU105 with analog JESD204B. I have made several modifications to the base project to include PCIe and cannot update the project to the newly released version which claims to make changes to the sampling rate easier. I've gone through many of the forums for changing the sampling rate but none seem to post a full solution to the issue.
We would like to have an effective sampling rate with the DAC (AD9144) of 256Msps and a sampling rate with the ADC (AD9680) of 512Msps.
The clock generator (AD9523) uses a 125MHz oscillator to generate the clocks for the system. I need to replace this with a 128MHz oscillator to generate the 512MHz clocks.
Looking at page 23 of the AD9144 datasheet (http://www.analog.com/media/en/technical-documentation/data-sheets/AD9144.pdf ) shows that the minimum sampling rate is 420Msps. That being the case, I would like to reduce the tx line rate such that the DAC has an effective sampling rate of 256Msps due to the slow data transfer.
To break things up into smaller pieces, I started by keeping the 125MHz and the DAC sampling rate. I then attempted to reduce the lane rate by making modifications to the JESD204B_GT core and the ad_fmcdaq2_ebz.c file as shown below.
With these settings, I was not able to get anything out of the DAC. I would have expected that changing TX_Out_DIV to 2 from 1 would have reduced the lane rate in half to 500Msps on the FPGA side and that changing the channel 4 divider to 4 from 2 would reduce the lane rate in half to 500Msps on the other side. I will note that I am not clear on the functionality of the gt_link structures.
Any help or insight on this would be greatly appreciated.
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FMCDAQ2 PCB assembly
Hello all,
I am working on a project where I duplicate the FMCDAQ2 eval board but adding the filters and RF pathes (RX/TX) on the same PCB.
On the FMCDAQ2, I noticed that the DAC/ADC and Clock/FMC connector are not on the same layer.
- Did you do it to improve the isolation?
- Did you glue the large bottom components (ADC/DAC)?
- 2 reflows? Then do you know a simple way to estimate if the component can fall or not regarding the paste area?
Thank you very much for your help.
Best,
Chris
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ADIsimPE Transimpedance Amp
I have a photodiode model that I want to try out. I got this from the analog devices photodiode design tool:
I want to do the same simulation in ADIsimPE. Can this be done? I put this all together in ADIsimPE but I can not get the AC analysis to work. It gives me infinite bandwidth and do not see a real transient response. The simulation file is attached. I even have the opamp parasitic capacitance in there because I don't know if they are included in the sim model.
Thanks,
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ADF5355 Phase Resync
Dear support
I'm evaluating the ADF5355 for an application where it is used as fractional-N PLL. In this application, more than one chip is involved. All those chips have to produce the same output frequency with the same phase after the PLL locking. Therefore, the Phase Resync feature has to be ON on each ADF5355 chip.
My point is, how to determine the correct value for the Phase Resync Timer (Register 12) in order to apply the phase resinchronization process just after the locking? In particular, is there anyway to automatically determine the value for the Phase Resync Timer in order to minimize the time to get all the output frequencies in phase?
Moreover, activating the Phase Resync feature on each ADF5355, does it ensure that ALL the ADF5355 output frequencies have the same phase?
Thank you for your support.
Luca
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AD7949 CFG and Ref Out
Hello,
I need help about AD7949 adc. I send CFG register the value AdcCFG = 0x3FC4:
* Overwrite contents of register
* Unipolar, INx referenced to GND
* IN7, full BW
* Internal reference, REF = 2.5 V output, temperature enabled
* Scan IN0 to IN[7:0] (set in CFG[9:7]), then temperature
* Read back current configuration at end of data
Order of write/read as below (I use timing RAC. ):
Write CFG >> Read null >> Read Data 0 to7 >> Read CFG >> Finally Read Temp.
Question1: Is the data read/write order true. Should I read CFG before or after Temp read.(I read true CFG read back before temp. ReadCFG = 0x3FC4)
Question2: Thats all ok. But when I measure the voltage on ref or ref buffer pin (No: 2.5V or 4.096V)???
Question3: I read temperature hex value: 0x0363 at room temp(~24-25'C) what is the meaning or calculation for temp.
Thanks for all answers...
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AD9164 Description of Peak DAC Output Power Datasheet Rev A Pg. 68
Hi,
I am trying to understand the math in calculating the output power on Page 68 of the AD9164 Rev A datasheet. The datasheet says with a 100 Ohm differential source termination, the DAC ac current source sees 50 Ohms. It states that the ideal peak ac current is 20 mA when the AD9164 is programmed for an IOUTFS = 40 mA. So, then it gives that the maximum power delivered to the equivalent load is 10 x (RINT / (RINT + RLOAD)) = 8 mW. What is the "10" in this equation? And if i use 100 Ohms for RINT and 50 Ohms for RLOAD, i get 6.667 for the result. What am doing wrong? Now, i didn't take into consideration the BALUN equivalent impedance which is 50 ohms. With this, the equivalent load would be 25 Ohms. Then the equation above would make sense.
Appreciate any insight.
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Multiple projects / export files, one DSP
I'm working on a project with a single 1701 programmed by a microcontroller. I'd like to be able to switch between two projects dynamically, via the microcontroller.
Obviously I can export two sets of system files, but having both included in the same C project is troublesome, as things get doubly-defined. Are there any good tricks for doing this? (They use the same configuration, just different schematics.)
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AD9234 - PRBS Pattern Testing
Hello,
I'm able to receive JESD Test mode patterns in FPGA board successfully. Since we are able to receive data, we are working on traffic test.
When we configure PRBS 7 at both ADC board and Kintex 7 board, we observe no link and high BER. Even though link is not up, FPGA can detect the eye. Please let me know if there is any ADC configuration setting to get 0 BER and link up.
Configuration: 10Gbps, Reference clock = 250MHz
Thanks,
Rekha
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EEG Measurement
I want to design a EEG Acquisition SMD circuit board with 24 ADC and want to give it to DSP using USB (i.e., micro USB on 24 Bit ADC board and USB of DSP board) ? How should I achieve this with the ICs Mentioned in EEG Measurement section?
I want the Power circuit and every thing that is needed on a single board.
Also, I want to Design it for multi-channel EEG acquisition.
The reason I asked the question is to have a clear idea as of what is to be considered while designing.
So, it is my sincere request to you to help me achieve this. ( I have decided to Design this board within a board, This is my target as I want to work on the depths of DSP as soon as possible.).
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which led is mounted on adux1020 evaluation board?
I am wondering which LED is mounted on the evaluation board for the ADUX1020?
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How to handle static OSD on ADV7625?
Hello video support team,
I'm supporting a customer who is evaluating ADV7625 on our evaluation board.
They would like to show the current HDMI input channel like "HDMI 1" on the
screen using OSD. They think static OSD is suitable this purpose however it
is not clear how to use static OSD in the manuals including "ADV7625
Framework User Guide", HW manual, SW manual etc.
Question / Request 1
Could you provide a Blimp sample project file of static OSD on ADV7625 for reference?
Question / Request 2
How can I see the static OSD image on the screen? I think it need to readout the image form flash memory to store into the OSD RAM in the ADV7625, then to set some register to enable OSD. Sample script is better to understand how I should do.
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