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AD9361 Configuration (DATA_CLK)

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Hi,

 

I am currently starting to work with an AD9361 (on AD-FMCOMMS3-EBZ) on a FPGA development board, using the ADI driver which I customized lightly ( AD9361 Device Driver Customization [Analog Devices Wiki] )

 

I am confused with the clocks configurations and as I can not find the answer I am asking for help here.

 

My setup is composed of a sine generator on the FPGA, two RF boards an oscilloscope and a signal analyzer.

I need FB_CLK and DATA_CLK's frequencies to be 40 MHz but I measure the DATA_CLK at 20 MHz. Furthermore, the sine's frequency is twice as low as it should be (4,85 MHz instead of 9,9 MHz).

 

Here is the definition of the clock paths I entered in adi-fmcommms2.dti :

 

/* BBPLL     ADC        R2CLK     R1CLK    CLKRF    RSAMPL  */

  adi,rx-path-clock-frequencies = <1280000000 320000000 160000000 80000000 40000000 40000000>;

  /* BBPLL     DAC        T2CLK     T1CLK    CLKTF    TSAMPL  */

  adi,tx-path-clock-frequencies = <1280000000 320000000 160000000 80000000 40000000 40000000>;

 

I noticed that if I change the value of the register 0x00A (01 instead of 02) both my frequencies (sine on analyzer and DATA_CLK  on oscillo) become correct. The out_voltage_sampling_frequency is then equal to 80 MHz, which was an invalid argument when I entered it directly ( sudo cat out_voltage_sampling_frequency  echo 80000000 | sudo tee out_voltage_sampling_frequency)...

 

The reported path evolve as well:

(BBPLL : 1280, DAC : 640 ; T2:320 ; T1: 160 ; TF : 80 : TXSAMP : 80 (MHz))

 

This register (0x00A) doesn't seem to be modified when I load the driver.

 

Which configuration should I set, and do I miss some configuration options ?

 

Regards,

OlivierN


AD9361 maximum data rate

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Hello,

 

If i understood correctly, the maximum data rate at the output of a channel is 61.44MSPS.
If yes, which stage limit the data rate? Is it the FIR?
So i suppose the data rate per channel is the same in 1R1T and 2R2T configuration because in 1R1T, the output data rate on the LVDS link is 61.44MSPS and in 2R2T, the output data rate on the LVDS link is 122.88MSPS.
Is that correct?

 

On the Rev.A (table 50) the Maximum data rate in 1R1T change from 122.88MSPS to 61.44MSPS.
So the maximum RF bandwidth using 2x Oversampling should be 30.72MHz?

 

Is there the same error in table 48 which show a data rate of 122.88MSPS in 1R1T DDR Dual port half duplex?

 

Thank you for your help.

Gyroscopes data SCALE for ADIS16445

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Hello Guys,

 

I'm using ADIS16445 , gyroscopes in this IMU should sense and measure rotations up to ±250°/sec . this is my understanding of MEMS gyroscopes . ADIS16445 datasheet says : Triaxial digital gyroscope with digital range scaling
±62°/sec, ±125°/sec, ±250°/sec settings . if my understanding is wrong please explain it to me .

 

but , when I read XGYRO_OUT , YGYRO_OUT and ZGYRO_OUT data from this IMU and scale these to DPS format , I can see values more than ±250°/sec , for example ±300°/sec and ±330°/sec , but I expected to see values between -250 to +250 DPS .

 

this is my code to read and scale received 8bit values to 16bit and convert to DPS format :

 

        GPIO_ResetBits(GPIOA, GPIO_Pin_1); // CS low
        transfer(XGYRO_OUT);
        transfer(0x00);
        GPIO_SetBits(GPIOA, GPIO_Pin_1); // CS high
        Delay_us(_stall); // 9us Delay
        GPIO_ResetBits(GPIOA, GPIO_Pin_1); // CS low
        uint8_t _msbData = transfer(0x00);
        uint8_t _lsbData = transfer(0x00);
        GPIO_SetBits(GPIOA, GPIO_Pin_1); // CS high
        Delay_us(_stall);
        int16_t _dataOut = (_msbData << 8) | (_lsbData & 0xFF);
        float gx = _dataOut * 0.01; // 100 LSB/°/sec

 

Best Regards,

Edward .

What does the Led CR2 could indicate in my AD9959 eval board?

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I want to know what is the function of the led CR2 besides of indicates when the DUT is ready, because, when I controll the AD9959 eval manually, I disconnect the USB comunication (after that I change the jumper W7 to manual), and sometimes the LED CR2 stays On, sometimes it gets off, and sometimes it blinks.

 

I want to know if the LED its indicating me something about the AD9959, for example, to much voltage, to much current, bad function or something like that.

 

Every answer would be aprecciated.

 

Best Regards,

Javier Glz.

Programming the Cypress chip on the HSC-ADC-EVALCZ to control the AD9269 with custom PC software.

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I've used visual analog for analysis of signals. My project requires me to write a custom program on visual studio to display the input signal in the time domain. I'm trying to figure out the best way to program the cypress chip for this application.Any help would be greatly appreciated.

About AD9628 Input

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Hi,

I would like to apply 0-2V input to AIN+ and AIN- in AD9628.

 

Absolute maximum rating of AIN is 2 V when AVDD is 1.8 V.

Is it possible to apply 2V to AIN+ and to apply 0V to AIN-?

 

 

Best Regard,

Yuya

12-20 GHz PLL Design - "Noise-like spurs"

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Hi All,

 

I'm currently working on a PLL design that's to generate frequencies from 12 GHz to 20 GHz.To do so, I'm using a HMC733 VCO with a HMC704 PLL (with a HMC447 div-by-4 to feed the VCO reference back to the PLL). After tweaking the loop filter, I finally got the PLL to lock throughout the frequency range I wanted, with one drawback: I'm noticing that the noise floor rises on both sides of my carrier signal as shown below:

 

HMC733 16 GHz Locked Output

 

 

The SpecAn capture I show is for a 16 GHz VCO output. This behavior is present throughout most of the frequency range of operation of my design (12 GHz up to ~18 GHz). Any thoughts on what might be causing this? I've tried increasing/decreasing the loop filter BW but this behavior persists. I'm currently using an 3rd order active C loop filter, with a 500 KHz loop filter bandwidth and a 80 degree phase margin. Also, both the VCO and the div-by-4 are being powered by a HMC976 (low noise linear voltage regulator).

 

Thank you!

Dynamic loudness in 1701

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Hi,

 

I am looking for a way to apply dynamic loudness to my signal in ADAU1701. I have found the dynamic bass boost block but that only adds gain to the lower frequencies. I want to add a dynamic "Fletcher Munson" type loudness curve which includes both low and high frequencies.

I have found the loudness block which adds gain to both low frequencies and high frequencies but this is not dynamically controlled.

 

Please let me know if there is a good solution to this available!

 

Best regards

Markus


IIO 9371 TX Attenuation

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Hi,

 

We've been trying to use the IIO Oscilloscope tool with our AD9371 evaluation board to perform some basic analysis of the TX attenuation settings and are having difficulty.  With the oscilloscope tool, under "AD9371->BIST", we can enable the TX NCO test tone and are able to view the test tone on the spectrum analyzer.  However, when we then navigate to the "AD9371->AD9371 Transmit Chain" settings and attempt to modify the TX1 attenuation setting, it appears as though the setting is accepted, however, the tone's level does not change on the spectrum analyzer.  Additionally, if we observe the value "out_voltage0_hardwaregain" of the ad9371-phy IIO device, we do not see that value change when modifying the setting in oscilloscope.  Also, if we try to change it by directly writing a value to that attribute on the command line, we are unable to make it change.  We've also attempted to modify the attenuation setting while having the FPGA generating the tone instead of using the BIST (via the Transmit / DDS test configuration) and are unable to have the attenuation setting impact the tone transmitted.

 

Is there a specific way that the attenuation setting needs to be configured in order to take affect?  Is modifying the attenuation setting while running in the BIST tone mode supported?  Are there any known issues with the TX attenuation settings being modified when using the IIO oscilloscope tool?

 

Any suggestions on this are appreciated.

 

Thanks,

Meaghan

Photodiode Wizard : Rshunt

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Whould it be feasible to extend the photodiode wizard for a Shunt-Resistance < 100kohm ?

Many (M)IR-PD have shunt resistance of about just 1-10kohm.

ADE7858A Checksum calculation

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Hello,

 

I'm trying to calculate checksum in software to verify it against the one calculated by the metering IC.

 

I have received a spreadsheet of registers used for calculating checksum for ADE7858A and have a couple of questions about it.

 

I’ll try to cover everything thoroughly since I’m trying to understand it myself, and don’t want to make any erroneous assumptions.

 

There are 2344 bits total that are fed into LFSR that generates a CRC-32 checksum for ADE7858A.

The default checksum should be 0xE908F4D0

 

Internal registers (refer to spreadsheet) make a total of 48 bits long,  and in hex the default array of bits looks like this: 000020000400
Those are fed into LFSR first, starting with 0 then 0, 4, 0, etc

 

There are 48 bits above, so that works out.

 

Next we have configuration registers. In hex the array is 000000000000000001ff00000e88000000000000000000000000000003bd1c00780000
There are 280 bits in here so documentation on page 66 showing configuration registers are a total of 280 bits works out.
Those are fed into LFSR starting from register CFG_REVA as least significant

 

Then we get to DSP data memory ram registers.
There are a total of 63 registers between address 0x4380 and 0x43BE. All initial values are 0 so I won’t bother pasting that array in here.
They are mainly 24 bit registers with exception of Reserved-32 registers in that excel sheet you’ve provided.

 

However the total number of bits here is 1568
56 24 bit registers and 7 32 bit registers

 

The number of bits I expect based on datasheet is 2064 for that section.
Even if I assume all registers are 32 bits long, that still lands 2016, a bit short of expected.

 

What am I missing? Is the way I count them wrong? Is the way I assume they are fed into lfsr okay?
Do you have any sample code that performs this crc calculation I can take a look at?

 

I’ve attached a spreadsheet I am using as reference, plus some modifications I made

 

Thank you for your patience,
Denis Sazhaev

ADF5355

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Dear Sir/Madam

 

When the ADF5355CE islow,whether or not the ADF5355 could power up through software configuration.
Thanks.

Register configuration issues on the HMC764

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Find a typical register configuration for integer division.
Now no matter how many of the registers of the N divider ,the vco are oscillating at around 7.5GHz.

Phase frequency is 10MHz and  reference input is 50MHz.

The following is my register configuration:

02h <= 5d(R divider is 5)

03h <=  770d(N divider is 770,expected RF out is 7.7GHz)

04h <= 0

05h <= 50894C

06h <= 703387

07h <= 4FA

08h <= 31DF

09h <= 900000

0Ah <= 0

0Bh <= 72

0Ch <= 0

0Dh <= A

 

ADE7953 Active Energy and Phase Calibration

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I need to calibrate phase for the ADE7953, as I am using a current transformer and want to collect power data. The current transformer is connected to channel A of the ADE7953. For phase calibration, according to page 12 of the AN-1118 document, I need to measure active energy. And to measure active energy, I need to set the accumulation time to 1 sec. To do that, I enabled the line cycle accumulation mode, and set the line cycles (register 0x101) to 120 (since the frequency of my voltage waveform is 60 Hz). Then I try to read the Active Energy A (register 0x31E), and I get a 0, regardless of what I set the voltage supply to. I am not sure what I am doing wrong. I am able to read the Vrms and IrmsA just fine.

 

Thank you in advance for any help.

ADE7953: Active energy register not working

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I have designed a metering device using an ADE7953 with a rogowski coil. My main Microcontroller (ARM M0+) can succesfully communicate and read electrical information from the ADE IC. 

 

I have had no big issues, and I have found that the  ADE7953 IC is really robust and very easy to get started with.

 

I can succesfully read Voltage, Ampere, reactive/Apparent power, but there is something wrong with the Active power and the power factor. These are some measurements/registers I can read: 

 

VRMS (0x31C) - IRMSA (0x31A) - PFA(0x10A) - AWATT(0x312) - AVAR(0x314) - AVA (0x310)

5696512    186153    0         168         61989              63209   
223.13V     1.82A      0.00    4.02W     1466.26Var     1494.73VA

5697412    185602    0         183         61868              63017
222.89V     1.82A      0.00    4.19W     1463.14Var     1491.47VA

5682620    185196    0         159         61597              62762
222.57V     1.81A      0.00    3.86W     1456.87Var     1484.85VA

5680437    185192    0         208         61530              62691
222.25V     1.81A      0.00    4.78W     1455.26Var     1482.55VA

 

First line is the register measurement, and second line is the real value after calibration. I am measuring from an electrical heater, therefore the reactive power should be small. 

 

I can see the following:

  • Mesurement are stable, except the Active power (AWATT)
  • Power factor is always cero. PFA register is a signed 16 bits, maybe the No-Load detection is activated?
  • There seems to be something wrong with the active power, there is not a stable reading, and it decreases when I consumes more power.
  • Reactive and apparent are stable and high enough

 

I have doublechecked that the registers are correct, but I am now stuck. Can you help me?


What accumulation mode is used for apparent energy accumulation in ADE7880,is it signed accumulation or absolute only accumulation?Not mentioned in datasheet It is observed apparent energy is accumulating in absolute mode only,can it be changed

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Hello Sir,

Can you help for the below queries 

i) What accumulation mode is used for apparent energy accumulation in ADE7880,is it signed accumulation or absolute only accumulation?Not mentioned in datasheet

 It is observed apparent energy is accumulating in absolute mode only,can it be changed

ii)  compute apparent energy import & apparent energy export form ADE7880

 

Thanks 

AD777x ADC family

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Hello,

recently the AD777x ADC family (AD7770, AD7771, AD7779) was announced at an exhibition which was related to energy and power distribution topics.

Unfortunately the ADCs listed above are not covered by a comparison table at your website.

Could you please tell me the differences in features and applications / use cases?

In the press I read that the AD7779 ensures fast power-up in circuit breaker equipment. What does that mean?

Thank you.

Does ADE7880 supports lag only metering, wherein for power factor in lead condition, power factor should be assumed at a fixed value? Can it be implemented in our controller using some inputs from ADE7880?

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Hello Sir,

Can you help for the below query 

Does ADE7880 supports lag only metering, wherein for power factor in lead condition, power factor should be assumed at a fixed value? Can it be implemented in our controller using some inputs from ADE7880?

 

We will be very much thankful to you for this 

AD7770

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Hello!

     I have question regarding the analog channels of the AD7770: are the analog channels isolated in AD7770? Can they be coupled directly with signals coming from plcs? Isolation amplifiers required for AD7770 if necessary?

 

Thank you!

ADV7611_Evaluation_Board_Software Documentation

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I was wondering where I could find more information on the ADV7611_Evaluation_Board_Software? I have Rel 1.56.0 of the software that I was able to download, but the documentation directory is empty, and the code has very little comments in it. I am trying to understand the flow in this software. I am trying to determine which sections of this I will need to replicate in my new design with the ADV7611. I have reached out to our local AVNET rep but they do not have anyone that I can contact regarding this product.

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