Hello,
Could you please also provide an approximation of the ADXRS290 Bias Repeatability ?
Many Thanks.
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ADXRS290 Bias Repeatability
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DAQ2 unexpected result in receive path
Hi Istvan,
I recuperate data: adc_data_0 (64bits) and add_data_1(64 bits) from a signal injected in Input of the ADC(DAQ2).
I try to plot it and observe it but i see difference between the oscilloscope and the signal
with the adc_data_0 and add_data_1.(saturation)
I consider data like your answer :
o in case of DAQ2, using the default ADC and JESD204B configuration, on the core's output you should see:
- adc_data_0 = {I3, I2, I1, I0} (converter 0)
- adc_data_1 = {Q3, Q2, Q1, Q0} (converter 1)
I plotted the samples I0,I1,I2,I3 and Q0,Q1,Q2,Q3 (saturation) separately.
thanks,
Bouchaib
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AD9117 register 0x02 setting
Hi,
We have use AD9117 in our design.
For 0x02 register, value is 0x96, you can see attached file, function is work,
But datasheet is strongly recommended that DCI_EN = DCOSGL = high,
or DCI_EN = DCODBL = high not be used, even though the device may appear to function correctly.
Would you please kindly provide some suggest for this setting?
Thanks.
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Problems in accessing SC589 ez-kit DDR3 SDRAM
I use sc589 ez-kit with ICE-1000 emulator. The initalization code is EE387. I use the preload project to replace CCES defualt preload code. In the memory accessing test, sharc core can access DDR3 successfully but the ARM core failed in such accessing test. CCES console show such a message:
A non-recoverable error or exception has occurred.
Description: No dispathed handler available for the specified interrupt code.
General Type: RunTimeError
Specific Type: NoDispathedHandler
Error PC: 0xc100447c
The version of CCES I used is 2.3.0.
I wanna know what's the problem.
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how DVI-D interface monitor receives the 576i resolution
can you explain the DVI TMDS of 576i data processed by DVI monitor with
timing diagram
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SC589 PCIe question
I have a ADSP SC589 EZ-kit board and I want to use it's PCIe interface to connect a custom PCIe card. I configured the kernerl as followings:
Then I re-build the kernel. The output message display the sc58x-pcie 310b8000.pcie: link training failed.
The info is following:
sc58x-pcie 310b8000.pcie: Link training failed
sc58x-pcie 310b8000.pcie: PORT_LINK_DEBUG0 = 4a4a02, PORT_LINK_DEBUG1 = 8000000
sc58x-pcie: probe of 310b8000.pcie failed with error -110
By the way, I have populated the R417 and R418 by 0 OHM resistor to provide the reference clock to card and the card is work normal.
I want to know why the EZ-kit did not detect the card. What more settings are needed?
Thanks a lot.
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AD9578 problem
At last I have finished my own development PCB and software to program the AD9578 in rational mode. I can enter the frequency , and the software finds the minimum fractional divider, minimum modulus, and output divider to generate the desired frequency. I can also read back the registers. I am currently using output1 and output2, both driven from PLL1. The outputs are set to LVPECL mode.
Everything works, except that occasionally the output disappears from both outputs, and a power on reset is needed to restore normal function. Reading back the registers after this strange failure shows all the registers unchanged, with PLL1 still showing locked. The outputs are still LVPECL, with correct DC levels, however there is no AC output.
The fault occurs from a few seconds to many minutes after power on reset and programming. After the failure, re-programming the registers has no effect.
I am fairly sure that the power supplies are OK, with no glitches. If the chip was resetting, I would expect the registers to go back to the default, which they do not. When I program the chip, I first write to register2 with the MR bit set. I then write the correct data to register2 with the MR bit cleared. I then program all the other registers in order except registers 10,11,and 13. The following is the register data, starting with register1. note 32 bit registers have 2 trailing zeros, and 24bit registers 4 trailing zeros, etc.
PR
0000007A08000000
000000055F570000
0000001003000000
00000000AA000000
0000000000505000
0000003F000EA3DE
0000006474700401
000000000000000E
0000006460700400
0000000000000000
00000019DAAAA300
00000082AAAAAB00
00000026AA6AE200
00000003AAAAAA00
0000002600000000
The frequency is 39.96MHz, the fractional divider is 117, the modulus 125, the integer divider 63, and the output dividers 80.
S is 3.
I hope you can advise on this problem
best regards
Cosmo Little
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AD9578 attachments
Attachment relating to previous post
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(CN0067)Do you have the PCB data?
Hi
We were reading CN0067.
CN0067 Circuit Note | Analog Devices
We thought that this will be very good reference four our customer to make isolated ADC.
If our customer think that they want to use this as the reference when they want to design the PCB.
Can you give us the PCB layout image?
".pcb" file will be perfect but if it is difficult , image file is OK.
Best regards.
Kawa
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ADXL362 : FIFO_OVERRUN
Hello,
I have a question about the ADXL362.
I use the ADXL362 in the stream mode.
Does this mode support the FIFO_OVERRUN bit?
Or, in this mode, is only the FIFO_WATERMARK bit supported?
Best Regards,
Mr.K
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Leakage current of /SDN ADA4851-1
Dear Sir/Madam,
Our customer asked as folowing question.
As for your ADA4851-1,
What is your output leakage current when /PDN is enabled?
In fact, he has put the transistor 2SC6075 at ADA4851-1 output, and has driven the laser diode.
But when he change /PDN=enable, then 2SD6075 worked and the laser diode came on.
He think the reason why is leakage current.
So I need your comment soon.
Thanks Kaos
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ADF7023 firmware update
Hi Sir ,
How to update the firmware of ADF7023?
Could you provide the file and tell me how to do ,tks!
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Energy Monitoring
Hai, I want to mesure the energy of a 3 Phase supply of 440V,5A using ADE7880 energy meter.What design changes is needed for the circuit.
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ADE7878 i2c interface not working
Dear all, I have use ADE7878 poly phase ic in stm32f4xx controller. I choose i2c interface with STM32F4XX. Initally, Reset pin set low to high 40 ms. Then set value in CONFIG register I2C lock register set bit 1. But I read CONFIG register in same bit, not came in same value. How to Inital that IC
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AD7641 EVAL Board noise floor issues
Dear all,
I have set up the EVAL-AD76XXEDZ with the AD7641 and the EVAL-CED1Z. When I am trying to measure the noise floor with the EVAL-PulSAR-CED software, I am getting this (see attachments for zoom) spectrum:
The analog input is not connected to a source. The EVAL-CED1Z is just connected to the supplied power supply and USB.
What could cause those spectral lines and how to approach that problem?
Thanks a lot in advance
Best regards
Matthias
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2147x FFTA
I debug the 2147x FFTA and have a problem. When I set a breakpoint at FFTA ISR (FFTIsr), the dsp work correctly and everytime the pc can stop at breakpoint. But the dsp runs at full speed, then cces report a error:
Core access to a SPORT/LINK Port is hung at PC:0x1244c2
I don't know what happen, and who can tell me what to do . Thanks!
/*****************************************************************************
* 21479flashtest.c
*****************************************************************************/
#include <sys/platform.h>
#include "21479flashtest.h"
#include <stdio.h> /* Get declaration of puts and definition of NULL. */
#include <builtins.h> /* Get definitions of compiler builtin functions */
#include <platform_include.h> /* System and IOP register bit and address definitions. */
#include <processor_include.h>
#include <services/int/adi_int.h> /* Interrupt Handler API header. */
#include "adi_initialize.h"
#include <sru.h>
/**
* If you want to use command program arguments, then place them in the following string.
*/
extern void initPLL(void);
extern void initExternalMemory(void);
int FFTtest(void);
void FFTIsr(void);
#define PCI 0x80000
#define COEFFSEL 0x100000
#define OFFSET_MASK 0x7FFFF
volatile int fft_done=0;
volatile float inputdata[512] = {
#include "input512.dat"
}; /*input data is in the form of real followed by imag.*/
static float coeffdata[512] = {
#include "twiddle256complx.dat"
}; /*512 twiddle data in the form of real and imag. coeff are in terms of cos, -sin, sin, cos.*/
volatile float outputdata[512];
int dataTxTCB[6] = {0,0,0,512,1,(int)inputdata};
int coeffTCB[6] = {0,0,0,512,1,(int)coeffdata};
int dataRxTCB[6] = {0,0,0,512,1,(int)outputdata};
int I1[256] ={};
int Q1[256] ={};
int I2[256] ={};
int Q2[256] ={};
float SUMI[256] ={};
float SUMQ[256] ={};
float DIFFI[256] ={};
float DIFFQ[256] ={};
int main(void)
{
// asm("JUMP 0;");
int temp;
int i,a;
/* Initialize managed drivers and/or services at the start of main(). */
adi_initComponents();
/* Initialize SHARC PLL*/
initPLL();
/* Initialize DDR2 SDRAM controller to access memory */
// initExternalMemory();
a= 0;
*pPICR0 =P3I4|P3I3|P3I1|P3I0;
adi_int_InstallHandler(ADI_CID_P3I, FFTIsr, NULL, true);
SRU(HIGH, PBEN09_I);
SRU(HIGH,DAI_PB09_I);
for(i=0;i<256;i++)
{
I1[i] = i;
I2[i] = i+1;
Q1[i] = i;
Q2[i] = i+2;
}
FFTtest();
while(1)
{
}
/* Begin adding your custom code here */
return 0;
}
int FFTtest(void)
{
unsigned int temp;
/* Selecting FFT accelerator */
*pPMCTL1&=~(BIT_17|BIT_18);
*pPMCTL1|=FFTACCSEL;
/*PMCTL1 effect latency*/
//asm("nop;nop;nop;nop;");
NOP();NOP();NOP();NOP();NOP();
/*Clearing the FFTCTL registers*/
*pFFTCTL2=0;
*pFFTCTL1=FFT_RST;
//asm("nop;nop;nop;nop;");
NOP();NOP();NOP();NOP();NOP();
temp= ((int)(dataTxTCB) + 5) & OFFSET_MASK; /*Set up coeff TCB*/
coeffTCB[0]= temp;
*pCPIFFT= (((int)coeffTCB+5) & OFFSET_MASK)|COEFFSEL; /* Start transmit TCB.*/
/* Enable receiveTCB need not wait for the transmit TCB to complete. */
temp = PCI; /* Enables interrupt after DMA for receive*/
dataRxTCB[0] = temp;
temp= (int)dataRxTCB + 5;
*pCPOFFT = temp; /* Starts DMA.*/
*pFFTCTL2=VDIMDIV16_16|FFT_LOG2VDIM_8; /* Set up VDIM values*/
*pFFTCTL1=FFT_EN|FFT_START|FFT_DMAEN;
//asm("nop;nop;nop;nop;");
NOP();NOP();NOP();NOP();NOP();
// while((*pFFTDMASTAT & ODMACHIRPT)==0);
// puts("256_Point_FFT_completed");
return 0;
}
void FFTIsr(void)
{SRU(HIGH,DAI_PB09_I);
unsigned int state=0;
// state= *pFFTDMASTAT;
FFTtest();
SRU(LOW,DAI_PB09_I);
}
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Good day! please tell me what are the differences between circuits adv7403cstz-110 and adv7403bstz-110 ?
Good day! please tell me what are the differences between circuits adv7403cstz-110 and adv7403bstz-110 ?
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digital RGB to HDMI converter
Looking for HDMI transmitter chip with support to 18 bpp Digital RGB ie. RGB666 ;RGBx6 bity each INPUT format .Want to use it for video application for the hdmi TMDS output.
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Init code
Hi,
I'm trying to init code the blackfin 533, but the software does not boot up
here is the code
#include <sys/platform.h>
#include <sys/anomaly_macros_rtl.h>
#define PLL_msel 24
#define PLL_d 0x0
#define PLL_count 0x200
#define PLL_bypass 0x0
#define PLL_csel 0
#define PLL_ssel 6
#define ASYNC_SETUP 2
#define ASYNC_ACCESS 3
#define ASYNC_HOLD 1
#define SPI_setting 8
//define spi_output
.section program;
.global _main;
_main:
//*******Pre-Init Section******************************************
[--SP] = ASTAT; // The Stack Pointer, SP, is set to the end of
[--SP] = RETS; // scratchpad memory (0xFFB00FFC)
[--SP] = (r7:1); // by the On-Chip Boot Rom
[--SP] = (p5:0);
[--SP] = I0; [--SP] = I1; [--SP] = I2; [--SP] = I3;
[--SP] = B0; [--SP] = B1; [--SP] = B2; [--SP] = B3;
[--SP] = M0;[--SP] = M1;[--SP] = M2;[--SP] = M3;
[--SP] = L0; [--SP] = L1; [--SP] = L2; [--SP] = L3;
//*****************************************************************
//*******Initialize Flags************
//Set PF as input
P2.L = FIO_DIR & 0xffff;
P2.H = FIO_DIR >> 16;
R0 = W[P2](Z);
BITSET(R0,14); //Set PF14 as output: LED (BUZZER_ON)
BITSET(R0,2); //Set PF2 as output: EEPROM CS
BITCLR(R0,1); //Set PF1 as input (SPI_MAGN_A_CS)
BITCLR(R0,7); //Set PF7 as input (SPI_MAGN_B_CS)
W[P2] = R0;
//Set Active High Polarity
P2.H = FIO_POLAR >> 16;
P2.L = FIO_POLAR & 0xFFFF;
R0 = W[P2](Z);
BITCLR(R0,1); //Set active high polarity for PF1
BITCLR(R0,7); //Set active high polarity for PF7
W[P2] = R0;
//Enable PF
P2.H = FIO_INEN >> 16;
P2.L = FIO_INEN & 0xFFFF;
R0 = W[P2](Z);
BITSET(R0,1); //Enable PF1
BITSET(R0,7); //Enable PF7
W[P2] = R0;
// Set PF14 pin high
P2.L = FIO_FLAG_D & 0xFFFF;
P2.H = FIO_FLAG_D >> 16;
R0 = W[P2](Z);
BITSET(R0,14);
W[P2] = R0;
// enable watchdog
P0.H = WDOG_CNT >> 16;
P0.L = WDOG_CNT & 0xFFFF;
R1.H = 0x000F;
R1.L = 0x0000;
[P0] = R1;
P1.H = WDOG_CTL >> 16;
P1.L = WDOG_CTL & 0xFFFF;
R1 = 0;
[P1] = R1;
// load signature
P2.L = 0xFF901D80 & 0xFFFF;
P2.H = 0xFF901D80 >> 16;
R2 = [P2];
R3.H = 0x6789;
R3.L = 0xABCD;
// check signature
cc = R3 == R2;
if cc jump check_true;
// check false -> jump to BOOTLOADER
R0.H = 0x2000; // set start address
R0.L = 0x1000;
jump post_init;
// check true -> jump to API
check_true:
// Set PF14 pin low
P1.L = FIO_FLAG_D & 0xFFFF;
P1.H = FIO_FLAG_D >> 16;
R0 = W[P1](Z);
BITCLR(R0,14);
W[P1] = R0;
R1 = 0;
[P2] = R1; // clear signature !!
R0.H = 0x2001; // set start address
R0.L = 0x0038;
post_init:
//*******Post-Init Section********************************************
L3 = [SP++]; L2 = [SP++]; L1 = [SP++]; L0 = [SP++];
M3 = [SP++]; M2 = [SP++]; M1 = [SP++]; M0 = [SP++];
B3 = [SP++]; B2 = [SP++]; B1 = [SP++]; B0 = [SP++];
I3 = [SP++]; I2 = [SP++]; I1 = [SP++]; I0 = [SP++];
(p5:0) = [SP++];
(r7:1) = [SP++];
RETS = [SP++];
ASTAT = [SP++];
//********************************************************************
RTS;
_main.END:
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Heat Slug Connection in ADSP-21060LCW
Dear,
I have questionw on Heat Slug of ADSP-21060LCW.
There is a heat slug at bottom side of IC and it's purpose is for cooling.
Q1) Is heat slug connected to internally ?
Q2) Can I connect this heat slug to Ground ? If not, where should I connect ?
Thanks a lot.
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