The input for the AD7609 is coming from an inductor (secondary coil of a transformer). So without any additional circuitry, the signal would just "float".

Currently we "bias" the signal by adding a resistors to ground on each input, which also adds a (desired) load to the system.

I'm wondering if this was the right thing to do. My gut says yes, because of the high input impedance (1M) of the ADC inputs. Would it be better to have the ADC input "float" and let the ADC provide whatever bias it wants? It looks as if the clamping circuit could cause problems in such a setup. The evaluation board schematic doesn't do this though.

Hi all,

when i run the Matlab Simulink example "ad9361_LTE.slx" form LTE Transmitter and Receiver Example [Analog Devices Wiki]  with loopback cable between Tx1 and Rx1, i get the result shown in the appendix. The phase of the constellation-points is ok but the amplitudes are very bad what gives an EVM around 8%.

The text in  LTE Transmitter and Receiver Example [Analog Devices Wiki]  says:

"According to the experiment, when the digital Tx - digital Rx loopback is used (RF bypassed), the overall EVM is around 0.077%. When a loopback cable is used between Tx and Rx (RF included), the overall EVM is below 2%."

I can confirm the 0.077% in RF-bypassed-mode but not the 2% when RF is included. I use ZedBoard with AD_FMCOMMS3-EBZ and another SDR-Board with Xilinx Zynq and AD9361 NAMC-SDR RF interface for Software Defined Radio  and get exactly the same results.

I tried slow_attack, fast_attack, manual with various gains and tracking modes enabled and disabled but still bad amplitudes. The used filter is LTE1p4_MHz.ftr from analogdevicesinc github. All DDS-tones are disabled.

Does someone have an idea how to improve the amplitudes of the symbols for a better EVM?

Thanks,

Will

     I have a adsp-sc584-ezboard,after download uImage and sc58x-ezkit-lpc.dtb file from tftp,Sometimes the board can not detect USB mass storage device,then the voltage of USB0_VBUS is only 0.9V.

     I also used the original uImage and sc58x-ezkit-lpc.dtb in this path (/opt/analog/cces-linux-add-in/1.1.0/buildroot-sc58x-1.1.0/images ),it also can't detect usb.

     My configuration of USB follow the user's guide (Linux Add-in User's Guide-->User Manual for USB in Linux Kernel):

Device Drivers  --->

  [*] USB support  --->

  <*>   Support for Host-side USB

             USB Physical Layer drivers  --->

        <*> NOP USB Transceiver Driver

Device Drivers  --->

  [*] USB support  --->

  <*>     Inventra Highspeed Dual Role Controller (TI, ADI, ...)

  MUSB Mode Selection (Host only mode)  --->

1.Sometimes the board can detect usb device

2.Sometimes the board can not detect usb device,when detect usb NG,the log print this message:

musb-hdrc musb-hdrc.1.auto: VBUS_ERROR in a_idle (90, <VBusValid), retry #0, port1 00000100

and why usb detector have this problem?thanks~

it's my whole log:

Starting kernel ...

Booting Linux on physical CPU 0x0

Linux version 4.0.0-ADI-1.1.0 (root@giant-virtual-machine) (gcc version 4.8.3 (Analog Devices Inc. ARM Tools (de6372ac6a9979273b92892f826b11ea3363115b). Distributed as part of CrossCore Embedded Studio an6

CPU: ARMv7 Processor [410fc051] revision 1 (ARMv7), cr=10c53c7d

CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache

Machine model: ADI sc58x-ezkit LPC

Memory policy: Data cache writeback

dump init clock rate

CGU0_PLL 450 MHz

CGU0_SYSCLK 225 MHz

CGU0_CCLK 450 MHz

CGU0_SYS0 112 MHz

CGU0_DCLK 225 MHz

CGU0_OCLK 150 MHz

CGU0_SYS0 112 MHz

Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 28448

Kernel command line: root=/dev/mtdblock2 rw rootfstype=jffs2 clkin_hz=(25000000) console=ttySC0,57600 mem=112M ip=192.168.1.3:192.168.1.5:192.168.1.1:255.255.255.0:sc58x:eth0:off

PID hash table entries: 512 (order: -1, 2048 bytes)

Dentry cache hash table entries: 16384 (order: 4, 65536 bytes)

Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)

Memory: 91464K/114688K available (3659K kernel code, 120K rwdata, 1352K rodata, 16860K init, 87K bss, 23224K reserved, 0K cma-reserved)

Virtual kernel memory layout:

    vector  : 0xffff0000 - 0xffff1000   (   4 kB)

    fixmap  : 0xffc00000 - 0xfff00000   (3072 kB)

    vmalloc : 0xc7800000 - 0xff000000   ( 888 MB)

    lowmem  : 0xc0000000 - 0xc7000000   ( 112 MB)

    modules : 0xbf000000 - 0xc0000000   (  16 MB)

      .text : 0xc0008000 - 0xc04ecf78   (5012 kB)

      .init : 0xc04ed000 - 0xc1564000   (16860 kB)

      .data : 0xc1564000 - 0xc15821e0   ( 121 kB)

       .bss : 0xc15821e0 - 0xc15980ec   (  88 kB)

NR_IRQS:16 nr_irqs:16 16

GIC CPU mask not found - kernel will fail to boot.

GIC CPU mask not found - kernel will fail to boot.

sched_clock: 32 bits at 112MHz, resolution 8ns, wraps every 38177486839ns

Console: colour dummy device 80x30

Calibrating delay loop... 297.98 BogoMIPS (lpj=595968)

pid_max: default: 32768 minimum: 301

Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)

Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)

CPU: Testing write buffer coherency: ok

Setting up static identity map for 0x8937c2f8 - 0x8937c32c

devtmpfs: initialized

do_initcall_level level 0

do_initcall_level level 1

VFP support v0.3: implementor 41 architecture 2 part 30 variant 5 rev 1

pinctrl core: initialized pinctrl subsystem

NET: Registered protocol family 16

do_initcall_level level 2

DMA: preallocated 256 KiB pool for atomic coherent allocations

do_initcall_level level 3

L2C: device tree omits to specify unified cache

L2C-310 dynamic clock gating enabled, standby mode enabled

L2C-310 cache controller enabled, 8 ways, 256 kB

L2C-310: CACHE_ID 0x410000c9, AUX_CTRL 0x06040000

sc58x_init: registering device resources

sec init...

enabled

hw-breakpoint: Failed to enable monitor mode on CPU 0.

ADI DMA2 Controller

do_initcall_level level 4

SCSI subsystem initialized

usbcore: registered new interface driver usbfs

usbcore: registered new interface driver hub

usbcore: registered new device driver usb

i2c-bfin-twi 31001400.twi: Blackfin on-chip I2C TWI Contoller, regs_base@f4001400

i2c-bfin-twi 31001500.twi: Blackfin on-chip I2C TWI Contoller, regs_base@f4001500

i2c-bfin-twi 31001600.twi: Blackfin on-chip I2C TWI Contoller, regs_base@f4001600

pps_core: LinuxPPS API ver. 1 registered

pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>

PTP clock support registered

Advanced Linux Sound Architecture Driver Initialized.

do_initcall_level level 5

Switched to clocksource cs_gptimer

NET: Registered protocol family 2

TCP established hash table entries: 1024 (order: 0, 4096 bytes)

TCP bind hash table entries: 1024 (order: 0, 4096 bytes)

TCP: Hash tables configured (established 1024 bind 1024)

TCP: reno registered

UDP hash table entries: 256 (order: 0, 4096 bytes)

UDP-Lite hash table entries: 256 (order: 0, 4096 bytes)

NET: Registered protocol family 1

do_initcall_level level 6

hw perfevents: enabled with armv7_cortex_a5 PMU driver, 3 counters available

futex hash table entries: 256 (order: -1, 3072 bytes)

jffs2: version 2.2. (NAND) �© 2001-2006 Red Hat, Inc.

io scheduler noop registered (default)

ADI serial driver

adi-uart4.0: ttySC0 at MMIO 0x31003000 (irq = 20, base_baud = 7031250) is a ADI-UART4

console [ttySC0] enabled

loop: module loaded

adi-spi3 31042000.spi: registered ADI SPI controller spi0

adi-spi3 31043000.spi: registered ADI SPI controller spi1

m25p80 spi2.38: found w25q128, expected w25q32

m25p80 spi2.38: w25q128 (16384 Kbytes)

3 ofpart partitions found on MTD device spi2.38

Creating 3 MTD partitions on "spi2.38":

0x000000000000-0x000000080000 : "uboot (spi)"

0x000000080000-0x000000600000 : "kernel (spi)"

0x000000600000-0x000001000000 : "root file system (spi)"

adi-spi3 31044000.spi: registered ADI SPI controller spi2

libphy: Fixed MDIO Bus: probed

CAN device driver interface

bfin_can 31000200.can: bfin_can device registered(&reg_base=f4000200, rx_irq=22, tx_irq=23, err_irq=24, sclk=112500000)

bfin_can 31000a00.can: bfin_can device registered(&reg_base=f4000a00, rx_irq=25, tx_irq=26, err_irq=27, sclk=112500000)

stmmaceth 3100c000.ethernet: no reset control found

stmmac - user ID: 0x10, Synopsys ID: 0x37

Ring mode enabled

DMA HW capability register supported

Enhanced/Alternate descriptors

        Enabled extended descriptors

RX Checksum Offload Engine supported (type 2)

TX Checksum insertion supported

Wake-Up On Lan supported

Enable RX Mitigation via HW Watchdog Timer

libphy: stmmac: probed

eth0: PHY ID 20005c7a at 1 IRQ POLL (stmmac-0:01) active

usbcore: registered new interface driver usb-storage

musb-hdrc musb-hdrc.1.auto: MUSB HDRC host driver

musb-hdrc musb-hdrc.1.auto: new USB bus registered, assigned bus number 1

hub 1-0:1.0: USB hub found

hub 1-0:1.0: 1 port detected

mousedev: PS/2 mouse device common for all mice

input: 3100b000.rotary as /devices/platform/scb/3100b000.rotary/input/input0

i2c /dev entries driver

adi_wdt: initialized: timeout=20 sec (nowayout=0)

Driver 'mmcblk' needs updating - please use bus_type methods

Synopsys Designware Multimedia Card Interface Driver

Blackfin hardware CRC crypto driver

bfin-hmac-crc 31001200.crc: initialized

bfin-hmac-crc 31001300.crc: initialized

usbcore: registered new interface driver usbhid

usbhid: USB HID core driver

icc 20080000.icc: initialized

TCP: cubic registered

NET: Registered protocol family 17

can: controller area network core (rev 20120528 abi 9)

NET: Registered protocol family 29

can: raw protocol (rev 20120528)

can: broadcast manager protocol (rev 20120528 t)

musb-hdrc musb-hdrc.1.auto: VBUS_ERROR in a_idle (90, <VBusValid), retry #0, port1 00000100

can: netlink gateway (rev 20130117) max_hops=1

do_initcall_level level 7

ThumbEE CPU extension supported.

console [netcon0] enabled

netconsole: network logging started

/ch8/buildroot/linux/linux-kernel/drivers/rtc/hctosys.c: unable to open rtc device (rtc0)

IP-Config: Complete:

     device=eth0, hwaddr=02:80:ad:20:31:e8, ipaddr=192.168.1.3, mask=255.255.255.0, gw=192.168.1.1

     host=sc58x, domain=, nis-domain=(none)

     bootserver=192.168.1.5, rootserver=192.168.1.5, rootpath=

ALSA device list:

  No soundcards found.

Freeing unused kernel memory: 16860K (c04ed000 - c1564000)

Starting logging: OK

Starting mdev...

Starting watchdog...

Initializing random number generator... random: dd urandom read with 24 bits of entropy available

done.

Starting system message bus: done

Starting network...

/bin/sh: run-parts: not found

ssh-keygen: generating new host keys: ED25519

Starting sshd: OK

Starting inetd: OK

Welcome to Buildroot

buildroot login: stmmaceth 3100c000.ethernet eth0: Link is Up - 100Mbps/Full - flow control rx/tx

random: nonblocking pool is initialized

You answer me regarding the 60601-1 ed3 but not with the Amendement A1.

The Amendement A1 of the IEC 60601-1 has been published in 2012. This is why I am surprised to not find in your certificate the Amendement A1.

Since 2012 all the new medical designs are compliant with IEC 60601-1 ed3 with Amend A1.

Could you please check again if this component is or not compliant with IEC 60601-1 ed3 with Amend A1 ? It is very important for us.

Thanks in advance.

The question is related to adsp-sc584-ezboard can't detect USB device 

and my problem is adsp-sc584-ezboard  sometimes can't detect USB device,It seems be related to hardware,could you provide a bare-metal USB test code  that's independent with u-boot/Linux.my email is 271924295@qq.com,thanks~~

Hello

I have a custome board with a ADV7343.

My problem: I cannot determine how to set the subdata ranges.

Configuration asks for:

-Horizontal Synchronization width

-Horizontal Back Porch

- Horizontal Front Porch

also:

-Vertical Synchronisation width

-Vertical Back Porch

-Vertical Front Porch

my Video is 720x567 active in RGB888 with SD_HSYNC SD_VSYNC hardware

>>> how should it set theese values, where to look them up?

We are in the process of configuring the AD9364 from the external processor board (Beaglebone Black)

The configuration and setup code on External processor board(BBB) will configure ad9364 board using SPI.

Ad9364 board consist of Artix 7 FPGA and ad9364 ASIC. The SPI of FPGA is connected to BBB processor board on one end and FPGA on other end. FPGA SPI lines are kept through (shorted) for initial configuration, so that BBB processor board can configure ad9364.

To compile the code, we used the Ad9364 linux code from Ad9364 No-OS code stack, We Modified the plantform_linux/parameters.h file and compiled on the External processor board

we are getting the following runtime error...Kindly Support

Hi,

Need help with the SPI communication with the IMU ADIS16460. We are sending the IMU 16bit bytes and giving a time delay of 40 micro sec before reading again 16bit bytes in our code. But we are getting garbage values form the IMU.

For eg for checking the SPI communication on Page 11 of data sheet there is DIN = 0x5600 which should give a
DOUT= 0x404C(in number 16460). We are not receiving that. The DOUT received is of random values like 65535 which is 1111 1111 1111 1111. This DOUT values changes randomly when we switch off and switch on the IMU.

SCLK = 1MHZ

CODE used is as follwed just for debugging the SPI communication part:

#include <SPI.h>

int CS = 2;

void setup() {
  // put your setup code here, to run once:
  Serial.begin(115200);
  pinMode(CS,OUTPUT);
  digitalWrite(CS,HIGH);

  Serial.println("Wait for 5 secs");
 
  SPI.beginTransaction(SPISettings(1000000,MSBFIRST,SPI_MODE3));

  SPI.begin();
 
  Serial.println("Waited 5 Secs");
 
  digitalWrite(CS,LOW);
  SPI.transfer16(0x5600);
  digitalWrite(CS,HIGH);
 
  delayMicroseconds(40);
 
  digitalWrite(CS,LOW);
  int data2 = SPI.transfer16(0x00);
  digitalWrite(CS,HIGH);

//  Serial.println(data1);
  Serial.println(data2);
}
void loop() {
  // put your main code here, to run repeatedly:

}

I have a ADSP SC589 EZ-kit board and I want to use it's PCIe interface to connect a custom PCIe card. I configured the kernerl as followings:

Then I re-build the kernel. The output message display the sc58x-pcie 310b8000.pcie: link training failed.

The info is following:

sc58x-pcie 310b8000.pcie: Link training failed
sc58x-pcie 310b8000.pcie: PORT_LINK_DEBUG0 = 4a4a02, PORT_LINK_DEBUG1 = 8000000
sc58x-pcie: probe of 310b8000.pcie failed with error -110

By the way, I have populated the R417 and R418 by 0 OHM resistor to provide the reference clock to card and the card is work normal.

I want to know why the EZ-kit did not detect the card. What more settings are needed?

Thanks a lot.

Hi

I have a question ADA4350.

I using S0,S1,S2. no using S3,S4,S5.

6pin FB3,5pin FB4,4pin FB5 and 1pin SWB OUT is connect to GND .it is no problem?

And ,

When using ADA4350 and ADC, Is it no problem to change using chip select?

Best Regards

HOD

I am working with hmc 232A switch. The PCB used is 2 layer Rogers 4350B 10 mil thick. While testing at 9-10 GHz, I am not getting isolation as projected inthe data sheet. Can we cascade three switches to improve isolation to a higher value something like 90 dB. Do I need to house the pcb in an aluminium housing during testing. Can anyone suggest how to proceed to get rated performance.

R R Rao

reference clk is 10MHz，R counter=10， P=16，A counter=16，B counter=229.
have set Bit F5&F4(MUTE UNTIL LOCK DETECT) of control latch to "1" , The frequency of LO is 925MHz, meanwhile ,the tx signal is off and on alternately . but, when i set Bit F5&F4(MUTE UNTIL LOCK DETECT) of control latch to "0" , The frequency of LO is 930MHz, and the TX signal is normal. could you help me to solve this question？

Hi! I'm trying to calculate the crc of a buffer. I've tried following the instructions provided in the Help in CCES and also i've tried running the snipped code from  CCES Examples. In both cases I'm facing the same problem: the code keep remaining stuck inside the while loop because adi_crc_IsCrcInProgress never returns false.

  /* CRC Return code */
 ADI_CRC_RESULT eResult;
 /* CRC value */
 uint32_t Crc32Value;

 /* Initialize managed drivers and/or services */

 adi_initComponents();

// putting some values different from zero in the buffer
 DataBuf[0] = 32;
 DataBuf[100] = 43;
 DataBuf[3] = 2;

 /* Open a CRC device instance */
 eResult = adi_crc_Open (0, &CrcDevMem[0], ADI_CRC_DMA_MEMORY_SIZE, &hCrcDev);

 /* Reset CRC registers */
 eResult = adi_crc_StopReset (hCrcDev, true, true);

 /* Set CRC polynomial */
 eResult = adi_crc_SetPolynomialVal (hCrcDev, 3988292384);

 /* Sets data mirroring configuration */
 eResult = adi_crc_SetDataMirror (hCrcDev, ADI_CRC_MIRROR_NONE);

 /* Enable DMA mode for CRC */
 eResult = adi_crc_EnableDmaMode (hCrcDev, true);

 /* Register callback function if required */
 eResult = adi_crc_RegisterCallback (hCrcDev, CrcCallback, hCrcDev);

 /* Set CRC operating mode as Memory Scan Compute Compare */
 eResult = adi_crc_SetOperatingMode (hCrcDev, ADI_CRC_MODE_SCAN_COMPUTE_COMPARE);

 /* Set CRC data word count and Reload word count */
 eResult = adi_crc_SetDataCount (hCrcDev, 512, 0);

 /*
 * Set the expected CRC32 value.
 * Pass this value as 0 if the CRC value for the the data stream is unknown.
 * The CRC device will return a CRC data compare error at the end of
 * CRC operation. Ignore this error and read the CRC final result register.
 * This register holds the CRC value calculated for the data stream.
 */
 eResult = adi_crc_SetExpectedVal (hCrcDev, 0);

 /* Set the current CRC status flag as CRC operation in progress */
 bCrcInProgress = true;

 /* Submit CRC buffer to Scan-Compute-Compare */
 eResult = adi_crc_DmaMemFillScan (hCrcDev, &DataBuf[0], 512);

 /* Wait until the CRC operation is complete or CRC error */
 while (bCrcInProgress && (bCrcDataCompareErr == false) && (bCrcDmaErr == false))
 {
 /*
 * Query the current status of CRC operation if operating in non-blocking mode
 * This function call is not required for callback mode
 */
 eResult = adi_crc_IsCrcInProgress (hCrcDev, &bCrcInProgress);
 }

 /*
 * Read the final CRC result if the CRC value for the buffer is yet to be calculated
 * This function also resets the registers that hold the final and intermediate CRC values
 */
 eResult = adi_crc_GetFinalCrcVal (hCrcDev, &Crc32Value);

 /* Handle CRC error, if any */

 /* Close CRC Device */
 eResult = adi_crc_Close (hCrcDev);

The callback function simply puts the flags to true/false if corresponding events occurs but it never gets called.

What I don't understand is that if I put a delay after adi_crc_DmaMemFillScan and I just call adi_crc_GetFinalCrcVal without the while loop, Crc32Value is correctly set.

I'm using BF707 in BLIP2 platform.

Am I using the APIs wrong? Is there some further setting I'm missing?

Thanks for your help

Chiara

Hi

We are using AD9361 Rx AGC in manual gain control mode with full table gain index writes from the SPI to register 0x109.

We are measuring the time for the new gain to take effect on the rx chain. This is done by triggering the logic analyzer to capture the received digital IQ data on SPI gain write to register 0x109 in the FPGA. These lines are probed out to the debug board for this purpose.

We see that the gain takes effect on the received digital IQ after ~70 microseconds (actually it varies between ~70 microseconds to ~100+ microseconds, depending on if we are programming from the SPI script using the direct_reg_access or through the GUI).

First, is this gain update time correct?, Next, Would like to know if there is any specific register setting of AD9361 which will reduce this time for the gain to take effect on the receiver chain.

Look forward to your advice.

Thank you

We are working with the ZC706 and AD9371 evaluation board provided by ADI. The setup works fine with the ADI IIO tools.

We wanted to analyze the power consumption of the AD9371 for various cases by individually turning Tx or Rx channels ON/ OF. For our application we want to operate the AD9371 as Rx only or Tx only in some cases. We connect an external 12V DC supply to the AD9371 board by bypassing one of the fuse connection.

From the GUI settings  we disable both Tx1 and Tx2 first and keep Rx1 and Rx2 ON. As a result, we see the current consumption of the AD9371 go down. But we cannot plot the IQ data from the Rx1 and Rx2 ports. We also see the following error commands indicating an internal RF PLL lock failure :

 root@analog:~# ERROR: 352: MYKONOS_waitArmCmdStatus() exited due to ARM error for the desired ARM opcode
ERROR: 255: ARM Command Error in MYKONOS_setRfPllFrequency()
ad9371 spi32766.1: PLLs unlocked b

A similar observation was made when we disable both Rx1 and Rx2 but keep Tx1 and Tx2 ON. The current consumption reduced from normal case, but we do not see any output from the Tx ports.

So our question is, how can we measure the TX and RX power consumption individually with the GUI tools provided by ADI ?

Thanks

Using Midas-Link and the IAR v5.4 IDE to program the ADuC7060 eval board (and our design derived from that) works fine.  However, the production environment uses the Segger Flasher portable programming box, and i have not gotten the Segger tools to operate with the 7060.  The Segger J-FlashARM V4.54c tool has worked with all the other micro's we use, but not yet on the 7060.  In all cases, this tool just freezes right away (and i have to windows-kill it) when it tries to Connect.  I've tried using 3 different Jlink boxes (Midas, IAR, and the Segger Flasher); I've tried changing the "Reset" to the "Type 2" (the software specific one for ADuC micros); I've changed the JTAG speed down to 100Khz; and all freeze.  I do not know where to start looking so any suggestions would be appreciated.

Please provide a working example for SPI reception using DMA. 

Thank you

Hi,

One of our customers came accross the ADV7611 mini board that is depicted in CN0282. He would like to evaluate this and base his design on it. If I am right, this is not the same as the ADV7611 evaluation board (can't find pictures of this one).

Can he acquire this 'mini board' (or can we, and loan it to him)?

Thanks!

Rob

Hi all,

I have an ADuC7023 evaluating board ---EVAL-ADUC7023QSPZ, when I'm writing the *.hex file, it shows can't connect with J-LINK. It was good when change the chip, it was damaged again after rewrite. Measured the P0.0  voltage, it's about 3.3V, and not in a serial download mode. J-FLASH has the tips as below:

“- Connecting ...
- ERROR: ADI system TAP: Could not read system TAP Id.
- ERROR: ADI system TAP: Could not read system TAP Id
”

For more details, pls look at the pictures!

When building a project for the SC589 in Cross Core, the .ld/.ldf map the shared L2 SRAM as follows (as noted in the SHARC app.ldf):

bank1 2008_0000 2008_7FFF 4KB uncached - ICC
         4KB uncached - MCAPI ARM
         4KB uncached - MCAPI SHARC1
         4KB uncached - MCAPI SHARC0
         16KB uncached - ARM
bank2 2008_8000 2008_FFFF 32KB cached - ARM
bank3 2009_0000 2009_7FFF 32KB cached - ARM
bank4 2009_8000 2009_FFFF 32KB cached - ARM
bank5 200A_0000 200A_7FFF 32KB cached - SHARC1
bank6 200A_8000 200A_FFFF 32KB cached - SHARC1
bank7 200B_0000 200B_7FFF 32KB cached - SHARC0
bank8 200B_8000 200B_DFFB 24KB cached - SHARC0

The linkers for both the ARM and SHARC will allow you to reapportion the memory differently, but this does not change the fact that BANK 2 - 8 continue to be cached.

Is my desire to reconfigure a large portion of this RAM as uncached, however I see no mechanism to achieve this.  Any help would be greatly appreciated.