LTC4001 Starting/Stopping

July 17, 2018, 8:17 am

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Hello!  I am working with a LTC4001 along with a Panasonic 20700 battery and am having some issues.  The part will start up and I can see the switching begin while the current ramps up to charge the battery - but then everything stops and the part resets.  If you probe the softstart line, it looks like a sawtooth with it coming up appropriately but then shutting back down.  Attached is the schematic.  I have tried dropping the input and output capacitors down to the 10uF minimums as well with the same results.  Hopefully its something dumb I have done, help!

 

Notes : I do not want temperature monitoring involved, I would like the battery to charge at 2A, and flag me that the charging is complete when the charge current gets to 80mA or below.

 

Thank you!

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External LO in TDD

July 12, 2018, 12:11 pm

≫ Next: How can the output voltage of a power converter be dynamically adjusted in no-opto isolated applications (using LT3748)?

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Hello. Is there a detailed guide on using external LO source with AD9361 in TDD. It appears that the 9361 expects the LO to be present at certain times during initialization and in RX/TX window. This was proved by supplying a constant, non bursty LO from a signal generator. Otherwise, there are quadrature, magnitude, and phase errors in the transmit waveform. Overall, our system works. We receive and transmit with degraded EVM. Can someone help? Thanks. 

How can the output voltage of a power converter be dynamically adjusted in no-opto isolated applications (using LT3748)?

July 17, 2018, 9:16 am

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I am using LT3748 in a flyback configuration to generate a regulated 2V-5V/3.5A output from 10-30V input voltage and would like to control the output voltage from a reference signal. I tried sourcing/sinking current to/from the reference point (Rref) but the output is not well regulated (the output voltage does not change linearly with the reference and there are regions where large 1-10Khz oscillations occur). Is there any other way to dynamically control the output voltage?

Lock Detect Signal Output from FMCOMMS-4

June 25, 2018, 4:32 pm

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Hello,

 

I am trying to use the AD9364 (on a AD-FMCOMMS4-EBZ with ZedBoard) as a sweeping signal generator where I am stepping the frequency from 2GHz to 3GHz with 20MHz steps. I am using the No-OS drivers (hdl_2016_r2 branch) and using the fastlock profiles (saving them in BBP and then loading them). I need to generate an output signal every time a new frequency is locked to trigger some external components. Is there any lock detect output signal that I can get the output from the FMCOMMS-4 board? Or can I drive a GPO pin every time the LO goes to a new frequency?

 

Thanks in advance.

Can an RF attenuator be used in non RF applications?

July 17, 2018, 1:34 pm

≫ Next: How to Ultra-low voltage AC-DC Convertor (Need something similar to LTC3108)

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I need an attenuator that will attenuate a signal from dc to 100MHz by a factor of 1 to 10. The signal could be up to 20Vp-p. Could an RF attenuator be used for this? Thanks

I

How to Ultra-low voltage AC-DC Convertor (Need something similar to LTC3108)

July 7, 2018, 7:34 pm

≫ Next: Problem with several readback action in adau1701

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Hi Power by Linear,

 

I have a ranging voltage of 0-340mV AC that I wish to step up and convert to DC. Most rectifiers will draw at least 400mV resulting in no more voltage to be converted to DC.  I am most interested in the LTC3108 DC-DC converter as it will both step up the voltage, and hold it steady for the operating voltages of 20-500mV. Do you have any suggestions?

 

Respectfully,

John

Problem with several readback action in adau1701

July 9, 2018, 8:40 am

≫ Next: AD9172 custom design mismatching jesd204 parameters

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Hello everyone. I have the following setup to evaluate the readback block.

I use a microcontroller via SPI communication. In my program I write 5 in DC1 and 3 in DC2, so I should read 15 in readback1 and 9 in readback2.

In sigma studio the readback1 counter is 0x0152 and readback2 counter is 0x0146.

In my test program I have the following:

- Write 5 in DC1

- Write 3 in DC2

- Write 0x0152 in readback1

- Read readback1 (read 15)

- Write 0x0146 in readback2

- Read readback2 (read 15)

- Write 0x0152 in readback1

- Read readback1 (read 15)

- Write 0x0146 in readback2

- Read readback2 (read 15)

In this case I read 15 in all attempts. 

 

However, if I have the following:

- Write 5 in DC1

- Write 3 in DC2

- Write 0x0146 in readback2

- Read readback2 (read 9)

- Write 0x0152 in readback1

- Read readback1 (read 9)

- Write 0x0146 in readback2

- Read readback2 (read 9)

 

- Write 0x0152 in readback1

- Read readback1 (read 9)

I read 9 in all the cases.

 

Why does the result read is wrong? 

Thanks in advanced.

AD9172 custom design mismatching jesd204 parameters

July 10, 2018, 3:17 am

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Hi,

 

I'm currently developing a project based on the AD9172. For that purpose, I bought one eval board and the ADS7v2.

They work correctly together and now I want to use another FPGA board (the ZCU102), so I designed a simple FPGA project based on the JESD204 IP from Xilinx.

 

I want to use JESD204 mode 2 (3 lanes). I configured the IP like this (IP core shared in design):

I program the FPGA and then I set the DAC with ACE like this:

I must change some registers because my clocking scheme is the following:

For the AD9172:

Registers	Value	Comments
0x308	0x8	physical lane 0 correspond to logical lane 0, phy 1 to log 1 etc.
0x309	0x10
0x95	0x0	Enable PLL
0x790	0	Required
0x791	0	Required
0x796	0xE5	Required
0x7A0	0xBC	Required
0x794	0x08	Recommended CP current
0x797	0x10	Required
0x797	0x20	Required
0x798	0x10	Required
0x7A2	0x7F	Required
Pause 100 ms
0x799	0xC3	Output clk = dac clock /4, N div=3
0x793	0x18	Input divider = 1
0x94	0x00	DAC clock = VCO / 1
0x792	0x2	Reset VCO
0x792	0
Pause 100 ms
0x7B5	READ	If locked, equals 1

For the HMC7044:

Registers	Value	Comments
3	0x2C	Disable PLLs
5	0x6F	CLKIN1 as external VCO input
0x64	0x1	External VCO
0xED	0	CLKOUT3 output mux = channel divider
0x151	0	CLKOUT13 output mux = channel divider
0x14B	0x40	CLKOUT13 divided by 64 -> 500 / 64 = 7.8125 = sysref to FPGA
0x14C	0
0xE7	0x40	CLKOUT3 divided by 64 -> 500 / 64 = 7.8125 = sysref to DAC
0xE8	0
0xE3	0	CLKOUT2 output mux = channel divider
0x147	0	CLKOUT12 output mux = channel divider
0xDE	0	CLKOUT2 divided by 2 -> 500 / 2 = 250 = data rate clock unused because external dac clock
0xDD	0x2
0x142	0	CLKOUT12 divided by 2 -> 500 / 2 = 250 = data rate clock to FPGA
0x141	0x2

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ltc3807

July 10, 2018, 3:14 am

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Hello,

I planned to use the LTC3807 in order to make a power supply with a current between 20A and 25A.

 

I saw a current limit at 25A in the product list on the website and a limit of 20A in the LTC power CAD software.

My questions are :

- What is the current limit for this component?

- What is the reason of this limit, all switching components are externals so could you explain me why there is a current limitation (Duty cycle, gate driver,...)

 

Thanks

Matthieu Baque

ADP5062 JEITA1 Mode

July 2, 2018, 9:26 am

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Hello Gents,

 

I need one confirmation please:

 

When operating under JEITA1, does ADP5062 use the Beta NTC coefficient for any matter? I see in the below table it considers instead standard resistors measurements as follows:

 

 

Can you please confirm CI operation of beta for JEITA1 mode?

 

Thanks!

 

Att

 

Juliano

LTC2323-14 TDSCKCLKOUT

June 27, 2018, 3:28 pm

≫ Next: ADA2200 - Circuit Example Suggests 125kHz Demod Operation?

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Hi Gentleman, 

 

Could you please detail LTC2323-14 TDSCKCLKOUT spec?

 

Why we do only have a minimum value in the datasheet? is there a spec for Maximum Values or is it related to a variable timing depending on application that cannot be measured?

 

Thanks

ADA2200 - Circuit Example Suggests 125kHz Demod Operation?

July 12, 2018, 4:22 pm

≫ Next: peak voltage detect for ultrasonic waveform

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The context for this question is as a high frequency response LVDT Signal Conditioner.

I was looking at the ADA2200 datasheet when I came across this passage in applications information:

ADA Datasheet pg17

From what I see here it suggests that the ADA2200 can be run using a 1MHz clock and can output demod at 125 kHz.

 

Question 1: Doesn't the datasheet say that a max 500kHz clock should be used and that only up to a ~30kHz output can be attained (~60 kHz output sample rate, ~30kHz after Nyquist)? Did I miss something?

 

Question 2: Is the multiplexer ADC viable for increasing output frequency on one channel? It shows application for multiple channels, but what if I used the same channel as inputs? Could I use two ADA2200 units in the formation suggested above and get 60kHz out?

peak voltage detect for ultrasonic waveform

July 12, 2018, 6:40 pm

≫ Next: Modifying AD9208 FPGA for ACE

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Hello, I'm looking for a method to detect the peak voltage of ultrasonic waveform. The waveform is shown in below. The frequency of the signal is 500KHz.

This waveform is viewed with CH2 configured AC.

 

The DC bias is 1.5V and it is an output from an amplifier. I wonder if LTC5507 could do this.

Modifying AD9208 FPGA for ACE

July 2, 2018, 11:32 am

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I am currently working with the Ads7-v2ebz and AD9208-3000ebz for a unique evaluation. I have modified the FPGA image that is on the analog website (https://wiki.analog.com/_media/resources/eval/ads7-v2ebz_13052_revc_design_files.zip) and would like to have this loaded on the FPGA from the ACE software sutie rather the manually with a JTAG connection. To give an overview I’m using the ACE software suite to collect data, currently just noise, with the modified FPGA image. The FPGA image is a modified version of the AD9689_AdS7v2.xpr that is contained in the zip file I linked to above, the modification is rather simple; I’m replacing the first 8-bytes in a data packet with a custom value. There is not documentation for the FPGA project, and I’m hoping to get a better understanding of the data flow and design itself. I’ve use my best intuition after reading the HDL to make the modifications but verifying I’ve interpreted the data flow would be useful.

 

Currently when I load the FPGA via JTAG with my custom image the ACE software panics a little (I’m not sure if it reloads the FPGA or not either) I’ve managed to do some data collections with what I suspect to be the modified FPGA but I’m not able to the connect to the ILA to view the internal signals. So here are a few things I’d like to know about:

 

1. Can I override the FPGA that the ACE software suite loads? So that I don’t have to load it via JTAG and hopefully this would cause fewer issues.
2. Can I  get more design documentation on the FPGA image for the ads7-v2ebz? The Vivado project is the AD9689_AdS7v2.xpr. I compared the chips and believe there is no issue using this image for the AD9208 but perhaps there is a project specifically for this chip.

2b. The external trigger functionality in the FPGA was a little difficult to follow so if a document doesn’t exist can we some get information on the data flow with an external trigger and how the ACE suite will collect that data?

ADF5355 Modulus Value(MOD2) setting

July 17, 2018, 5:33 pm

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Hello,

 

I received a question about MOD2 setting of ADF5355. According to the datasheet of ADF5355, the setting of "1" and "2" are not allowed. Are there any probles if we use these setting?

 

Best regards,

Akira

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CSC function of ADV7513

July 15, 2018, 3:43 am

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Hello.

 

The customer are facing the problem with CSC function of ADV7513. 

So would you tell us the specification of CSC function.

 

-YCbCr 4:2:2 input -> CSC : it looks vertically-striped pattern

-YCbCr 4:2:2 input -> convert 4:2:2 to 4:4:4 -> CSC : OK

-YCbCr 4:4:4 input -> CSC : OK

 

According to above result, it seems the CSC cannot handle 4:2:2 input.

Can't the CSC function accept the 4:2:2 input?

 

Your support would be appreciated.

 

Best regards.

Kikka

no output signal for LTC2247

July 11, 2018, 2:35 am

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Hi there,

 

I am using LTC2247 ADC to convert RF analog signal to digital. I have seen the differential input signals on the corresponding pins but there is no signal on the output pins. There might be two possiblities: 

1. I did not programmed the chip correctly.

2. The chip is not working correctly.

 

For the first one, I have tested the signal on the scope and it seems all right(might be wrong).

For the second one, I want to know is there anyway to know if the chip is still working well?

 

thanks

yong

AD9154 work configuration

July 13, 2018, 10:45 pm

≫ Next: AD2S1210 velocity 0 Resolver position

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Can you give the FPGA code of AD9154 concerning the JESD204B IP configuration and AD9154 register configuration? I can't get the AD9154 working properly at the moment. thank you

AD2S1210 velocity 0 Resolver position

July 10, 2018, 6:08 pm

≫ Next: LTC2312-12 Rising edge timing of CONV & SCK

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Hello

 

I have questions when the resolving velocity of the resolver is 0.
· Can AD2S1210  detect the position after startup or reset
· We use two resolvers for switching. Is it possible to detect when the resolver on the switched side is stationary?

 

Thank you.

LTC2312-12 Rising edge timing of CONV & SCK

July 10, 2018, 6:54 am

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Hello,

 

According to the datasheet of LTC2312-12, it is recommended to hold SCK static low or high during tconv.

Are there any problems if the rising edge of CONV and the rising edge of SCK is same timing?

 

Best Regards,

Akira