Hi
I'd like to know how to calculate the input current of LTC2620 reference input. The resistance under Normal Mode condition is 16kohm typ. When the reference voltage is +2.5V, may I calculate the current as 2.5V/16kohm = 0.15mA? Otherwise 0.15mA*8=1.2mA, because there are 8 DACs in LTC2620.
Regards,
Hiroyuki
Hi
There is no data for absolute maximum ratings of supply voltages VDD25_DAC, VDD12A, VDD12_CLK, VNEG_N1P2, DVDD, IOVDD7, VDD_1P2, VTT_1P2, DVDD_1P2, PLL_LDO_VDD12, PLL_CLK_VDD12, SYNC_VDD_3P3 and BIAS_VDD_1P2 in AD9161 data sheet. Could you give me the data?
Regards,
Hiroyuki
We plan to use the AD9172 in our system but for now we are looking for a way to rapidly test the system. It should act as:
Actually, the complete system should act like the AD9958 but with synthesized frequency up to 3 GHz rather than 250 MHz.
The AD9172+FPGA satisfies these conditions but it takes man-years to build that from scratch. I am wondering if the evaluation boards (EVAL-AD9172, ADS7-V2EBZ, AD-HSDACFX3-EBZ) can be easily used to test this kind of setup.
Yes, the EVAL-AD9172 can be hooked up to an FPGA board directly with the FMC connector but again - it takes man-months/years to get it up and running.
For evaluation, I could even think storing test vectors of certain frequencies to be synthesized in some big RAM of ADS7-V2EBZ. However, the crucial part is synchronization with the (external) UPDATE signal.
Any insights are greatly appreciated. Thanks!
I am using an ADS7-V2EBZ and DPG Downloader to provide 12-bit patterns. I also have a test setup using the ZCU102 Zynq Ultrascale+. In both cases, the JESD link is up and running and I can see data being transmitted via Xilinx ILA debugger, but I detect no signal on either TX0 or TX1 outputs besides a spike at the sampling frequency.
Is there any documentation on this?? I have verified the functionality of multiple 16-bit modes but cannot get a 12-bit mode to work, not even using exclusively AD dev. boards and tools. The datasheet says nothing of 12-bit mode configuration save for JESD link parameters, which I have ensured are correct.
Please advise!!
-Dan
Hi AD team, please answer the following questions:
1. The LTM4622A datasheet says (in the Description section):
Fault protection features include input overvoltage, output overcurrent and overtemperature protection.
However, no explanation is given on the overcurrent protection mechanism. Hence the question: is the LTM4622A module output protected against short-circuit condition? If yes, how this protection works (shut-down with soft start upon short-circuit elimination, etc.) If the protection is implemented as output current limiting, then what is the current limit when both channels are paralleled, and the output voltage is in the range 4 to 10V?
2. Suppose the module is operating at 10V output, the output current being 1 to 1.5A (once again, both channels are paralleled). What happens if the external feedback resistor is instantly changed from 3.86 kOhm (corresponding to 10V output) to 10.6 kOhm (corresponding to 4V output)? Is it safe for the module to perform an output voltage transition in this way?
3. Will the LTM4622A module stay in production in the coming years?
Thanks in advance and best regards,
Michael
Here i am trying to comm with I2C through SDA and SCL of Arduino uno board.
its starting stage im not able to read the data in register of ad7156
its showing FF for all reg.
hardware connection in correct and logical level converter connected between both boards.
here i attached the my code and verify help to resolve this issue.
what is address of I2C in ad7156?
For write?
for read?
Hi.
In datasheet AD9739 in page 40:
It has been found through characterization that the optimum setting is for both inputs to be biased at approximately 0.8 V. This can be achieved by writing a 0x0F (corresponding to a −15) setting to both cross controller registers (that is, Register 0x22 and Register 0x23).
As we can see from datasheet default values of this registers = 0. What internal offset voltage is default on pins DACCLK? How this internal voltage changes by different values of registers?
There were two issues. For both I found workarounds. (Building with Vivado 2018.2.)
Issue 1: Project build errors.
Excerpt from build log:
...
## source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl
...
### ad_connect sys_ps8/emio_spi0_ss_i_n VCC
...
ERROR: [IP_Flow 19-3460] Validation failed on parameter 'Const Width(CONST_WIDTH)' for "Const Value is out of range -0:1 allowed by width"
. BD Cell 'sys_ps8_emio_spi0_ss_i_n_VCC'
ERROR: [IP_Flow 19-3460] Validation failed on parameter 'Const Val(CONST_VAL)' for Const Value is out of range -0:1 allowed by width
. BD Cell 'sys_ps8_emio_spi0_ss_i_n_VCC'
Workaround 1: In zcu102_system_bd.tclcommented out offending lines 100 and 113 :
100 #ad_connect sys_ps8/emio_spi0_ss_i_n VCC
113 #ad_connect sys_ps8/emio_spi1_ss_i_n VCC
Issue 2: In synthesis got two errors (subsequently)
ERROR: [Synth 8-1766] cannot open include file inc_id.h [/data/nas/md12-fs17/md12-fs17/ES/ECAD/stargazer_fpga/users/walsh/RS/debug/hdl-master/projects/adrv9009/zcu102/adrv9009_zcu102.srcs/sources_1/bd/system/ipshared/6002/address_generator.v:74]
ERROR: [Synth 8-1766] cannot open include file resp.h [/data/nas/md12-fs17/md12-fs17/ES/ECAD/stargazer_fpga/users/walsh/RS/debug/hdl-master/projects/adrv9009/zcu102/adrv9009_zcu102.srcs/sources_1/bd/system/ipshared/6002/response_generator.v:58]
Workaround 2: Copied the missing files from other folders. Completed synthesis/implementation/bit file generation in the GUI.
I want to know the model of write connector.
and what connector can be connected it .
Hi,
We currently has the application and require to charge 1.2V 200 cells in series.
LTC6813-1 is a potential IC and support Multiple device in daisy chain.
I would like to consider applying 6pcs LTC6813-1. However, I find that datasheet has the statement "Stackable Architecture Supports 100s of Cells".
Does it mean stackable LTC6813-1 only capable to charge up to max 100 cells in series?
If yes, kindly advise if ADI have any alternative solution for 200 cells.
Thank you.
Dear all
I am looking for a Digital to analog converter with SDK support for Android and iOS .
That kind of product is available or not
According to the LTC6813-1 demo board manual page 11,
http://www.analog.com/media/en/dsp-documentation/evaluation-kit-manuals/DC2350AF.PDF
Software Setup need
1. Download and install Arduino IDE ... I currently downloaded from windows store
2. Using bmsSketchbookBeta.zip provided by ADI... I do not know how to get it?
Later, it seems that you can only use the Arduino IDE's Serial Monitor window for some simple commands (as a textual interface).
So ADI doesn't plan to use QuikEval anymore? No GUI ?
Thanks!
In the demo board manual I can see screenshots from it but they're not included in the actual sketchbook download.
Guess I shoudn't be a big deal to update the code for the ltc6811 but if someone already did the work, why do it yourself.
Hope someone has some information
This has yet to be my most complex Tutorial and I hope not the final one...I call it Audio Filter control. In fact it is many things in one. I have finally achieved UART immortality by being able to control everything from it. I can turn LED on and OFF. Set the BLINK Rate among many different rates, turn Audio ON and OFF and lastly, turn a Cross-Over filter ON or OFF. You might want to turn the LED OFF while the filter is executing or you might get weird feedback. I guess I'm not perfect, so nothing is stopping you from correcting my quickly written code that included the work of brilliant people here on the Forum. @PatrickG and @UweS to mention a few great minds...Lets move on, shall we ?!
This example can be a bit daunting, but it is really quite simple even underneath the surface. I have used Will Pirkle's excellent software called RackAFX to test my prototype whose simple parameters are passed passed in at the console. The only commands you need to know in this incarnation of the software are really: aud on / aud off /filt on / filt off.
Check out my other indepth tutorials for the other commands which are clearly obtained by typing term at the PUTTY terminal i.e.
The terminal is very self explanatory, so go ahead and experiment with the different terminal commands. The neat thing in this version is that you can simply engage a mode of the terminal that works for you by commenting or un-commenting one line at the top of the source! If you used the definition as you see below, it means you are running UART as DMA interrupt device. If you comment the line out you are only running interrupts RX and TX without DMA. The choice is yours!
// Comment out #define USE_UART_DMA to only engage UART in interrupt mode!
#define USE_UART_DMA
One you turn audio on via terminal command aud on you are on your way to play around with various instruments to feed audio into the line intput port and feed the output port to a scope, or head phones...
while the aud on or filt on is immediately typed at the PUTTY terminal console, you should see something on your scope that looks similar to either an audio signal passed in or perhaps an oscillator pulse from RackAFX.
If you engage UweS cross-over FIR filters, it can be done with filt on / filt off.
I hope you found this tutorial useful. Let me know how it works out for you. As always I have attached the source code for it. If you can improve it and make it better also let me know how! I will evolve the terminal so that filter coefficients can be passed in automatically from a graphic environment. More on this later...
Cheers,
Mario G.
Firmware Engineer
Hello Everyone,
I am trying to connect the AD-FMC-DAQ2 to KCU105 FPGA, and reccently I met the problem with setting up the AD9144. I have used the following code to do the basic setup, then I give the digital signal and get the waveform from the oscilloscope, from which the frequency is 250MHz. Now I want to make the change so I can get the different frequency，and I have several questions about the setup code, which is referred from : EngineerZone: Message List
1. The input reference clock sourced from input port is 1GHz, I am confused about the DAC CLK, does it use the DAC PLL or directly use the input reference CLK?
2. In the section of required device configurations, why set (0x1c4, 0x73) since I found it should be set 0x7e in AD9144 manual.
3. What does (0x291, 0x49) mean since I didn't find it in the manual.
int wr_reg_spi (int dev, unsigned long offset, unsigned long data)
{
//ioctl ( 3, 0xffff & (~(0x1 << (dev-1))));
*((uint32_t *) map_base + (0x0002) ) = 0xffff & (~(0x1 << (dev-1)));
usleep(1000);
//printf("wr_reg:%X\n", 0xffff & (~(0x1 << (dev-1))));
//ioctl ( 4, ((offset<<8)+data)<<8);
*((uint32_t *) map_base + (0x0000) ) = ((offset<<8)+data);
*((uint32_t *) map_base + (0x0001) ) = 0x1;
usleep(1000);
//printf("wr_reg:%X\n",((offset<<8)+data)<<8);
//ioctl ( 3, 0xffff);
*((uint32_t *) map_base + (0x0002) ) = 0xffff ;
usleep(1000);
//printf("wr_reg:%X\n",0xffff);
return 0;
int cfg_DAC()
{
wr_reg_spi(1,0x000, 0x81); // reset
wr_reg_spi(1,0x000, 0x00); // reset
wr_reg_spi(1,0x011, 0x00); // dacs - power up everything
wr_reg_spi(1,0x080, 0x00); // clocks - power up everything
wr_reg_spi(1,0x081, 0x00); // sysref - power up/falling edge
// required device configurations
wr_reg_spi(1,0x12d, 0x8b); // data-path
wr_reg_spi(1,0x146, 0x01); // data-path
wr_reg_spi(1,0x520, 0x1c); // sysref-armed
wr_reg_spi(1,0x040, 0x00); // current
wr_reg_spi(1,0x041, 0x02); //
wr_reg_spi(1,0x042, 0x00); //
wr_reg_spi(1,0x043, 0x02); //
// wr_reg_spi(1,0x146, 0x00); //
// wr_reg_spi(1,0x520, 0x1e); //
// wr_reg_spi(1,0x521, 0x00); //
// wr_reg_spi(1,0x522, 0x00); //
// wr_reg_spi(1,0x523, 0x00); //
// wr_reg_spi(1,0x524, 0x00); //
wr_reg_spi(1,0x2a4, 0xff); // clock
wr_reg_spi(1,0x1c4, 0x73); // dac-pll
wr_reg_spi(1,0x291, 0x49); // serde-pll
wr_reg_spi(1,0x29c, 0x24); // serde-pll
wr_reg_spi(1,0x29f, 0x73); // serde-pll
wr_reg_spi(1,0x232, 0xff); // jesd
wr_reg_spi(1,0x333, 0x01); // jesd
// digital data path
wr_reg_spi(1,0x112, 0x00); // 2x interpolation
wr_reg_spi(1,0x110, 0x00); // 2's complement
wr_reg_spi(1,0x111, 0xa0); // fdac/4 modulation
wr_reg_spi(1,0x13c, 0xff); // I gain
wr_reg_spi(1,0x13d, 0x07); // I gain
wr_reg_spi(1,0x13e, 0xff); // Q gain
wr_reg_spi(1,0x13f, 0x07); // Q gain
// transport layer
wr_reg_spi(1,0x200, 0x00); // phy - power up
wr_reg_spi(1,0x201, 0x00); // phy - power up
wr_reg_spi(1,0x300, 0x01); // single link - link 0
wr_reg_spi(1,0x450, 0x00); // device id (0x400)
wr_reg_spi(1,0x451, 0x00); // bank id (0x401)
wr_reg_spi(1,0x452, 0x04); // lane-id (0x402)
wr_reg_spi(1,0x453, 0x83); // descrambling, 4 lanes
wr_reg_spi(1,0x454, 0x00); // octects per frame per lane (1)
wr_reg_spi(1,0x455, 0x1f); // mult-frame - framecount (32)
wr_reg_spi(1,0x456, 0x01); // no-of-converters (2)
wr_reg_spi(1,0x457, 0x0f); // no CS bits, 16bit dac
wr_reg_spi(1,0x458, 0x2f); // subclass 1, 16bits per sample
wr_reg_spi(1,0x459, 0x20); // jesd204b, 1 samples per converter per device
wr_reg_spi(1,0x45a, 0x0a); // HD mode, no CS bits
wr_reg_spi(1,0x45d, 0x49); // check-sum of 0x450 to 0x45c
wr_reg_spi(1,0x46c, 0x0f); // enable deskew for all lanes
wr_reg_spi(1,0x03a, 0xc1); // sysref-armed
wr_reg_spi(1,0x476, 0x01); // frame - bytecount (1)
wr_reg_spi(1,0x47d, 0x0f); // enable all lanes
// physical layer
wr_reg_spi(1,0x2aa, 0xb7); // jesd termination
wr_reg_spi(1,0x2ab, 0x87); // jesd termination
wr_reg_spi(1,0x2b1, 0xb7); // jesd termination
wr_reg_spi(1,0x2b2, 0x87); // jesd termination
wr_reg_spi(1,0x2a7, 0x01); // input termination calibration
wr_reg_spi(1,0x2ae, 0x01); // input termination calibration
wr_reg_spi(1,0x314, 0x01); // pclk == qbd master clock
wr_reg_spi(1,0x230, 0x28); // cdr mode - halfrate, no division
wr_reg_spi(1,0x206, 0x00); // cdr reset
wr_reg_spi(1,0x206, 0x01); // cdr reset
wr_reg_spi(1,0x289, 0x04); // data-rate == 10Gbps
wr_reg_spi(1,0x280, 0x01); // enable serdes pll
wr_reg_spi(1,0x280, 0x05); // enable serdes calibration
wr_reg_spi(1,0x268, 0x62); // equalizer
// cross-bar
wr_reg_spi(1,0x308,0x11); // lane selects
wr_reg_spi(1,0x309,0x03); // lane selects
// data link layer
wr_reg_spi(1,0x301, 0x01); // subclass-1
wr_reg_spi(1,0x304, 0x00); // lmfc delay
wr_reg_spi(1,0x305, 0x00); // lmfc delay
wr_reg_spi(1,0x306, 0x0a); // receive buffer delay
wr_reg_spi(1,0x307, 0x0a); // receive buffer delay
wr_reg_spi(1,0x03a, 0x01); // sync-oneshot mode
wr_reg_spi(1,0x03a, 0x81); // sync-enable
wr_reg_spi(1,0x03a, 0xc1); // sysref-armed
wr_reg_spi(1,0x300, 0x01); // enable link
// dac calibration
wr_reg_spi(1,0x0e7, 0x38); // set calibration clock to 1m
wr_reg_spi(1,0x0ed, 0xa6); // use isb reference of 38 to set cal
wr_reg_spi(1,0x0e8, 0x03); // cal 2 dacs at once
wr_reg_spi(1,0x0e9, 0x01); // single cal enable
wr_reg_spi(1,0x0e9, 0x03); // single cal start
wr_reg_spi(1,0x0e7, 0x30); // turn off cal clock
return 0;
}
I really hope anyone who has the relevant experience can help me with it, thank you soooo much!!
Hello , guys!
I have finished the installation of IIO-OSC following the steps of IIO Oscilloscope [Analog Devices Wiki] . However, once I wanted to turn on the OSC , it always showed the errer that
ERROR: Bad URI: 'usb:expected_error'
And the interface of IIO-OSC shows nothing like:
Does anyone who has the relevant experience or knowledge can help me with that ? Thank you so much !!!
Dear All!
I have a problem in reset NCO phase of all channel ( include channel data path, main data path, 2 DAC) synchronize with sysref signal. Current mode used is :
+ JESD 204b. Subclass1. Mode1, Dual channel.
+ Sysref 1MHz continuous pulse,50% duty cycle
+ DAC freq : 9216 MHz
+ Channel_NCO freq : 1152 MHz
+ Board : AD917x-FMC-EBZ
+ Sysref :On, AC mode
As in data sheet, NCO can reset by sysref signal by setting bit 2 in register 0x131 for channel NCO and 0x113 for main NCO. But no thing happened. Is any setting need for auto reset NCO with sysref signal????
Hello everybody.
With all the answers i recieved from my other topics i was able to create my second DSP with the ADAU1701 chip. This one is by far better than the first one i build! Many thanks for it!
The thing is i need more GPIO I/O connections for my application. I would like to ask if Analog has a chip like the ADAU1701 only with GPIO connections but without all the audio parts (Audio core, AD/DA etc.) that i also can program with Sigmastudio? I like this program and the way to program devices with this.
Thank you very much!
Hello,
I'm trying to generate a profile using the AD9371 Filter Wizard v1.10 with an RX sample rate of 126 MHz, ORX and TX sample rates of 252 MHz, and a device clock of 126 MHz using a modified VCXO frequency of 100 MHz and RefClk at 10 MHz.
According to this link AD9371 Evaluation Board VCXO selection I should be able to generate this profile with values:
M1: 3
N2: 38
R1: 3
chDIV: 10
This gives a VCO of 3800 MHz (within the limits of 3450 to 4025 MHz) and a device clock of 126 MHz.
This all works fine. However, if I then select "Write AD9528 Settings To File", set VCXO at 100 MHz and RefClkA at 10 MHz, I can no longer select a device clock of 126 MHz! My nearest options are 120 MHz or 140 MHz.
In the MATLAB source files, the function AD9528_Rates() does not look to include an option for the 5-bit divider R1. This looks to limit the value of N2 unnecessarily. Similarly, this functions limits the output channel divider to the range of 3-50, even though the above link states the allowable range is in the range of 1-256.
Is there something I'm missing here?
Hello all,
I have connected the ADT7516 sensor's eval board to my PC through the usb port. Also, I've
installed the software for it. But it seems that the drivers for the software are missing.
When I try to run the software with the hardware connected, it gives me the following error.
I don't see any .inf to install drivers from the CD provided with the hardware.
Can anyone help me with this for the software to work?
Thanks