Hi !

Our customer have some trouble at their ADV7282AM system.

They are not using ADI EVAL board. They are using their own PCB board.

But the script is 100% same as ADI recommend script.

We are trying to connect customers video source to ADI EVAL board next week.

They will use ADV7282AM for automotive rear camera interface.

Their problem is this.

*************************************************************************************************************

①Immediately after register setting, seemingly normal color bars are displayed.
　However, since analog noise occurs sporadically, it seems that some problems already exist.

②When ADV7282A-M lock to CVBS-Diff, the status bit is this.

　0x10 => 0x05

　0x11 => 0x43

　0x12 => 0x00

　0x13 => 0x69

③After a while, the image display is disturbed. (It may be several seconds, sometimes a couple of minutes later)

　When checking the status register when the video display was disturbed, the lock was lost.

④When several minutes elapsed again, there was a case where it returned to a normal image.

⑤When resetting the IC and setting the register again, a normal color bar is displayed and return to ① as I wrote above.

We already checked that ADV7282AM AIN pin clamp looks there is no problem.

We checked CLK jitter but there was no problem.

*************************************************************************************************************

We will confirm the input signal in more detail.(ex. sync, sub carrier...)

They are using fast switch mode and the disable fast switch after system start but nothing changed.

We asked to my customer to change VID_STD to NTSC-M buy the problem didn't disappear.

They are connecting 

DVD player => ADA4433-1(change single to differential) => ADV7282AM => SoC > Monitor

ADA4433-1 circuit is this.

(ADA4433-1) To connect ADA4433-1 to ADI Video decodor 

Also they changed 150Ohm register to 75Ohm.

(Video decoder)When inputting full differential, is the network resistance really 150 ohm? 

We already know that ADV7282AM status bit is something wrong and when they use free run mode there is no problem so we think it is not SoC or Monitor problem.

Do you have any idea what is the reason for this problem?

Do you have any advice for this?

Are there similar experiences?

Best regards

Kawa

Why ADF7020-1  generate interrupt even respective Master is off?

What is the possible cases for generation of interrupt by ADF7020-1?

Is it check for valid interrupt or not before generation of interrupt?

We like to use SOM2 in our end application with our customised carrier card packed in the EMI/EMC complied enclosure(enclosure meeting our EMI/EMC qualification requirements) 

When i pack in proper enclosure,

1) if i use two transmitter, whether with appropriate tuning of the filters  on the TX path, i can use in an end application requiring dual TXR, by PCB design is it supported

2)If i use one TXR and one RXR(active simultaneously), whether by the PCB design, it is supported

3)If i use two RXR(active simultaneously), whether by the PCB design, it is supported

4)Whether i have to use either as one RXR or one TXR only

Please clarify.

Thank you

Hey,

we have developed a board with reference to the FMCOMMS5-EZB and the ZC702. We had to modify the XDC file of AD reference design and route the signals do different pins. We did that straight for other signals and then modified the system_top as well. When running the synthesis and implementation we receive the following error:

[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
    < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets i_system_wrapper/system_i/axi_ad9361_0/inst/i_dev_if/i_clk/clk_ibuf_s] >

    i_system_wrapper/system_i/axi_ad9361_0/inst/i_dev_if/i_clk/i_rx_clk_ibuf (IBUFGDS.O) is locked to IOB_X1Y64
     and i_system_wrapper/system_i/axi_ad9361_0/inst/i_dev_if/i_clk/i_clk_gbuf (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31

Honestly, this is something i don't know how to handle. Adding the set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets i_system_wrapper/system_i/axi_ad9361_0/inst/i_dev_if/i_clk/clk_ibuf_s] into the xdc file results into an successfully implementation, but with errors in timing. These errors are in the rx_0_clk to clk_fpga_0 and rx_0_clk torx_1_clk and i'm quite sure that this will be an issue in the end (I did not tested it so far). Does anyone could support us with the error above?

Thanks and kindy regards

Jan

P.S.: See attached the related XDC file and system_top.v

In a mixed-voltage application for the ADA4899, should the exposed paddle be connected to actual GND or to the negative supply voltage?

I am working with an AD9959 evaluation board, that I recently bought, in  PC mode. I am having problems getting the software that comes with the AD9959 to recognize an input refclk source. I am using a waveform generator set to 10Mhz 1V peak to peak, and have connected this to J9 on my board. The software gives me back an error saying: "The evaluation board does not seem to have a refclk! ... Please check your connections." All of the required power supply connections to the board, including CLK_VDD

All of the connection are according to the manual i.e.,  W7 to PC. Placed a jumper on W1,

W2, W3, W9, and W10

What connections/pieces am I missing?

Hi, I am using the ad9914 evaluation board. Now, the signal of 950MHz ~ 1450MHz is generated by LFM. no dwell high only high. By the way, I want to connect to the OSK pin with the output of the DROVER pin to make a pulse shape, but no output is produced from the drover pin on the right of the evaluation board. Even if I use No dwell, it does not work and does not work even if I do not use it. I also want to use frequency jump, but this also does not work. Naturally, the enable freq jump pin (CFR2 [14]) and the enable freq jump pin (CFR2 [13]) are set high. I tried to control it directly with the MCU and tried the evaluation board software below but it does not work.

 In our application we are reinitializing ADF7020-1 configurations for every 10 sec.

In our observation even respective master is OFF , Interrupt is generated by adf7020-1 for every 10sec.

If Master is ON then interrupt is generated by ADF7020-1 in less than 10 sec.what is the reason behind this observation?

Dear ladies and gentleman,

I would like to implement an automatic source selection for the ADAU1702 and ADAU1452 DSP chipsets.

The basic idea, is to detect the presence of an audio signal on one of the inputs and than process this audio signal through the rest of the schematic towards the audio outputs. The ideal case would be a solution where the priority of the audio streams can be controlled. A possible use case is to process an audio stream from FM radio and then switch over to a  Bluetooth audio stream automatically as soon as music is played with this BT link. Since this is my first implementation with the Sigma Studio I have not fully grasped all of the possibilities of the software. My first try was to use a threshold detection and than combine it with a mute button. But the mute button can only be checked in the Sigma Studio? Isn't it possible to check the mute button by any other function? If this is the case I see a strong limitation of the use cases for this button, because this would postulate that the DSP is only used in combination with a live debugging session.

Hello:

      We are using AD9467-FMC with Xilinx Kintex-7 evaluation kit KC705. The example design describes the procedure for capturing some ADC samples and looking at them with Xilinx Chipscope tool. But we can only see a limited number of samples in this way. We want to fill up the whole memory of KC705 (DDR3) and dump it out using UART or some other means. Can you please suggest an easy way to do this?

Thank you so much.

Best regards,

Hi, I'm using an AD5933 with ATxmega128A1U through an I2C interface with MCLK=1MHz. Everything seems to be working fine and I have been able to write data onto the slave successfully. The problem is, however, that I still can't read data from it. On the output of the oscilloscope, I expect a 0x90 value with NACK, but I keep getting 0x00 with NACK. I would really appreciate any help with this issue.

P.S.: I have attached my C code, along with screenshots of the output of the oscilloscope and also the schematics of the circuit I'm using.

S.M

Dear engineers and researchers,

I have an FMCOMMS5 board on a carrier platform of xilinx zynq zc706 and I'm able to control the FMCOMMS5 board using no-OS API approach. I also know that using linux device driver and MATLAB block diagram I can control the board. 

My question is can I control the various operations of the FMCOMMS5 board just by writing customized verilog codes? If so, how can I do that? 

Thanks,

Tanmoy Das 

Hi 

I have fmcomms5+ZC706 I want to transmit and capture data continuusly on matlab but I cant transmit conti. on simulink  system object. Is there a way to fix simulink or another way for transmit and capture data cont

Thank you

Hi,

So i have been trying to to establish SPI communication between AD7193 and Raspberry pi 3. I'm using the Yocto-rpi image for this purpose. This is procedure i followed but facing some issues:-

1. Enabled the ad7193 driver in menuconfig.

2. Added the patch file in the drivers/staging/iio/adc/ad7192.c for it to support device tree.

3.Created an overlay. dts file for this is /boot/dts/ as follows

/dts-v1/;
/plugin/;

/ {
        compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";

        fragment@0 {
                target = <&spi0>;
                __overlay__ {
                        status = "okay";
                };
        };

        fragment@1 {
                target = <&spidev0>;
                __overlay__ {
                        status = "disabled";
                };
        };

        fragment@2 {
                target = <&spidev1>;
                __overlay__ {
                        status = "disabled";
                };
        };

        fragment@3 {
                target = <&gpio>;
                __overlay__ {
                        ad7193_pins: ad7193_pins {
                                brcm,pins = <45>;
                                brcm,function = <0>;
                                brcm,pull = <0>;
                        };
                };
        };

        fragment@4 {
                target = <&spi0>;
                __overlay__ {
                        /* needed to avoid dtc warning */
                        #address-cells = <1>;
                        #size-cells = <0>;

                        adc: ad7192@0{
                                compatible = "adi,ad7192";
                                reg = <0>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&ad7193_pins>;

                                spi-max-frequency = <1000000>;
                                spi-cpha;
                                spi-cpol;
                                irq-gpio = <&gpio 45 0x2>; /* IRQF_TRIGGER_FALLING */
                                interrupts = <45 0>; /* high-to-low edge triggered */
                                interrupt-parent = <&gpio>;
                                adi,reference-voltage-mv = <3300>;
                                adi,clock-source-select = <2>;
                                adi,refin2-enable;
                                adi,unipolar-enable;
                                status = "okay";
                        };
                };
        };
};

4. Added this overlay.dts file to bb.append file and rebuild the kernel and enable the overlay file in /boot/config.txt in the target.

5. The driver is loaded but i keep getting setup failed and spi0.0 supply vcc not found, using dummy regulator
ad7192 spi0.0: setup failed

ad7192: probe of spi0.0 failed with error -5

I'm attaching the image below please let me know what i'm doing wrong.

Note:- I have connected AGND,CS,SCLK,Din,Dout/Rdy to the respective pins in raspberry pi 3.

Thanks in advance.

-SK

I generate 8bit,10bit,12bit width for RGB, and use ADV7612 to analyse these datas.

when I choose Color Control function, the data analysed by 7612 is not equal to the data which I generated,

however, when I not choose Color Control, the data analysed by 7612 is equal to the data which I generated.

For more information, please look at the picture

So I want to know :

1. Is it a normal phenomenon?

2.How can I get the right data when I choose Color Control function?

We are using  ADAU1966A  in system design with direct master clock mode by following clock sequences. 

   MCLK : 16 MHz

   DBCLK: 1 MHz

   DLRCLK: 31.25KHz 

   sampling rate FS : 31.25 KHz

   I2S Left Right justified

We need help with programming the registers, for the above mentioned configuration. 

What we have currently tried, 

PLL_CLK_CTRL1 reg 0 (0x00)       - 0x01

PLL_CLK_CTRL1 reg 1 (0x01)       - 0x2B

PDN_THRMSENS_CTRL_1(0x02) - 0x82

PDN_CTRL2  (0x03)                        - 0x00

PDN_CTRL3  (0x04)                        - 0x00

DAC_CTRL0 (0x06)                         - 0x00

DAC_CTRL1 (0x07)                         - 0x00

DAC_CTRL2 (0x08)                         - 0x06

With the above register sequence, we can read the temperature from 0x05 register correctly, but we not getting any audio output at the DAC.

Questions:

1) Is the above register values are correct ?

2) Is there any sequence to be followed to be followed while programming the registers

Thanks in advance

Hi all,

When the PLL is bypassed, how to retime the SYSCLK and SYNC_CLK ?

Is it only a way to do it, do the MASTER_RESET ?

Best regards,

sss

I can't find any mention in the data sheet for the a specification on the minimum supply current for the ADAU1961 CODEC under shutdown conditions. I can shut down the 8 MHz clock (externally) and all internal functions but am looking for a shutdown supply current in the order of a few tens of microamps. If the ADAU1961 cant be shutdown to this extent can you advise a CODEC or ADC/DAC combination which would provide a shutdown capability (24 bit Sigma delta with 48 kHz sampling)

Hi

I was advised on High-Speed DACs and I will set up a new thread here.

https://ez.analog.com/thread/106273-output-sawtooth-wave-to-ad9144

This is a question about the operation of the AD9144(or ADI FMCDAQ2).
My customers are evaluating the AD9144.
My customer is trying to output sawtooth waves from AD9144.
T = 200 nS, + 100 count → -100 count
The customer inputs the code and evaluates the output waveform.
Strangely, the output slope bounces small around 0 count.
Customers suspect this as miscounts.

The FPGA side consists of Xilinx ZC706 and the DAC side is made by ADI FMCDAQ2.

How should I check to isolate it from mistakes in circuit design?

Hello Team,

     We were working with ADRV9371-W/PCBZ and zc706 EVK.

     But now we have received our custom board and now we are working on our custom board. AD9371 driver is failing with following error.

// the above picture text

ad9371 spi32766.1: ad9371_probe : AD9371 Rev 4, Firmware 184.72.95 API version: 1.5.1.3565 successfully initialized
cf_axi_dds 44a04000.axi-ad9371-tx-hpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.00.b) at 0x44A04000 mapped to 0xf09d8000, probed DDS AD9371
cf_axi_adc 44a00000.axi-ad9371-rx-hpc: ADI AIM (10.00.b) at 0x44A00000 mapped to 0xf09e0000, probed ADC AD9371 as MASTER
hctosys: unable to open rtc device (rtc0)
ALSA device list:
No soundcards found.
axi-jesd204-rx 44aa0000.axi-jesd204-rx: Lane 0 desynced, restarting link
axi-jesd204-rx 44aa0000.axi-jesd204-rx: Lane 1 desynced, restarting link
axi-jesd204-rx 44ab0000.axi-jesd204-rx: Lane 0 desynced, restarting link
axi-jesd204-rx 44ab0000.axi-jesd204-rx: Lane 1 desynced, restarting link
EXT4-fs (mmcblk0p2): recovery complete
EXT4-fs (mmcblk0p2): mounted filesystem with ordered data mode. Opts: (null)
VFS: Mounted root (ext4 filesystem) on device 179:2.
devtmpfs: mounted
Freeing unused kernel memory: 264K (c07fe000 - c0840000)
This architecture does not have kernel memory protection.
init: hwclock main process (847) terminated with status 1
systemd-udevd[941]: starting version 204
init: udev-fallback-graphics main process (1319) terminated with status 1
macb e000b000.ethernet eth0: link up (100/Full)
init: samba-ad-dc main process (1495) terminated with status 1
init: failsafe main process (1442) killed by TERM signal
init: alsa-restore main process (1653) terminated with status 19
init: tty1 main process (1762) killed by TERM signal
init: lightdm main process (1609) terminated with status 1
ad9371 spi32766.1: ad9371_spi_read: REG: 0x0 VAL: 0x3C (0)
ad9371 spi32766.1: ad9371_spi_read: REG: 0x0 VAL: 0x3C (0)
ad9371 spi32766.1: ad9371_set_radio_state: failed: Device not in radioOff/IDLE state. Error in MYKONOS_enableTrackingCals()

ERROR: 258: Device not in radioOff/IDLE state. Error in MYKONOS_enableTrackingCals()
ERROR: 258: Device not in radioOff/IDLE state. Error in MYKONOS_enableTrackingCals()
ERROR: 258: Device not in radioOff/IDLE state. Error in MYKONOS_enableTrackingCals()
ERROR: 40: Invalid ObsRx channel in setObsRxManualGain().
ERROR: 258: Device not in radioOff/IDLE state. Error in MYKONOS_enableTrackingCals()
ERROR: 258: Device not in radioOff/IDLE state. Error in MYKONOS_enableTrackingCals()
ERROR: 258: Device not in radioOff/IDLE state. Error in MYKONOS_enableTrackingCals()
ad9371 spi32766.1: ad9371_spi_read: REG: 0x0 VAL: 0x3C (0)
ad9371 spi32766.1: ad9371_spi_read: REG: 0x0 VAL: 0x3C (0)

we also use the zc706 EVK ,and same linux kernel uImage，same boot.bin,  but devicetree.dtb. bucause our custom board chip ad9528 output use different pin ,and everything else is the same. We've made corresponding changes on the devicetree.

ADI IIO Oscilloscope can not set RX_LO_Frequency TX_LO_Frequency

We can't find the cause of the problem now，and  we guess that is firmware problem ,Is it?

Am I missing something? Please help me out.

Thanks and Regards,

luo xiaofeng