Quantcast
Channel: EngineerZone : Discussion List - All Communities
Viewing all 51060 articles
Browse latest View live
↧

ERROR: Timing Constraints NOT met! FIR filters integration with the FMCOMMS2 HDL design

June 5, 2018, 9:02 pm
$
0
0
Hello, I am currently working with FIR filters IP core integration according Integrate FIR filters into the FMCOMMS2 HDL design [Analog Devices Wiki], available from hdl/projects/fmcomms2_fir_filters/zc706/ [GitHub], and I am currently having some issues about Timing Constraints NOT met.  I am not sure if it is something I am doing wrong in my case and any help would be greatly appreciated!
I am using Win 10, Vivado 2016.4, Cygwin64 and downloading the repo as a zip. The project is written for platform  ZC706 + AD-FMCOMMS2, and I can compile it without any error.
As that's the hardware I have, I am trying to build it for ZED + AD-FMCOMMS2. I modified all the zc706 parameters in scripts (include Makfile, tcl) to zed, and also manually compiled axi_i2s_adi and util_i2c_mixer IP cores in the library sub fold. But when I run make, I got the following error messages in log file.
$ tail fmcomms2_zed_fir_filters_vivado.log
open_run: Time (s): cpu = 00:00:58 ; elapsed = 00:00:59 . Memory (MB): peak = 2209.121 ; gain = 356.113
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
report_timing_summary: Time (s): cpu = 00:01:06 ; elapsed = 00:00:36 . Memory (MB): peak = 2387.449 ; gain = 178.328
ERROR: Timing Constraints NOT met!
    while executing
"adi_project_run fmcomms2_zed_fir_filters_zed"
    (file "system_project.tcl" line 17)
INFO: [Common 17-206] Exiting Vivado at Tue Jun 05 14:48:26 2018...
Is there any need for additional modification?
↧
Search

How to config clock

June 2, 2018, 3:34 am
$
0
0

Hi,

  I want to receive 8ch serial data  from  other dsp  in TDM8 mode  , and use adsp-21489 transmitter  it to dac in I2S.  

 

how to config  the clock? 

 

  Master DSP : MCK=12.288MHz 

                        BCK=12.288MHz (TDM8)

                        LRCK=48KHz

DCA   :  MCK=12.288MHz

             BCK=3.072MHz

             LRCK=48KHz

 

↧
↧

Getting start with AD9361

May 24, 2018, 4:29 am
$
0
0

We bought KC705 Xilinx Evaluation board with AD-FMCOMMS3-EBZ RF front end to develop Radar applications. Till now we used NI Hardware and developed own software and made systems but we aimed to custom board development. So as first step we bought above 2 boards to study and research to get start. We have expertise in VHDL and vivado platforms. In our office I am the first to explore on these boards. So please help me in configuring this device as soon as possible.

 

Answer me below queries:

 

1) Can I program this Transceiver in windows? I saw some linux packages in website. Is linux OS is mandatory to configure Transceiver module? If yes that would be difficult problem for us as we don't want to install linux. Is there any alternative solution to solve this?

2) How to start with KC705+AD-FMCOMMS3-EBZ configuration to build a basic Transceiver application.

3) I installed vivado node locked license in our server system to develop applications. How to program AD-FMCOMMS3-EBZ board from vivado?

 

 

I know these are very basic level questions that i have asked but please be patience in replying above and feel free to ask if you want any information.

↧

LTC4368 weak gate drive

May 27, 2018, 7:25 pm
$
0
0

I have implemented the LTC4368 with the following configuration:

VIN(MIN) = 40V

VIN(MAX) = 52V

OCP = 5A

 

Nominal input voltage is 48V. This is part of a larger system, however all that is currently populated on the PCBA is what is shown in the attached schematic.

UVLO/OVP works as intended. However the gate drive voltage in the valid band is extremely weak; only around 2.4V. When Q13 (N-FET pair) is unfitted, GATE drives to about 12V in the valid band, which agrees with the 10-13.1V range indicated in the datasheet for 12V - 60V VIN. Removing C71 has no apparent effect on drive strength.

 

Interestingly, when this circuit is run in LTspice as drawn, the UVLO threshold doesn't comply. In fact, the FETs don't turn on anywhere across an applied 0-55V ramp input. I don't understand how, as the UV pin threshold exceeds 0.5V at ~40V in. However, when R85 and R87 are swapped, the FETs turn on (albeit at a slightly lower 37V than the programmed 40V) and correctly turn off at the OVP threshold of 52V. Even more intriguingly, implementing the typical application circuit on the cover of the datasheet in LTspice also doesn't work. I don't know which to believe at this point. On one hand, the gate drive potentials are as expected in the model (when the FETs are operating); on the other, the real world circuit behaves correctly with UV/OV thresholds but has a weak gate drive. The FETs used in the model (FDS5690) aren't the same as what's used on the actual design (SQJ974EP), but their max input capacitances and gate charges are very similar (1107pF/1050pF, 32nC/30nC) so I doubt this is the cause of the discrepancy. I do find it a little concerning that the model doesn't seem to work correctly.

 

Furthermore, it seems to have killed a few MOSFETs already, with their gate source resistances ranging from 500R-200k after being used in the circuit. I have already replaced the 4368 with another in case the first was a dud only to have the same operating behaviour on the replacement.There must be something simple that's wrong here, but it's about as close to the typical app note as you can get as far as I can see. Has anyone used this part with success?

↧

AD9215

June 7, 2018, 9:37 pm
$
0
0

Hi

 

I have a question AD9215.

 

Although it has a single-ended configuration as shown in the datasheet, in order to reduce the current consumption, if the resistance to create the bias potential from AVDD is set to about 10 kΩ, it can not be assumed potential

So, please tell us the value of bias current of VIN +, VIN- terminal.

 

 

Best Regards
HOD

 

 

↧
↧

What is the voltage range of the AuxDAC?

June 7, 2018, 1:36 pm
$
0
0

The equation is:                     (  )=0.97×        +(0.000738+9×10−6×(        ×1.6−2))×                     [9:0]×                     − 0.3572×                     +0.05.   Can zero volts ever be obtained?  Thanks RJ

↧

why more cycles will be taken if "apt_sc584.c" file is changed ARM cortex A5 on ADSPSC589?

May 28, 2018, 10:14 pm
$
0
0

Added segments/sections on L3 memory on adsp-sc58x-common.ld file,and also mapped at L3 memory address region.

and segments/sections are mapped at { 0x89000000u, 0x8FFFFFFFu, ADI_MMU_WB_CACHED}, region.

 

we declared predac buffer size(256*12*4) address region declared on apt-sc584.c file.Like

{ 0x80600000u, 0x80609FFFu, ADI_MMU_RO_CACHED}   /*Predac buffer size*/

 

we are verified a.map file these segments and predac buffer address regions are mapped at L3 part only.

But we added any copying or any function routine in core0 it will take huge cycles compared to core1 & core2.

 

Let me know the any changes are required on macro, we need to create/defined newly.

Please clarify why it will take huge cycles if "apt-sc584.c" file is modified or any further handling required to maintain same cycle in both cases.

 

↧

Hi I am working on a design which has LT6106 current sense amplifier where the VCC is 5V and IN and IN- is 12V. Device is working now and I want to understand if the internal ESD structure of the IC are specialised enough for this application as when In

June 7, 2018, 12:03 am
$
0
0

Hi I am working on a design which has  LT6106 current sense amplifier where the VCC is 5V and IN+ and IN- is 12V. Device is working now and I want to understand if the internal ESD structure of the IC are specialised enough for this application as when Input voltage is higher than the supply voltage.  If not can i have a drop in replacement of that IC which are having such capability as i cant change the design now. opamp

↧
Search

AD9364 Tuning RX Failed for high freq.

May 28, 2018, 3:06 am
$
0
0

Hi,

 

We have custom board for ad9364 chip. Our HDL reference is hdl_2017_1. (kc705)

We got received Tuning RX Failed! for more than 45 Mhz frequency.

 

In ad9361_dig_tune_delay() function, we have changed rates as below.

//rates[3] =  {25000000U, 40000000U, 61440000U} 

rates[3] = {25000000U, 30000000U, 40000000U}

 

With these rates, we don't have any error. ad9364 initialize successfully.

 

My question is that is this problem related to our HW?

Do you have any suggestion to me to check some parameters in sw?

 

Thanks,

Yasin 

↧
↧

AD7986 - Data Reading

May 31, 2018, 10:00 am
$
0
0

Hi,

 

I have interface AD7986 with FPGA. With Internal reference and Turbo mode, I am reading data in CS MODE, 4-WIRE WITHOUT BUSY INDICATOR.

 

Clock – 25MHz

Conversion time used is 600ns

Data reading during acquisition.

  

Below are digital output code got for respective voltage

 

4 volt     - 0x1F90E

3 volt     - 0x178A9

2 volt     - 0xE94A

1.5 volt - 0x7145

1 volt     - 0x0148

0.5 volt - 0x3EF15

 

What may be the reason for this observed voltage drop.

 

Please find attached schematics.

 

Thanks and Regards,

Dileep

↧

TMP37 FIT Rate

June 7, 2018, 10:54 pm
$
0
0

Hi All,

 

What are FIT Rates (60% and 90%) of the TMP37?  Same as those of TMP36?

 

Regards,

Kazu

↧

ADAU1962 Popping noise after Power-ON

May 22, 2018, 12:37 am
$
0
0

Dear Team,

Initially popping noise is observed at ADAU1962 DAC output after enabling Master Power-Up bit of  PLL_CLK_CTRL0

register. Please find the attachment for ADAU1962 configuration code.

Could you please share the your feedback on this issue.

 

Hardware: ADSP-SC589 EZKit

Tools: CCES 2.7.0

↧

Layout of AD1674

June 5, 2018, 1:25 am
$
0
0

Hi, 

 

we develop a board with AD1674. 

 

we are performing a PCB layout of our board, we need layout information. 

(We referenced the datasheet, but it lacks information.)

 

In addition, refer to the 12 page ground section of the AD1674 data sheet, it is referred to as ' Then connect AGND and DGND together at the AD1674'.

 

Does the sentence mean that AGND and DGND pins of AD1674 should be connect?

 

I will wait for your reply.

 

Thank you.

↧
↧

ADF5355 linux driver : is /dev/iio:deviceX useful?

June 7, 2018, 5:50 pm
$
0
0

Hi all,

 

I can see /dev/iio:device0 and /sys/bus/iio/devices/iio:device0 when I use the ADF5355 driver.

 

As documented, /sys/bus/iio/devices/iio:device0  provides two channels for outputs a & b for changing frequency, power up and down the two channels.

 

Is /dev/iio:device0 useful? does it provide any useful interface? Is there any documentation on that? 

 

Cheers

↧

Port selection in FMCOMMS5(ad9361) using no-OS api !

June 7, 2018, 3:35 am
$
0
0

Hello,

Physically if we consider the no of RF ports on an FMCOmMS5 board is 12(Total 8 RX SMA & 4 TX connectors). I'm using FMCOMMS5-ZC706 platform, bare metal application with no-os api.

My question is whether is it possible to select one of these 12 RF SMA port using any API? If so, can I turn off (or on) that selected RF SMA port again using any api? If API are not available, is there other  any way, so that I can do my job?

Thanks,

Tanmoy

↧
Search

Is ADSP-218xN family code compatible with ADSP-2115 obsoltete part?

June 5, 2018, 5:47 am
$
0
0

I need to replace obsolete ADSP-2115 family with a new one hopefully code compatible.

Is the ADSP-218xN family a good choice?

↧

ADALM-PLUTO serial connection

June 7, 2018, 8:06 am
$
0
0

My aim is to talk to ADALM-PLUTO via a Micro Controller using the standard Serial commands.

I have tested all the commands first by using Putty and then a vb.net and everything works fine.

The small amount of data I need is fine at 9600 baud.

The next stage is confusing me. My microcontroller will send Serial TTL.

I have made a test cable and with 2 USB to serial adapters, then 2 terminals working on the windows laptop.

Thats is fine.

When I connect one end of the cable to ADALM-PLUTO via a OTG cable, nothing happens.

Is there a command to tell the firmware to talk via OTG instead of the supplied USB cable?

Do I need to install drivers for the USB to Serial Adapters to work on ADALM-PLUTO. 

I'm new to Linux and ADALM-PLUTO, so any help would be appreciated

↧
↧

ADR01BRZ output voltage -30C

June 4, 2018, 11:47 pm
$
0
0

Hi. 

Customer's device didn't work well at low temperatures ( -30 C ) and  they found  that problem were with ADR01BRZ.

Tested stand along IC at -30C temperature loaded on 1.1k resistor  (9.1 mA) with input voltage 15 V, output was 9.990 to 9.991 V.

initial accuracy is 9.995 -10.005 V, temperature drift 3ppm/C, delta 55C will cause  -1.65 mV drift.

Worst case must be 9.995-0.00165 = 9.993 V.

Any idea ? what else could affect ? 

↧

Pass element LT1764A and LT1963A

June 8, 2018, 12:06 am
$
0
0

Hello,

I would like to know what is the pass-element (NMOS, PMOS, PNP or NPN) of the LT1764A and LT1963A. Is anybody can help me?

 

Thanks

↧

AD7193 Accuracy Issues...

May 25, 2018, 10:20 pm
$
0
0

   Hello,

AD7193 calibration issue is solved & now i am getting values of offset register & Full scale register as follows.

 

      Offset register=8389236

      Full scale register=5584950

  AD7193 Configured as follows:

Mode register=0x0C0060

Configuration register=0x040118

Gain=1, Vref1=2.5, Chop disable, FS[9:0]=96,Continuous conversion mode,unipolar configuration

0 to 2.5V dc input connected to ch1 to check linearity of  ADC.

But i am getting 3.5% error (of the reading) near 0.1V

Zero: 0v , ADC counts=0

Span: 2.5V, ADC counts = 16754713

i/p                   ADC counts          Calculated Counts        Error(%)

0.10001          644500                     670228                     3.8387

0.20001         1315798                   1340390                    1.8346

0.30001         1987091                    2010551                   1.1668

0.4001            2660577                   2681316                   0.7734 

0.5001            3331311                   3351478                   0.6017

0.6001            4002490                   4021639                   0.4761

.......

.......

2.0001            13398607                  13403902                0.0394

2.2001            14741788                  14744225                0.0165

2.4001            16083274                  16084548                0.0079

2.5001            16754713                  16754713                

 

 

Please help me how to minimize Error..

Expected error for my application should be <.25% of the reading near zero.

 

Any help will greatly appreciated...

↧
Viewing all 51060 articles
Browse latest View live
Search
<script src="https://jsc.adskeeper.com/r/s/rssing.com.1596347.js" async> </script>