At initialization I am getting the following on the UART:

   Please wait...

   AD9528_initialize() failed

I have checked the register address values of AD9528 :

1) 0x010A = value is 0x00 

 I am writing the value 0x2 but when i read back the value its value turn out to be 0x00.

2) 0x0508( Readback 0 )  = value is 0x21

which means my PLL1 is locked but PLL2 is not locked

I have also checked the clock which is generated by AD9528 "  FPGA_REF_CLK+ and DEV_CLK_IN+ " but no clock is generated at output.

Was there anything else that needed to be modified in the code to initialize it ?

OK, thank you for reply. May I continue to ask you questions in that forum topic?

My next problems are:

1) How should I do copy source files to my NIOS project? Do I need to save dirrectory structure:

ad9528\
mykonos\
platform_altera\
platform_xilinx\                   //is it realy needed for Altera???
common.c
common.h
headless.c
myk.c
myk.h
myk_ad9528init.c
Mykonos_M3.h
?

When I do this, project doesn't build. Eclipse can not find include (*.h) files in subdirrectories. I tried to  set up include path in Project -> C/C++ General -> Path and Symbols but it doesn't help the situation. My be it is because my poor knowledge of Eclipse and I should configure environment somehow. Anyway, I work it out by coping all *.h and *.c files in one dirrectory.

2) After that I got this build error:
'DAC_GPIO_PLDDR_BYPASS' undeclared here (not in a function)    headless.c    /software/src    line 122    C/C++ Problem

I've found that DAC_GPIO_PLDDR_BYPASS only defines in the platform_drivers.h file in  platform_xilinx dirrectory, which I didn't copy to my project, because of coinciding names. OK, I transfer definitons:
#define GPIO_OFFSET            54
#define DAC_GPIO_PLDDR_BYPASS    GPIO_OFFSET + 60
to altera  platform_drivers.h and this error goes away.

3) After that I got this error:
Description    Resource    Path    Location    Type  make: *** [software.elf] Error 1    software             C/C++ Problem

And I stuck with it.

Eclipse console output is:

...\hdl\projects\adrv9371x\a10gx\software\AD9371/HAL/src/alt_instruction_exception_entry.c:95: warning: Unable to reach (null) (at 0x00087da0) from the global pointer (at 0x00074a2c) because the offset (78708) is out of the allowed range, -32678 to 32767.

collect2.exe: error: ld returned 1 exit status
make: *** [software.elf] Error 1

My current configuration is:

Project: hdl\projects\adrv9371x\a10gx\

Altera project brunch: Master

No-OS project brunch: 2016_R2

Quartus Prime: 16.0.0 build 211 standart edition

Eclipse (comes with quartus): Version: Kepler Service Release 2 Build id: 20140224-0627

I just want to go thru all build process and see example project working on my evaluations boards: Arria 10GX GPGA Development Kit and ADRV9371-W.

Thank you for support.

Hi, I am trying to setup a no-OS/bare metal project in the Xilinx SDK for the AD9375. I followed the instructions from AD9371/AD9375 No-OS Setup [Analog Devices Wiki].

The code won't compile because of the following problem:

In _profile_timer_hw.h: xintc.h, xintc_l.h, and xtmrctr_l.h not found

Can you please give a hint what is the problem here? Maybe a problem with the BSP?

I am using the HDL reference design TAG 2017_r1 and the no-OS BRANCH 2017_R1 from the git reps.

Thanks in advance, Jan

I am doing a project on portable 12 lead portable ecg device. We have to use raspberry pi or arduino to implement the application. We are considering ADAS1000 to do so.

I got a AD9739A-FMC-EBZ from digi-key.

when I unpack it，I found it cannot be powered up for the  two un-mounted jumper JP1/2.

It seems like thisI have an AD9739A-FMC-EBZ and jumpers JP1 and JP2 are not installed.  Why is that?  Thank you. 

Then I shorted them,  and the board can be powered with 1.8/3.3V.

I use the AD9739A FMC Eval board with a FPGA KC705 board, jump P2 to FMC and switch S1 to ADF4350. Then it reads:

********************************************************************
  ADI AD9739A-FMC-EBZ Reference Design
  AD9739A PART ID: 0x24
********************************************************************
Error occurred during AD9739A setup.
Possible reason: wrong position of switch S1.

Exit application.

Then I debug and see where throw an exception, I found the MU of AD9739A cannot be locked!!!

At the same time, The ADF4350 locked normally.

And then I change the P1 to USB, plug the USB cable.I found the MCU seems not working. for the XCR1 blind and no any response when I plug the USB cable to computer.

Hi,

Within my fully working Simulink model I have an AD9361 Zynq SDR Receiver block and when I try to build the embedded executable standalone binary with hardware implementation "Xilinx Zynq Based Radio Board Target" in Normal mode I get to these errors:

Has anyone had similar errors with the build process with AD9361 block before? I can't find the code of all these missing functions within my hard drive. Maybe it is called from any library. All needed Xilinx Zynq support packages for building the embedded code are properly installed.

My goal is deployment of the standalone binary on the ARM part of the AD9361 board.

Thank you a lot for any ideas how to overcome these errors.

Regards,

Ethan

We need the AD9162, post every power-on-reset/initialization (POR), to output a waveform with the same deterministic delay with respect to an external trigger that’s phase coherent (fixed phase-relationship) with respect to the DAC’s SYSREF and sample clock; but are unable to do so. Our question therefore is how to accomplish this?

According to: https://www.youtube.com/watch?v=9p03g0Of9qM, slide 20: The JESD204B specification defines Deterministic Latency as the time difference between (Tx frame & Rx de-frame) the frame based data generation at the Tx to when the frame based data on Rx is output measured within the Frame Clock domain. The specification further specifies that the deterministic latency shall be programmable in increments at least as small as the Frame Clock period, and shall be repeatable from power-up cycle to power-up cycle, AND shall be repeatable regardless of link resynchronization events. This video is incomplete, it would be nice to provide a link to its entirety.

According to caption of Table 23 on pg. 54 AD9162 datasheet (Rev. C), SYSREF is sampled with an internal divided by 4 version of the DAC clock. Therefore, unless this divided-by-4 is synchronously reset from POR to POR there are four possible phase states. Hence, under Subclass 1 description on the same page: this mode gives deterministic latency and allows the link to be synced to within four DAC clock periods.  However, step-6 of the Sync Procedure on the same page provides a means to read back the SYSREF_PHASEx register to identify which phase of the divide by 4 was used to sample SYSREF. According to the answer provided by https://ez.analog.com/message/316932-jesd-ynchronization-accuracy-for-ad9144-and-ad9162, doing so would produce a synchronization accuracy in a multi-convertor case within a single DAC clock cycle. We are simply trying to accomplish such accuracy for a single convertor case from POR to POR.

We have an external SYSREF signal that is accurately phase aligned to the DAC clock. The SYSREF and Device Clock signals are also POR deterministic with respect to the core clock/SYSREF fed to the JESD204B transmitter IP of the FPGA. Our settings are: M=1, L=8, F=1, SYNCMODE = Continuous, No SYNC errors were reported, DAC’s internal PLL locked every time without issue.

We also followed procedures on pg. 56 for Link Delay Setup Example, Without Known Delay. However, we see up to 8 PCLK variations from POR to POR relative to the synchronous external trigger. Such variations are >> 4 DAC clock cycles. We have gone through pertinent sections of the DAC datasheet to no avail, and would much prefer an offline real-time person-to-person discussion.

Hi

I am using an ADAU1701 to implement a four channel audio mixer. The first two input channels are routed to the DSP's ADC0 & ADC1, the second two input channels are routed to the DSP's SDATA_IN0 via an external ADC. A fifth internal DSP input channel may be selected from either pink noise or sine tone. The input stage (shown below) depicts the MS Signal Envelope / Readback block used. The mixer & output stages (not shown below) contain more MS Signal Envelope / Readback blocks, for a total of 12.

The DSP is compiled for a 48kHz sample rate with PLL_MODE1 tied high and PLL_MODE0 tied low.

Number of instructions used (out of a possible 1024 ) = 992
Data RAM used (out of a possible 2048 ) = 425
Parameter RAM used (out of a possible 1024 ) = 328

The DSP is hooked up to a STM32 micro vis a SPI bus. On power up or reset, the micro resets the DSP, waits 25ms for the PLL to stabilize, activates SPI slave control (toggles the CS line three times) then writes the program & parameter to the DSP (as per function default_download_DSP() from the code generated by Sigma Studio).

In order to extract audio signal levels from the DSP, the micro performs a read every 100ms of all the DSP readback blocks. Each readback block reads the value from a MS Signal Envelope with TC = Decay = 100dB/s. These read values are then converted to dB and fed to a VU-meter style display.  The final effect is quite satisfactory and working well with the chosen TC and decay values of the MS Signal Envelopes.

However, I have come across two issues, one of which is a showstopper.

After a reset of micro with no audio signal present on any input (i.e. all power supply & audio voltage levels are stable) the micro then resets the DSP, goes through the DSP startup procedure described above and proceeds every 100ms to read all readback blocks.  

Issue #1:

After every reset, some of the MS Signal Envelope / Readback blocks "misbehave", returning a random value that decays to zero over a period of time. This period ranges from ~200ms to ~3 seconds after reset. The remaining blocks return zero (as expected since there is no audio signal present).

Once the affected block's value had decayed to zero, normal operation is seen where the readback value follows any applied input signal. 

It will not always be the same MS Signal Envelope / Readback block that is affected. It appears to be a random infliction with no discernable pattern. No two affected blocks will have the same initial value or decay time. Once the affected blocks have decayed to zero, the "misbehaviour" is not seen again; it only occurs after the DSP reset / startup procedure.

One interesting point to note is that when I remove some of the filters in the DSP and thus reduce the number of instructions (MIPS), this "misbehaviour" is then rarely seen. When seen, the initial value read is much smaller & the decay time very small (< 300ms).

Issue #2 (showstopper):

Occasionally, after reset, one of the MS Signal Envelope / Readback blocks "lock up", permanently returning a value of 0xFFFFFF. The value does not change over time. Only another reset will return the block to normal operation.

Again, it will not always be the same MS Signal Envelope / Readback block that is affected. It appears to be a random infliction with no discernable pattern. This issue is rare, only seen in one out of five resets.

Since the issue does not resolve over time (as with issue #1), this is a major problem with the VU meter display showing full scale when no signal is present.

Hoping that someone can shed some light on what is happening & how I can resolve it.

Regards

Mark

Hi, I have a HMC739LP4 evaluation  board, which I want to use to setup a heterodyne phase locked loop. I wanted to know the fastest speed/frequency or response time, upto which I can tune the input voltage signal ? This is important for me, since I need to know if this VCO is suitable for my application. For e.g. Can I frequency modulate the (input voltage of the) VCO and achieve datasheet performance for a MHz range input voltage signals ? I have a tunable loop-filter that works upto 200 MHz. This information isn't present in the datasheet as far as I understand. Thanks...

What is the performance of AD8369 at 500MHz with 3V supply ?. 

For Specifications like 

Gain

P1 dB

IMD2

IMD3 

Harmonic power

SUPPLY Current.

Hi ,

Please suggest me the below. 

1. Can i use AD8369 at 500 MHz?  What is the performance of AD8369 at 400 MHz &  500 MHz.  like : Voltage Gain
Gain Flatness
Noise Figure
Output IP3
IMD3
HarmonicP1dB
Distortion.. 

2. What is the recommended value of capacitor for High pass filter to have a cut-off at 250MHz. 

how to calculate that capacitor value? What is the filter response. ? 

I'm looking for an affordable solution for learning and evaluate high-speed ADC (100MSPS) but the evaluation board HSC-ADC-EVALEZ is a bit too expensive for me right now, what you recommend me to use instead?

The purpose is to use high speed ADC in a medical application in which the front-end electronics is already developed. The main communication interface right now is a standard micro controller Arm 4 (STM32F401, 80 Mhz) and a 1MSPS ADC, and I want boost the system performance going to a faster ADC and microcontroller/FPGA solution. 

Hello, is it possible to use the LTC3630 (and in general any Linear synchronous buck converter) in the so-called "fly-buck" topology? Just to clarify, this is the way Texas Instruments calls a mix berween the buck and the flyback topologies, ad described in this page:

Multi-Output Fly-Buck™ Topology | Power Management | TI.com 

As far as I can understand, any synchronous buck converter set for a duty cycle less than 50% should be compatible, but I'm not sure if in reality some specific optimizations are required.

Thanks!

L.

Hi all,

I'm not seeing  ADF5355 driver in Raspberry pi kernel (https://github.com/raspberrypi/linux ). I tried versions up to 4.16. 

Under Synthesizers DDS/PLL category, I can see only ADF4350/ADF4350 as shown below : 

Also, ADF5355 IIO Wideband Synthesizer Linux Driver [Analog Devices Wiki]  suggests to set the following options.

 --- Industrial I/O support               -*-   Enable ring buffer support within IIO               -*-     Industrial I/O lock free software ring               -*-   Enable triggered sampling support

but what I get is as follows : There's no option for "Enable ring buffer support" & "Industrial I/O lock free software ring"

I saw this post : Stuck setting up ADF5355  and it says ADF5355 is working with Raspberry Pi3, but the post does not tell the steps taken to install the driver.  I don't know much about kernel/driver installation & I don't know where to put .dts files, where to put source files (.h .c) etc. when adding new drivers. 

Please bare with me, my linux kernel/driver installation knowledge is very limited. 

It would be great if someone could guide me to control ADF5355 with RPi 3 using iio device driver. 

Cheers,

Hi all,

I can see /dev/iio:device0 and /sys/bus/iio/devices/iio:device0 when I use the ADF5355 driver.

As documented, /sys/bus/iio/devices/iio:device0  provides two channels for outputs a & b for changing frequency, power up and down the two channels.

Is /dev/iio:device0 useful? does it provide any useful interface? Is there any documentation on that? 

Cheers

I would like to ask a question and if anybody can answer my question, I would very much appreciate.

I am using Z706 and AD9361. I have setup the SD card image on the server side and I have a client machine which is a Linux machine. I am using ad9361-iiostream file where I send my data using sin and cos function to DAC and try to get the output from DAC. If I send the random number which does not exceed 2047, do the left shift 4 bit and send the data to DAC. It creates a nice waveform file and the waveform can be seen on oscilloscope clearly.  Using random number I can get the output from DAC. However, when I send the sin and cos function, the output from DAC can not be captured or I get just 0 and one single value as output.

I have used iio_channel_read_raw function to capture the output else iio_channel_read function to capture the output from DAC. I want to capture the DAC output and then send the output to ADC and finally I want capture the ADC output to compare the digital data on both side.

Can any export or whoever is familiar with the subject libiio can answer my question. Thanks a lot.

Hi !

I have some questions about ADV7611 EDID.

Our customer are trying to use internal EDID but sometime ADV7611's checksum will fail.

Our customer is writing 0x00 to EDID checksum block.

The correct value is different but we think that ADV7611 will update checksum block automatically.

This is written at hardware users manual.

So our customer write 0x00 on purpose to checksum block and check ADV7611 update the value automatically for fail safe(they want to detect ADV7611 is something wrong or not).

But when they connect some source machine to ADV7611 and monitor the DDC line, the checksum value is not correct.

ADV7611 output checksum value which our customer wrote.

Also they tried to retry the EDID sequence and used the reset pin but after reset they read back EDID_A_ENABLE register ,EDID_A_ENABLE is still "1" . (default is "0").

Also I read many thread for ADV7611 EDID in engineer zone and have many thing to confirm.

Q1)

To enable EDID, hardware user manual said set EDID_A_ENABLE to "1".

This is the only conditions that ADI's document ask to us.

But I found this thread.

How can I use ADV7611 with an internal EDID 

At this thread, I thought that if our customer want to use EDID, they have to set,

・　64 77 00 ; Disable the Internal EDID
・　Write EDID RAM.

・　64 77 00 ; Set the Most Significant Bit of the SPA location to 0

・　64 52 20 ; Set the SPA for port B.

・　64 53 00 ; Set the SPA for port B.

・　64 70 9E ; Set the Least Significant Byte of the SPA location

・　64 74 03 ; Enable the Internal EDID for Ports

these setup.

So my question is this.

To enable EDID and update checksum result ,is

・　64 74 03 ; Enable the Internal EDID for Ports

only the trigger to enable EDID and update checksum?

Or do they have to set all register which I wrote above?

Q2)

Our customer is using ADV7611.

Not ADV7612.

If they have to set all register which I wrote above, I think this is the correct setting.

・　64 77 00 ; Disable the Internal EDID
・　Write EDID RAM.

・　64 77 00 ; Set the Most Significant Bit of the SPA location to 0

・　64 52 20 ; Set the SPA for port BA ( I think this is typo). 

・　64 53 00 ; Set the SPA for port B.

・　64 70 9E ; Set the Least Significant Byte of the SPA location

・　64 74 03 ; Enable the Internal EDID for Ports

・　64 74 01 ; Enable the Internal EDID for Ports

How do you think about this?

Q3)

After they enable EDID using EDID_A_ENABLE and fail to connect HDMI source because of the checksum result, they use reset pin to restart the device.

But after reset, 64 74 is still 01.

After they shutdown the power supply and re-supply the power , register turns to default value.

I thought reset pin will reset this register but I can not check about this at EVAL board because I'm out now.

So my question is this.

Would reset pin resets EDID_A_ENABLE?

Q4)

If reset pin don't reset EDID_A_ENABLE, is it safer to set EDID_A_ENABLE default value before our customer write EDID RAM?

Our customer have to fix their software very soon so please help about this as soon as possible.

Best regards

Kawa

Hi there,

We are evaluating the reverse polarity protection feature of the LTC4364 using the DC2027A-B demo board.  When a reverse input voltage was applied, the reverse input current was 35 mA.  We were expecting a much smaller value.  Why would there be so much leakage current?

Scirroco

My objective is to convert HDMI to RGB with an ADV7611 installed on a custom PCB. This PCB has, among other stuff, a microcontroller that manages the initialization of the devices. When I make work the ADV7611, the configuration will me managed by the microcontroller.

In order to obtain a valid configuration, I use an Aardvark I2C-USB, AVES SW and an EVAL-ADV7612-7511; as well as a Saleae Logic analyzer for data sniffing.

As far as I understood from reading here in the support site, ADV7611 and ADV7612 are configuration-compatible (although some registers are not present on ADV7611). So I assumed that if I am able to obtain a working configuration for ADV7612, exactly the same configuration will be valid for an ADV7611. Is this assumption correct?

What I did in order to get a *valid* configuration for the ADV7611 that is installed on my PCB was more or less as follows:

 - Use the EVAL-ADV7612-7511 EVB to get a working configuration for the ADV7612 and save it as an AVES script

 - Keep the previously obtained configuration script and use it to write configuration to the ADV7611 on my board

 - **In theory** the ADV7611 should work.

The results that I got are basically:

 - At this stage what I consider "correct operation" is the detection of the HDMI received from a PC (I used a custom and working EDID) and having the pixel clock locked

 - ADV7612 is working fine but ADV7611 is not

 - Observations regarding ADV7611:

      I observed that in ADV7612, the address set for the Infoframe reg. map is set to 0x76 (in the register F5 of IO map -0x98-) so I had to change it from 0x76 to 0x7C to avoid the reception of NAK when writing to the Infoframe reg. map

      The control signals in both devices have the following values:

         HDMI_HPD: 0 in the EVB, 1 in my PCB. Probably because of the correct detection of the video source in ADV7612

         ADV_RESET_N: 1 in both cases, reset mode is disabled

         INT1_N: 0 in both cases

         INT2_N: 0 in the EVB, a 40MHz switching signal in my PCB (no signal is being injected here and the INTRQ2 is disabled)

Notes:

  In my board the output lines (RGB data plus video control signals are floating for the moment). Can this have any influence in my system's behavior?

  The Crystal oscillator is exactly the same P/N as the one used in the 7612 evaluation kit, running at 28,6363MHz

Could I get some suggestions, guidance on how to make work my ADV7611?

Is there any support documentation about the configuration porting/compatibility between ADV7611 and ADV7612?

Thanks in advance

Hi all

When one of my customers uses the ADuCM330 in slave mode, it wants to communicate under certain circumstances without requesting the master.

For example, if the battery voltage is below the reference voltage while sensing the battery voltage, she wants to send a critical alarm even if there is no master request.

I think that it will be possible to connect the communication by generating the interruption when the battery voltage is below the reference voltage while sensing the voltage, but please advise about the specific method.

Thank you