Hello,
I'm trying to modify the provided HDL/no-OS reference source code for the AD7616 to support our custom design.
We have 4 AD7616 using a shared serial interface (SPI) configured by hardware signals (no SPI DIN line) and the intended operation it's to capture the data activating the shared CONVST signal and then cycle through all the ADC's getting the data through both SPI DOUT lines at the same time.
Right now, using the AD7616 reference HDL/no-OS (using only 1 CS line) we can successfully read the ADC captured data from the AXI SPI Engine register, although the DMA transfer (ADI AXI DMAC) doesn't work.
I would like some assistance with the following modifications:
1) [SPI-Engine][HDL] Add three more chip select lines to the Vivado AD7616 IP.
2) [SPI-Engine][No-OS] Configuration of the SPI Offload Engine to address the different new CS lines.
3) [ADI AXI DMAC] A working version.
1) Modifications made to the axi_ad7616 block:
*[ADD] parameter NUM_OF_CS = 4
*[MODIFY] output [NUM_OF_CS-1:0] rx_cs_n
*[MODIFY] spi_engine_execution #(.NUM_OF_CS (NUM_OF_CS), ...
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Is there any other HDL modification necessary to the HDL in order to support 4 CS lines?
2) [SPI-Engine][No-OS] SPI Offload Engine
spi_engine_write(SPI_ENGINE_REG_OFFLOAD_CTRL(0), 0x0);
spi_engine_write(SPI_ENGINE_REG_OFFLOAD_RESET(0), 0x1);
spi_engine_write(SPI_ENGINE_REG_OFFLOAD_SDO_MEM(0), 0x00);
spi_engine_write(SPI_ENGINE_REG_OFFLOAD_CMD_MEM(0), 0x2103);
...
How to enable/disable the different new CS lines?
3) [ADI AXI DMAC] Problems
The ADI AXI DMAC no-OS code indefinitely hangs in this loop:
// Wait until the new transfer is queued. Checks for the transfer has been successfully queued.
do {
ad7616_dma_read(core, ADC_DMAC_REG_START_TRANSFER, ®_val);
}
while (reg_val == 1);
Any tips in how to debug or what to check to complete the DMA transfer?
Thank you in advance,
Regards,
Vicente
