Is there a MatLab model or similar for the AD9164 RF DAC?

I would particularly like to model the different options for up-conversion.

Hello,

My customer wants to change the REF clcok of HMC767 and HMC778 from 50MHz to 10MHz.

In the case, the customer has some questions about phase noise spec on datasheet.

    1. At REF 10MHz, unwanted spur signals were observed in SSB Phase Noise specs of datasheets as below

          Could you please provide a design guide to minimize or eliminate the unwanted signal ?

      2. In another SSB Phase Noise specs of datssheets, unwanted spur signals were not observed as below

            What is the difference between the above spec and this spec ?

       3. In addition, could you please provide a design guide for thermal of high frequency PLL devices ?

Thanks a lot.

Hello,

We have found a problem with a PLO which is designed using a solution based on a HMC704LP4E PLL and a HMC531LP5E VCO. The signal reference for locking the PLL is a 100MHz signal from a VCXO which is locked to a 10 MHz external signal through an ADF4002BRUZ PLL.

Initially we have designed a PLO (it will be called PLO_V1), which has been manufactured around 100 units. These PLOs have been working without problem.

After that, it has been designed a new version of the PLO (it will be called PLO_V2) which includes an internal 10 MHz OCXO. The schematic and the PCB design it almost identical between PLO_V1 and PLO_V2, without considering the additional components used in PLO_V2 to include the OCXO. The main difference is that 100 MHz VCXO in PLO_V1 is soldered over the top of the PCB and in PLO_V2 is soldered at bottom of the PCB.

The problem we found with version PLO_V2 is that there is a degradation in the phase noise behaviour, but this degradation is only observed when using as fractional, if the PLL is used as integer the phase noise is the same for both versions.

We have assembled two units of PLO_V2, one with internal 10 MHz OCXO and the other without mounting all the components for the OCXO and using an external 10 MHz reference to lock. In this second assembly, we have the same components as in PLO_V1. The wrong behaviour is the same for both configurations, it is not noticed any difference.

In figure1 and figure2, it can be observed the phase noise of PLO_V1 for a frequency of 14 GHz (integer) and for a frequency of 14.025 GHz (fractional). The registers used in each case are the following:

F=14 GHz à  00000000,01000001,02000001,03000023,04000000,05000005,060307CA,0700004D,0809BEFF,092DBFFF,0A002205,0B078071,0C000008,0F000081

F=14.025 GHz à 00000000,01000002,02000001,03000023,04100000,05006095,06030F4A,0700004D,0809BEFF,092DBFFF,0A002205,0B078071,0C000000,0F000081

These should be the phase noise results we could expect for PLO_V2 using the same registers. However, as it can be observed in figure3 and figure4, for the frequency of 14 GHz the phase noise is the same and for a frequency of 14.025GHz the phase noise is rather worse. The registers are the same that in PLO_V1

We have been doing several tests to find which could be the reason to this problem, and we have found a strange situation in PLO_V2. If we sent the registers 00000000,01000001,02000001,03000023,04100000,05006095,0603074A,0700004D,0809BEFF,092DBFFF,0A002205,0B078071,0C000000,0F000081, the PLO is not locked as it is logical because it has been disable the modulator through signal frac_rstb (bit 11 register 06). After that is sent again the 14.025 GHz registers (00000000,01000002,02000001,03000023,04100000,05006095,06030F4A,0700004D,0809BEFF,092DBFFF,0A002205,0B078071,0C000000,0F000081) the PLO takes about 5 seconds to lock and the phase noise is OK as it can be observed in figure5. Now, if is send again the same registers after about other 5 seconds the phase noise is degraded again as in figure6.

We can understand this behaviour because the registers programmed in the PLL are exactly the same.

We have been doing tests with other register values and we have found one register combination where the PLO is locked to 14.025 GHz and the phase noise is OK as in figure7. The registers used in this case are:

00000000,01000001,02000001,03000023,04100000,05000005,06030F42,0700004D,0809BEFF,092DBFF0,0A002205,0B078071,0C000000,0F000081

With these registers we have two problems, there are some spurious at 6.27MHz very high (figure8) which are not admissible in our application and we have seen that in this configuration we are using the Delta Sigma Modulator Type in a configuration ‘reserved’ as it is indicated in datasheet (bits [3:2] of register 06)

We would appreciate if you could give us any advice, about which could be the problem we have or any recommendation for locking the PLL to a frequency of 14.025 GHz. If you need any additional information please let us know it. Thanks

Hi!

I have AD9681 and Artix7.

Now, I use:

CLK_PIN- IBUFDS-IDELAYE2-ISERDESE2.

DATA_PIN- IBUFDS-ISERDESE2.

DDR two-lane, bytewise.

Delay (for clk) and bitslip operation are doing manual (by VIO)

clk-line (after ISERDESE2 ) alwsys indicates "AA"

fco-line (after ISERDESE2 )  indicates "F0" after bitslip operation.

If ADC if going test (0D register - 04,09) - correct data (after bitslip).

But signal is bad!

I used XAPP524, XAPP585.

I would like to evaluate the ADRV9364 reference design and see how the FPGA interface is handled.  Where do I find the FPGA project files for this design?  I have the schematic and a very brief data sheet.  I need more.  Do I need to buy before I try on this one?

It is possible to implement a gps receiver on the ADRV9364 / PicoZed SDR 1x1? Because i read in the data sheet of the AD9364 reciverchip that it converters the RF signal direct to a baseband signal. And gps signals have all different frequency shifts due to the doppler effect so the center frequency is four every signal different.

thanks alex

Hi,

I am trying to implement HDL ref design of AD9371 provided on your site , by removing the DMA logic.

I am using adi Linux kernel to on ZC706 board , with edited device-tree similar to ref design and having similar parameters.

SPI devices were getting probed (ad9528 successfully , ad9371 unsuccessful), but I could see the prints in dmesg

but for HDL drivers , they were not getting probed. I cross-checked device-tree several times , I don't think that was issue.

In next build I used HDF directly from reference design provided on your site for AD9371.

In that  kernel tried probing dma driver and went to panic.

Are drivers present on  (iio drivers)

AD9371, AD9375 highly integrated, wideband RF transceiver Linux device driver [Analog Devices Wiki] 

dependent on DMA core , because of which other HDL IP's are not getting probed on my design.

Can you confirm this?

Hello,

I have the ADRV9364 with the ccbob.  I would like to run the no os drivers however, I get this:

make -C no-OS/adrv9364z7020/ccbob_lvds/
make: Entering directory '/home/arl/no-OS/adrv9364z7020/ccbob_lvds'
rm -fr .metadata .Xil hw fsbl_bsp fsbl xilsw sw xsct.log
xsct  ../../../no-OS/scripts/xsct.tcl ZYNQ_PS7 init ../../../hdl/projects/adrv9364z7020/ccbob_lvds/adrv9364z7020_ccbob_lvds.sdk/system_top.hdf > xsct.log 2>&1

../../../no-OS/scripts/zynq.mk:62: recipe for target 'hw/system_top.bit' failed
make: *** [hw/system_top.bit] Error 1
make: Leaving directory '/home/arl/no-OS/adrv9364z7020/ccbob_lvds'

The xsct log shows this:

rlwrap: warning: your $TERM is 'xterm-256color' but rlwrap couldn't find it in the terminfo database. Expect some problems.: Inappropriate ioctl for device
Starting SDK. This could take few seconds... timeout while establishing a connection with SDK
    while executing
"error "timeout while establishing a connection with SDK""
    (procedure "getsdkchan" line 108)
    invoked from within
"getsdkchan"
    (procedure "::sdk::createhw" line 26)
    invoked from within
"sdk createhw -name hw -hwspec [lindex $argv 2]"
    invoked from within
"if {$m_mode eq "init"} {

  hsi open_hw_design [lindex $argv 2]
  sdk createhw -name hw -hwspec [lindex $argv 2]

  if {$m_cpu eq "ZYNQ_PS7"} {
    sd..."
    (file "../../../no-OS/scripts/xsct.tcl" line 8)

I was able to make and build the hdl project with no problems.

I am using the Vivado SDK 2016.4 and I downloaded the dev branch for both no-OS and hdl. 

Does anyone know what the line lengths are for the differential DCO, Data, and OR lines are from the AD9467 to the FMC conn?  The relative skew for the Data and OR lines relative to the DCO signal at the connector would be just as good.  I'm working on interfacing the card to a different dev board and that info is needed.  The constraints in the ZED example on the Analog Devices Wiki for the AD9467 do not contain this information.

Thanks,

--Mike V.

Till now I am using Zynq ZC702+AD9361 setup in Linux.Now I want

to use in windows.I am using the default libraries and projects given

by the Analog devices(hdl-master.zip).In Linux when i just write "make"

in terminal it does all the work required.

Now i want to use the same hdl-master folder in windows as well.I have

installed  Cygwin in windows with the packages necessary for make

included.But i am unable to make the files.there are errors.I am able to

run vivado from Cygwin but unable to make the file.I am attaching

screenshot.

Currently I am using the Digilent Nexys4 DDR development board and want to use the on board ADXL362 accelerometer. But in the Wiki page, I only found the ISE or XPS design for the digilent Pmod, does any one has Vivado Project based on Microblaze software processor with this sensor?

I posted a similar question in another thread and was pointed here (see AD9361 Tx filter calculations )

What are the No-OS ad9361_tx_bb_second_filter_calib() calculations based on? There is some obvious rounding of a 3dB cutoff frequency to determine resistor and capacitor values, but UG-570 does not specify the actual vs. desired cutoff frequency for the Tx secondary single-pole LPF (like it does for the Tx third order BB LPF).

AD9689 customer evaluation card; Schematic, page 8;  FMC pin numbers D4,D5.  This pair of pins is labeled "EXT_REFCLK_TO_FPGA".   They don't seem to go anywhere on the schematic.  The actual reference clock is on pins G6,G7.  Why is this label still there please?    Am I missing something?  Thanks, John Reyland

Please I am checking to see if I can purchase an unpackaged ultra low power microcontroller ?  

Hello,

My customer are designing PLL circuit  with HMC698LP5 (PLL), HMC391LP4(VCO) and OP27 (OPAMP).

And the ouput frequency are 3.9GHz or 4.05Ghz and the reference frequency is 50MHz.

Q1) when they implement a charge pump  of HMC698, can they implement up/down of charge pump at the same time?

Q2) At this time, can they implement a loop filter circuit as passive type?

Q3) They want to handle a fixed LO as 4.05GHz and 3.9GHz with one OP Amp. (OP27S).

       At this time, can they control a tune voltage with under 1V range through OP27S?

Q4)Would you check below their loop filter design?

.

Please advise me.

Regards,

Se-woong

Hi All,

I have a custom board with a BF537 si 0.3. Upon boot up, a simple assembly boot loader is loaded off of sflash. The boot loader configures PPL, EBIU, etc. Then it loads the main program from sflash. Clock in is from a 25MHz crystal. MSEL=19, DF=0, BYPASS=0, SSEL=5, CSEL=0.

The relevant section of our boot loader is:

CLI R2; // Disable interrupts, copy IMASK to R2
 P0.H = hi(SIC_IWR); // enable PLL Wakeup Interrupt
 P0.L = lo(SIC_IWR);
 R0 = [P0];
 bitset(R0,0);
 [P0] = R0;

P0.H = hi(PLL_DIV);
 P0.L = lo(PLL_DIV);
 R0 = 0x0005(Z); // SCLK = CCLK /5
 W[P0] = R0;

P0.H = hi(PLL_CTL); // CCLK - CLKIN * 19, PLL Not Bypassed
 P0.L = lo(PLL_CTL); // No Input or Output Delay Added,
 R0 = 0x2600(Z); // All Internal Clocks on, CCLK on,
 W[P0] = R0; // PLL Powered, Pass CLKIN to PLL
 SSYNC;
 IDLE; // Drain pipeline, enter idled state, wait for PLL wakeup
 STI R2; // After PLL wakeup occurs, restore interrupts and IMASK

The problem we are experiencing is periodically, after the bootloader loads the main program the program seems to be running way slower than expected and we measure SCLK with an o-scope to be about 1/3 less than expected. This happens frequently but not always. When the program runs as expected, we measure SCLK to be 95MHz (as expected). 

Does anyone have any ideas of how to figure out what is happening and how to resolve this issue?

Thanks in advance.

-Matt

Hi, I'm doing a modified version of device_sink block from gr-iio in GNU Radio. I'm working with the ad-fmcomms1-ebz and get this error while trying to connect remotely to the board:

Traceback (most recent call last):
  File "/home/daniel/Documentos/top_block.py", line 116, in <module>
    main()
  File "/home/daniel/Documentos/top_block.py", line 104, in main
    tb = top_block_cls()
  File "/home/daniel/Documentos/top_block.py", line 67, in __init__
    self.fmcomms1_fmcomms1_sink_0 = fmcomms1.fmcomms1_sink('192.1.135.87', 2400000000, 2084000, 20000000, ['voltage0','voltage1'], 0x8000, 1 - 1), cyclic
  File "/usr/local/lib/python2.7/dist-packages/fmcomms1/fmcomms1_swig.py", line 554, in make
    return _fmcomms1_swig.fmcomms1_sink_make(*args, **kwargs)
RuntimeError: Unable to create buffer: -22

 This is the code I'm implementing, it still very unclean but I think it should work:

#ifdef HAVE_CONFIG_H
#include "config.h"
#endif

 

#include <gnuradio/io_signature.h>
#include "fmcomms1_sink_impl.h"
#include "fmcomms1_source_impl.h"

 

#include <cstdio>

 

namespace gr {
  namespace fmcomms1 {

 

    fmcomms1_sink::sptr
    fmcomms1_sink::make(const std::string &uri, unsigned long frequency,
          unsigned long samplerate, unsigned long bandwidth,
          const std::vector<std::string> &channels,
          unsigned int buffer_size,
          unsigned int interpolation,
          bool cyclic)
    {
      return gnuradio::get_initial_sptr
        (new fmcomms1_sink_impl(fmcomms1_source_impl::get_context(uri), true,
                      frequency, samplerate, bandwidth,
                      channels, buffer_size, interpolation, cyclic));
    }

 

    fmcomms1_sink::sptr
    fmcomms1_sink::make_from(struct iio_context *ctx,
          unsigned long frequency, unsigned long samplerate,
          unsigned long bandwidth,
          const std::vector<std::string> &channels,
          unsigned int buffer_size,
          unsigned int interpolation,
          bool cyclic)
    {
      return gnuradio::get_initial_sptr
        (new fmcomms1_sink_impl(ctx, false, frequency, samplerate,
                      bandwidth, channels, buffer_size, interpolation));
    }

 

    /* Función para establecer los parámetros de los dispositivos de transmisión */
    void
    fmcomms1_sink_impl::set_params(unsigned long frequency,
              unsigned long samplerate, unsigned long bandwidth)
    {
      std::vector<std::string> params_dev, params_phy, params_vga;

 

      // Parámetros del dispositivo de transmisión
      params_dev.push_back("out_altvoltage0_frequency_resolution="+
              boost::to_string(frequency));

 

      // Parámetros del dispositivo DAC
      params_phy.push_back("out_voltage0_calibbias="+
              boost::to_string(bandwidth));
      params_phy.push_back("out_voltage1_calibbias="+
              boost::to_string(bandwidth));

 

      // Parámetros del dispositivo vga
      params_vga.push_back("out_altvoltage0_ZD_OUTPUT_frequency="+
              boost::to_string(frequency));
      params_vga.push_back("out_altvoltage0_ZD_OUTPUT_phase="+
              boost::to_string(bandwidth));

 

      fmcomms1_source_impl::set_parameters(this->vga, params_vga);
      fmcomms1_source_impl::set_parameters(this->phy, params_phy);
      fmcomms1_source_impl::set_parameters(this->dev, params_dev);

 

    }

 

    /*
     * The private constructor
     */
    fmcomms1_sink_impl::fmcomms1_sink_impl(struct iio_context *ctx,
          bool destroy_ctx, unsigned long frequency,
          unsigned long samplerate, unsigned long bandwidth,
          const std::vector<std::string> &channels,
          unsigned int buffer_size,
          unsigned int interpolation, bool cyclic)
      : gr::sync_block("fmcomms1_sink",
              gr::io_signature::make(1, -1, sizeof(short)),
              gr::io_signature::make(0, 0, 0)),
      ctx(ctx),
      interpolation(interpolation),
      buffer_size(buffer_size),
      destroy_ctx(destroy_ctx)
    {
      unsigned int nb_channels, i;

 

      /* Set minimum input size*/
      set_output_multiple(buffer_size /(interpolation + 1));

 

      if (!ctx)
        throw std::runtime_error("Unable to create context");

 

      dev = iio_context_find_device(ctx, "cf-ad9122-core-lpc");
      phy = iio_context_find_device(ctx, "adf4351-tx-lpc");
      vga = iio_context_find_device(ctx, "ad9523-lpc");

 

      if(!dev || !phy || !vga)
      {
        if (destroy_ctx)
          iio_context_destroy(ctx);
        throw std::runtime_error("Device not found");
      }

 

      //** Opcional, puede ir en la interfaz del bloque **//
      
      // Canal del dispositivo phy de la tarjeta-
      struct iio_channel *chn0 = iio_device_find_channel(phy, "altvoltage0", true);

 

      // Canal 0 del vga
      struct iio_channel *chn1 = iio_device_find_channel(vga, "altvoltage0", true);

 

      // Canal 1 del vga
      //struct iio_channel *chn2 = iio_device_find_channel(vga, "voltage1", true);

 

      struct iio_channel *chn3 = iio_device_find_channel(dev, "voltage0", true);
      struct iio_channel *chn4 = iio_device_find_channel(dev, "voltage1", true);

 

      //Activación de los canales
      iio_channel_enable(chn0);
      iio_channel_enable(chn1);
      //iio_channel_enable(chn2);

 

      //** Activación de los canales del dispositivo de recepción **//
      // Primero se desactivan todos, si están activados
      // nb_channels = iio_device_get_channels_count(dev);
      // for (i = 0; i < nb_channels; i++)
      //   iio_channel_disable(iio_device_get_channel(dev, i));

 

      // if (channels.empty())
      // {
      //   for (i = 0; i < nb_channels; i++)
      //   {
      //     struct iio_channel *chn = iio_device_get_channel(dev, i);

 

      //     iio_channel_enable(chn);
      //     channel_list.push_back(chn);
      //   }
      // } else {
      //   for (std::vector<std::string>::const_iterator it =
      //        channels.begin(); it != channels.end(); ++it)
      //   {
      //     struct iio_channel *chn =
      //         iio_device_find_channel(dev, it->c_str(), false);

 

      //     if (!chn)
      //     {
      //       if (destroy_ctx)
      //         iio_context_destroy(ctx);

 

      //       throw std::runtime_error("Channel not found");
      //     }

 

      //     iio_channel_enable(chn);
      //     channel_list.push_back(chn);
      //   }
      // }

 

      //channel_list.push_back(chn);
      set_params(frequency, samplerate, bandwidth);
      
      buf = iio_device_create_buffer(dev, buffer_size, cyclic);

 

      if(!buf)
        throw std::runtime_error("Unable to create buffer: " + boost::to_string(-errno));

 

    }

 

    /*
     * Our virtual destructor.
     */
    fmcomms1_sink_impl::~fmcomms1_sink_impl()
    {
      iio_buffer_destroy(buf);
      if (destroy_ctx)
        iio_context_destroy(ctx);
    }

 

    void
    fmcomms1_sink_impl::channel_write(const struct iio_channel *chn,
        const void *src, size_t len)
    {
      uintptr_t dst_ptr, src_ptr = (uintptr_t) src, end = src_ptr + len;
      unsigned int length = iio_channel_get_data_format(chn)->length / 8;
      uintptr_t buf_end = (uintptr_t) iio_buffer_end(buf);
      ptrdiff_t buf_step = iio_buffer_step(buf) * (interpolation + 1);

 

      for (dst_ptr = (uintptr_t) iio_buffer_first(buf, chn);
            dst_ptr < buf_end && src_ptr + length <= end;
            dst_ptr += buf_step, src_ptr += length)

 

        iio_channel_convert_inverse(chn,
          (void *) dst_ptr, (const void *) src_ptr);

 

    }

 

    int
    fmcomms1_sink_impl::work(int noutput_items,
        gr_vector_const_void_star &input_items,
        gr_vector_void_star &output_items)
    {
      int ret;

 

      if (interpolation >= 1)
      {
        ptrdiff_t len = (intptr_t) iio_buffer_end(buf) -
                          (intptr_t) iio_buffer_start(buf);

 

        memset(iio_buffer_start(buf), 0, len);
      }

 

      for (unsigned int i = 0; i < input_items.size(); i++)
        channel_write(channel_list[i], input_items[i],
                noutput_items * sizeof(short));

 

      ret = iio_buffer_push(buf);

 

      if (ret < 0)
      {
        char buf[256];
        iio_strerror(-ret, buf, sizeof(buf));
        std::string error(buf);

 

        throw std::runtime_error("Unable to push buffer: " + error);
      }

 

      consume_each(buffer_size / (interpolation + 1));
      return 0;
    }

 

    void
    fmcomms1_sink_impl::forecast(int noutput_items,
              gr_vector_int &ninput_items_required)
    {
      for (unsigned int i = 0; i < ninput_items_required.size(); i++)
        ninput_items_required[i] = noutput_items;
    }

 

  } /* namespace fmcomms1 */
} /* namespace gr */

The question became when I tried to use th original block from gr-iio and get this warning: thread[thread-per-block[4]: <block device_sink (1)>]: Unable to push buffer: Device or resource busy

I don't think it's necessarily related because -22 errno it's about bad arguments, but get me suspicious about the device's disponibility or configuration in the board. I did the update_tools.sh too and get the same result in both tests, so I'm wandering if it could be some problem with my code or it is something with the card. The card is on a Zedboard ZC706.

Best regards, Daniel.

Hello,

I'll preface by saying that I am relatively new to using DDS' - I've only been using the AD9959 for around 2 weeks now. The project I am working on is to build a function generator using the AD9959 and an SPI connection to an Arduino Due (and a 25MHz reference clock).

I have been able to get everything up and running and am able to get any desired single tone frequency by just writing to the registers of the DDS.

Where I am having difficulties is in trying to create a basic frequency sweep - I know how and what to set all the registers to as per the AD9959 datasheet and using the AD9959 eval board software as a guide (Reg Map Debug window).

I believe the issue that I am having is in triggering the sweep - specifically writing to the profile pins (P3 in my case where I am using channel 3 from the DDS) to change their "logic from 0 to 1" which I figured I could accomplish by just writing to the digital output pins I had attached from the arduino to just go high, but unfortuantely this does not work. I believe I am correct in saying that the 'logic from 0 to 1' has nothing to do with the bytes I am sending to my registers, but is something I need toggle outside of the function registers.

I have considered that it may be a clocking issue but I have played around a bit with putting delays in my code to no avail.

Also oddly enough, when I run the attached code, I just get an output of 20MHz, but if I toggle the power of the board (so turn it off and on again) I then get an output of 45.8MHz.

I have attached the arduino code that I am using.

For my hardware connections, Arduino -> DDS (U2 row):

-Pin 10 -> CSB (my slave select pin)

-Pin 9 -> Reset

-Pin 4 -> IO_UPDATE

-SPI MOSI -> SDIO_0

-SPI SCLK -> SCLK

-Pin 6 -> P2

-Pin 7 -> P3

The adjacent pin on the DDS for each of the above is also grounded to the various grounds on the Due board:

-Digital Pin GND: IO_UPDATE + RESET + P3 + P2

-Analog Pin GND: CSB

-SPI GND: SDIO_0 + SCLK
(Using different grounds as for some reason grounding to the same ground on the arduino meant I couldnt get an output FROM the arduino, perhaps due to crosstalk??)

Any and all help will be greatly appreciated.

Cheers,

Chris.

EDIT: I managed to resolve my issue - the problem was the 1K pull down resistor on the profile pins on the actual PCB board of the DDS. So what was happening is my trigger signal was not strong enough to actually trigger the sweep. I solved this by just putting the arduino output for that pin through a digital buffer and then to the DDS board. My attached code does in fact work fine except for some reason the no-dwell mode does not seem to work.

Hi, 

I'm trying to configure the AD7124-4. I'm facing really bizarre issues.

1. when I try to write 0x8087 to Channel_0 register (0x10), it doesn't get written. I know this since when I read back I get 0x8081. And this is not limited to this register, but in multiple 16-bit registers.

2. I have successfully read 0x05 register and it returns 0x04.

3. I successfully wrote 0x008011 to the IO_CONTROL_1 register and I'm able to read back the same value.

I'm using an STM32 discovery microcontroller to interface with the ADC7124 chip using a SPI bus running at 0.175 Mhz.

My SPI_write code:

uint8_t SPI_Tx(uint8_t address, uint32_t data, uint8_t nbytes){

   uint8_t i;
   uint32_t mask;

   GPIO_ResetBits(GPIOE,GPIO_Pin_4);// Pull CS low

   while(!SPI_I2S_GetFlagStatus(SPI2,SPI_I2S_FLAG_TXE));
   SPI_I2S_SendData(SPI2,address);
   while(!SPI_I2S_GetFlagStatus(SPI2,SPI_I2S_FLAG_RXNE));
   SPI_I2S_ReceiveData(SPI2);
   while(!SPI_I2S_GetFlagStatus(SPI2,SPI_I2S_FLAG_TXE));

   for(i=0 ; i< (nbytes); i++){
      mask = ((1<<8)-1)<< (8*i);
      SPI_I2S_SendData(SPI2, (uint8_t)((data & mask) >> (8*i)));
      while(!SPI_I2S_GetFlagStatus(SPI2,SPI_I2S_FLAG_RXNE));
      SPI_I2S_ReceiveData(SPI2);
      while(!SPI_I2S_GetFlagStatus(SPI2,SPI_I2S_FLAG_TXE));
}

GPIO_SetBits(GPIOE,GPIO_Pin_4);// Pull CS HIGH

return i;
}

Am I missing something here ? Any help would be greatly appreciated.