When operating the HMC914 as a single ended input. What is the best choice for terminating the unused differential input? I do understand the inputs are terminated with 50 ohms to VCC internally. Would it be best to leave these unused inputs open or AC ground them through a capacitor?
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HMC914 single ended input termination
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HMC799 simulation tool/Spice model
Hello,
I am interested in the HMC799 amplifier. However I would like to understand better how it compares with similar devices such as the Texas Instruments OPA847 or the Linear Technology LTC6268-10. The reason why I want the HMC799 is that apparently it could enhance the bandwidth a lot by keeping comparable noise levels. So my question is
- is there any simulation tool that I could use to have a good comparison between these devices such as Hmc799 model for LTspice, Tina-TI?
- Are there any similar devices, as for example the ADN2880 with a spice model that could be used for comparison?
Many thanks
Francesco
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ADF4350/1 FSK function
Hi Sir,
Does ADF4350/1 could do FSK function?
If yes, how to do FSK on the chip?
We would like to have as same as LMX2571's FSK function.
Thank you!
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About I2S
Hello sir
I am using msp430 controller to capture the I2S data.I am not using this I2S for communication I want this data for the level detection.I use LR clock and Data pin only for capture the data. But i am unable to know when the cycle of the signal is completed.
how can i do this please help me.
thank you
regards
priyanka sharma.
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ADRV 9361/64 Life Time.
Looking at using the ADRV9361-Z7035 and ADRV9364-Z7020 into products. Are you able to confirm the expected lifetime?
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AD9162
Dear Sir/Madam,
For the AD9162 SPI register configuration, do I only need configure the sequence register, without configuring other register. is there command for reading the sequence register.
Thanks.
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AD9361 RX FIR sample rate ADC_CLK/2
AD9261 Reference Manual UG-570 contains following information:
"The Rx FIR has two options for its sample clock, either ADC_CLK or ADC_CLK/2"
How I can change this?
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AD9625 Translator
I am looking at using a translator to connect to the AD9625 SPI interface. I only need the SDIO as bi-directional but I am intending putting the SCK & CS on the same device (perhaps even IRQ, FD, PWDN & RSTB). Originally I was considering your ADG3304/8 (or TI's TXB0104/8) which originally appeared okay however I notice that your eval boards make use of the OnSemi FXLA104 on this interface. All these type of translators appear to need a reasonable drive current into their inputs for correct operation. The only IOH & IOL values I can see on the AD9625 spec are for SDIO (800uA for logic '1' & 50uA for logic '0') and I am not sure if these are maximums.
What are the output drive capabilities of the AD9625 output pins mentioned above ?
Presumably the FXLA104/8 is fine to use with the AD9625 (lower drive currents required) but could we happily use the ADG3304/8 (or TXB0104/8) in its place or are their drive requirements too high (hence why they were not used) ?
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Using ADAU1761 an external MCLK not working when DSP is running
Thanks!
That was the patch I was looking for! Now everything is (almost) working. I stumbled upon another strange problem:
if I use the oscillator integrated on the evaluation board, to generate the MCLK, everything works as espected; if I use an external signal (with the same 12.288Mhz frequency, verified with a scope) as MCLK, it works as long as I don't use the DSP.
What am I doing wrong?
Thanks
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USB driver problem - ADUS82Z -
I'm just installing the ADI-SigmaStudio Rel3.15-x64 on our new Dell PC, WIN 7 Enterprise, 64bit and getting an installation error because of the USB driver for our EVAL-ADAU1452MINIZ.
Do you have a idea or a working driver version for the USB Adapter ADUS82Z, label labeled 1.3?
Do you have a idea or a working driver version for the USB Adapter ADUS82Z, label labeled 1.3?
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Allocating Array Memory to SDRAM ADSP-21489 EZ-Kit
Hi, I am writing a program using the ADSP-21489 Ez-Kit, which uses a large delay line array that is more than the on-chip memory can accommodate. I would like to allocate this array to the external SDRAM (MT48LC16M16A2P). In my research on the topic I have seen this done via pragma marks such as this:
“#pragma section (“seg_ext_dmda”)
int array1[100];”
I have also gathered that external memory needs to be configured in the app.ldf, which should be modified via the system.svc file.
I have tried doing this, but whenever I check the use external memory option in the system.svc, my program (which is based on the ADSP-21469 Block Based Talkthru Example modified for the ADSP-21489) fails to pass audio to the output, even when no external memory is being allocated.
I have heard that SIMD is possible from external memory on the ADSP-21489 processor. Is this true, and does this work with the run-time DSP library functions?
Can someone please provide an example as to how to correctly to external memory using the ADSP-21489 Ez-Kit?
Thanks!
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AD9826 - Single Channel SHA-Mode.
We have interfaced AD9826 with microcontroller for DC test Voltage measurement. ADC Clock is 1Mhz and timing's for ADCCLK and CDS2 clock is provided into the attachment. The ADC processor is configured into SHA Mode to read the dc voltage from voltage source.
To test, Analog input (0-3V) is provied to VINR using potentiometer.
Settings for registers are as follows,
Configuration Register -->
Input Range : 4V,
Internal Vref : Disabled(Also tried by Enabling this),
3CH Mode : Off,
SHA Mode Enabled,
Input Clamp Bias : 3V,
Mux Configuration Register -->
Only Red Channel selected.(Analog Input is given to this pin).
ADC Clock and CDS Clock timings waveforms are generated as below,
Problem :
Data read from data lines is not as per the voltage applied to VINR input.
Since applied input varies from 0 to 2V, the data output should vary from 0x0000 to 0xffff respectively. But the output is read as 0x0000, 0xff00, 0x0A0A or some random values.
So is it due to improper timings , wrong settings or any other reason.
Please help us with this issue.
Thanks and Best Regards,.
Rohit M.
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can codec ADAU1761 detect voice by removing wind and music noise?
Hello,
My application is to give audio input while driving bike and detect human voice. For that wind noise remove and voice detection is essential. I have tesetd ADAU1761 codec for my application. But when I tried algorithm of Voice Activity detection and VAD flag, I found that ADAU1761 do not differentiate human voice and other noise like music or whistle. I have also attached project file. I want to know using ADAU 1761 codec, can we precisely detect human speech?
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AXI I2S Zynq+ Fails Timing Vivado 2017.2
I am using the axi_i2s_adi (dev branch) IP block in a Zynq+ Vivado 2017.2 design targeted for P/N xczu2eg-sbva484-1L-i and it is failing timing. See below. Can you help?
Paths failing timing.
Active Constraints for the I2S IP block
AXI_I2S IP Configuration
Constraint file
Schematic showing one of the data paths that is failing.
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PFD capable of identifying 2.4G analog signals
Our system need a PLL to output very stable 2.4G analog sinusoidal signals，we know many chips can do that. But in our system，the situation may be different from the usuals. In our system ,we will give PFD 2.4G analog signals，than we hope it come through charge pump, loop filter and vco, the signals which create by vco would be disturbed by noise and than send back to PFD。It means we need a chip works as a traditional PLL to deal with two 2.4G analog signals,one is stable ,the other whose frequency is stable(2.4G) but the phase varies. At last, the vco out a 2.4G analog signals which could compensate phase jitter.
We want to know if chips like HMC7044 could do that.
Thank you!
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Capturing the raw data using ADAU1772
Hi,
We are using Analog devices board ADAU1772 for developing a capturing application for multi mi data.
1. Is it having any internal DSP to capture the raw data on the board?
2. If not, how can we capture the raw data?
3. Are there any images and OS information about the board?
4. Are there any sample application for capturing and rendering the data?
5. Is it possible to connect the board to windows PC for capturing the raw data? Where can I get the drivers for interfacing the PC and board?
Regards,
Prasad
@
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Analog or Digital Audio Interface
For an audio application we have already identified some boundary conditions to which we now want to find the best suitable soluton.
Boundary conditions:
1. The clock from the real-time system is expected to be 8 kHz. The sample rate should be supported by all components, so no anti-alias filters need to be implemented.
2. The latency from the analog input to the analog output should be minimal.
3. The microphone should have linear transmission behavior in the relevant frequency range up to 8 kHz and have the lowest possible phase rotation.
4. Up to 4 microphones must be read synchronously.
5. The amplifier should have a power of at least 2 x 25 W at 8 ohms.
6. The cost of the components should be as low as possible.
7. The distance between the microphones and the board is up to 1 m.
Now there are different options. So far, we've been relying on the ADAU1372 codec because it has a low latency and provides the appropriate number of IOs. Now, however, we have seen that new MEMS microphones have already integrated an I2S interface. In addition, there are amplifiers which also have an integrated I2S interface. In this case, the audio codec wouldn't be necessary. Certainly one must consider that I2S lines are likely to be susceptible to EMC interference for the planned distance to the board. For the amplifier, it would be no problem because it is placed on the board. Do you have any recommendation out of the analog devices portfolio?
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RX Sensitivity degradation with AD9363 vs AD9361
Hi
For one of my customers that moved from AD9361 to AD9363 and getting lower rx sensitivity.
Same board, same peripherals, sam management platform and interfaces.
See table attached for the percentage of the jperf in the sensitivity test.(new rf-AD9363 results in the RIGHT SIDE of the table, AD9361 results in the LEFT SIDE ).
All units are in DBm. also see that the second channel RF2 is showing much worse sensitivity levels with the AD9363.
Please advise what/where to look for...
The Configuration registers are the same for both AD9363/1.
Thanks
Freddy
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Clock Powerup timing
I have a design using ADAU1452 processor, the power for which may be turned on/off by a control CPU. The XTALIN pin is driven at 24.576MHz from an FPGA which also runs from the same on/off power lines as the ADAU1452.
My first question is:
Is it OK to power up the chip and then apply the XTALIN clock signal a short while later? It takes a second or two to program the FPGA and only then does the clock get established.
2nd question:
I am using the SPI slave interface to load the program etc. Is there a suitable register I can read before I do this that will contain a known value to confirm the chip s powered up and running? At the moment I am reading PLL_CTRL0 (address 0xF000) which says in the data sheet should have a reset value of 0x0060 but I am getting 0x0000...
Thanks anyone for any advice you can offer
PhilipJ
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How do I fix an "adisAPI Transfer Timed Out" error?
We recently purchased the ADIS16448 and the EVAL-ADIS2Z. We are looking to capture data through the Analog Devices IMU Evaluation program, for a period of 12 hours and a sampling rate of 50 Hz. Currently, when the data capture module is run with the sample rate set to 51.2 SPS, with all data capture registers selected except GPIO_CTRL and SEQ_CNT, it returns an error saying "adisAPI Transfer Timed Out." It also does this when all registers have been returned to factory settings, or if only one data capture register is selected. Is there a way to fix this problem? Thank you!
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