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Regarding AD6688/AD9208 Eval board - AD9208_3000EBZ

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Hello,

 

We recently designed a PCB for AD6688/AD9208 ADCs based on the eval board design files of AD9208_3000EBZ. As per ADI, this is the official eval board for AD6688/AD9208. The entire ADC power supply of our PCB was designed based on this eval board schematic (almost a copy paste).

 

However, when we measured the voltages at most test points we see they are 10% higher than necessary. Further, on calculating the actual voltages based on the resistor values used in the AD9208_3000EBZ, we also see that the voltages are 10% higher than required (DRVDD_0P9 is 1V instead of 0.9V, 2V4_AVDD is 2.6V instead of 2.4V,  AVDD_1P8_REG is 2V instead of 1.8V and so on)

 

It would be very helpful if someone could clarify if it was intentional from ADI to design the eval board with 10% higher voltage than specifications? If yes, why was it done ? Is it even safe to operate the ADC at 10% higher values ?

 

Regards,

Raju


AD9208 information request

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Hi there, 

 

I'm interested in the AD9208 but need some information to see if it suits my application. I like to look at the phase differences of multiple channel signals coming in at say 100 to 1.1 GHz. Questions are:

 

1) Does the ADC have an onboard anti-aliasing filter?

2) can the ADC sample both its channels simultaneously with no phase delays introduced?

3) If multiple ADCs are used, can they be synched say from an external clock or otherwise?

 

 

 

Many Thanks,

Amin

AD5933 invalid and inaccurate measures

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I´m using Ad5933 with AFE (AN -1252). the external clock signal is provided by DS1077. I wanna do sweeps from 10 Hz to 1 kHz. I divided my output-signal (excitation) into many pieces to perform sweeps. For example on sweep is from 10 Hz to 30 Hz with an increment size of 1 Hz and id like to perform 20 increments. I programmed a loop with 4 repeats for each frequency and I'm using the first 2 values to calculate system phase and gain factor. the last two values for measuring impedance and phase. I calculated mclk with the following formula:

MCLK = OutFreq * 16 * 1024 / NbPeriods

Number of settling cycles is 5

I get many inaccurate measures or hundreds of invalid values. decreasing settling cycles gives me more invalid values and more inaccurate measures... what could I do wrong?

SigmaStudio "autoEQ" don't do the "auto-part" ( ADAU1701 )

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Hi 

 

can you please help me with a "small" task:
 ( with a  ADAU1701 )

in sigmaStudio/schematic I have a "simple" project:

"signal in" - "mixer" - "AutoEQ" - "signal out"

 

I have imported the frequency responce file, and see this in gaph

 

 

then i click on the target response-tab

and change the target

then i click on the design Settings-tab

and see this:

if i click the Init filter i get "one blank filter"

if i click the design filter i get "15 blank filter"

so can you please tell me how to activate the "auto"-part of the EQ?

How do i link the Anlog Devices supplied AD630.cir file into my schematic/simulation using ADIsimPE

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How do i link the Anlog Devices supplied AD630.cir file into my schematic/simulation using ADIsimPE

ADG1404 ENABLE PIN VOLTAGE

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Hi all,

 

I am using the ADG1404 MUX in my designs and I have supplied the EN (Enable pin) with a voltage of up to 3V3. 

 

What I want to know is what is the maximum voltage that I can supply to the EN (Enable) pin? I have this question because it would be easier for me to just set it to +5V, which I use for Power Supply. The MUX mostly stays on.

 

Would that be possible? In the datasheet says that the Digital Pins (A1,A0 and EN)can take GND − 0.3 V to VDD + 0.3V. My assumption is that I can give +5V. Am I right?

 

Also, if this is possible (Enable pin to +5V), then what should the Digital Logic voltage be for the A1, A0 pins? Would they understand a 3V3 voltage as HIGH or not? 

 

Thanks in advance.

 

Georgios 

AD-FRQCVT1-EBZ

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Hi all, I need to control the AD-FRQCVT1-EBZ board with a picozed using the SPI interface. My is a no-OS project. Can someone help me, some link where this is documented?

Thanks

Stefano

send data zynq pl to ad9361 fmcomms5

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Hi I generated a signal from fpga part of my zynq zc706 board and now I am trying to send this signal to fmcomms5 board and analyze it . What is the way to do that? I connect the output of the signal to fmc ports in .xdc file Does it works or Do i need use hdl reference design which seems a bit complicated.I already ask question in this forum ad I did not get any helpful answer so I am asking again


Interfacing ADC & DAC of AD9361 with BB module running in PL side of picozed SOM

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In my application my BB modules for RX and TX are available in VHDL and I need to configure the AD9361 and need to send my TX data to DAC and RX data from Ad9361 to My RX modules. What i find is all the HDL drivers given connects the DAC and DAC data to AXI port. Whether I can use the drivers(applicable verilog files only) as such for my application or as per the data port timing diagram given, I can make a module in VHDL for ADC & DAC interface.If i save time by using your HDL drivers, what are the files I need only to send data to DAC and receive data from ADC. Please advice

AD9371 HDL Reference Design Files for ZCU102

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Hi All, 

 

         Hope all are doing fine.

 

 I have downloaded AD9371 HDL Reference Design from ADRV9371 HDL Reference Design [Analog Devices Wiki]   created and testing the project on ZC706  can I use the same files for creating the project for ZCU102? otherwise can i get the design files for creating AD9371 for ZCU102.

  Waiting for your reply

 

Thank you

Naveen S

AD-FMCDAQ2-EBZ on ZCU102

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Hello,

 

We are trying to get up and running using the AD-FMCDAQ2-EBZ with the ZCU102 board, but we are having issues setting up and loading the example project. We are using Vivado 2017.2.1 and the /dev branch for no-OS and hdl.

 

Using the following commands (cygWin) I successfuly make the HDL and no-OS projects:

- export PATH=$PATH:/cygdrive/C/Xilinx/SDK/2017.2/bin

- make -C hdl/projects/daq2/zcu102

- make -C no-OS/fmcdaq2/zcu102

- make -C no-OS/fmcdaq2/zcu102 run

 

What are the next steps to running/loading the project on the ZCU102?

AD9144 Single Link mode 2

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Hello,

I made a custom board with the AD9144 DAC part.

From your daq2 reference design (Vivado_2016_R2 for ZC706 no-os), I started to make my own FPGA design to address 4 DACs instead of 2.

So instead of having a JESD204b link in Single link MODE 4, it will be Single link MODE 2.

 

I was wondering if you had an example for MODE 4 configuration (FPGA and AD9144 sides).

 

Thanks for your help.

 

 Chris

 

PS: You can find the vivado system attached

About EVAL-AD7626

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Hi,

I would like to use EVAL-AD7626.

So, I have a question.

 

When using boards EVAL-AD7626 and EVAL-SDP-CH1Z, is it appropriate to recognize that you can control ADC with FPGA and can take data?

 

Best Regards,

Yuya

applicability of Emission, immunity and environmental test report of SOM1 for picozed is applicable to SOM2

Protecting input of AD9250

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Hi there,

 

I've got a system with an AD9250 which is being driven by an HMC1023. The HMC1023 is driving a 330 ohm load across the ADC input through a pair of 40R resistors (i.e. one in each arm of diff pair giving a total load of around 400R). At the ADC input we have some shunt capacitance and some series 10Rs into each input pin to reduce peak transient current. The input is biased at 0.9V.

 

The datasheet states that the maximum voltage level on any of the AD9250 analog input pins is 2.0V (AVDD+0.2) referenced to AGND.

 

Although at first I believed that the HMC1023 was only capable of driving a 2Vppd signal into a 400R load (per the datasheet which would limit our max ADC voltage to well below 2V), it appears that if the input power keeps rising, the voltage that we see at the output of HMC1023 can reach a heavily distorted square-ish wave of 3-3.5Vpp in EACH arm of the differential pair. This is clearly in excess of the maximuim voltage of the ADC input. I wanted the system to be inherantly safe such that the driver stage was not capable of blowing up the ADC.

 

I was wondering if it would be possible to have any further information on the reason for the 2.0V limit on the Ain pins and, if it is due to the conduction of protection diodes for example, what the maximum allowable current would be into this input as we might be able to protect it by increasing the value of the series 10Rs. If is not a protection diode limit, any information on whether the described situation presents a genuine threat and any possible means of mitigating that threat would be most appreciated.

 

Thanks


ADXL372 Problems with detecting shock via Instant On mode

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I'm having trouble getting the ADXL372 to wait for a shock in Instant ON mode.

 

I looked around for example code found the "ADXL Demo Suite", but that seems to be specific to the ADuCM3029 CPU and the ADXL372 evaluation board which does not yet appear to be available.

 

So I very carefully ported the adxl372_spi_drv.c code to my environment (EFM32 and Rowley) and tested it very very carefully and thoroughly.

 

The related code adxl_example.c uses this driver code to collect acceleration data in FULL_BW_MEASUREMENT mode via FIFO. This seems to work fine for me. Here is the api calls that do this:

 

    result = rb_Detect_ADXL372_Sensor();      // reset chip

    result = rb_ADXL372_Init();     // set chip to FULL_BW_MEASUREMENT mode and set up/enable FIFO to STREAM

    status = rb_ADXL372_Read_FIFO_Data();  // read data from FIFO

 

Then I modify this code to:

 

   result = rb_Detect_ADXL372_Sensor();   // reset chip

    result = rb_adxl372_Configure_FIFO(512, BYPASSED, XYZ_FIFO); // reset FIFO just on general principals

    result = rb_ADXL372_Init();  // comment out setting the chip to FULL_BW_MEASUREMENT mode; 

    result = rb_adxl372_Set_Op_mode(STAND_BY);

    result = rb_adxl372_Set_Op_mode(INSTANT_ON);

    status = rb_ADXL372_Read_FIFO_Data();

    

    while(true);

 

And the chip drops all the way through to the while loop without waiting for a shock.

 

I repeated this many times while testing until I was absolutely sure everything had been ported correctly and was working. Basically with the INSTANT_ON modification the chip continued to work as if it was still in FULL_BW_MEASUREMENT mode.

 

Then I tried my software on a new board. On the new board it hung waiting for a shock just as it should. Exactly once. Then it went into the same mode as the first board. Power cycling and the included reset instruction did not change the behaviour back to the correct one.

 

The I tried a third board. Same thing. It worked once and then it no longer paused waiting for a shock.

 

Is there something else I should be doing to get the chip into INSTANT_ON mode?
Is there example code that demonstrates INSTANT_ON mode? There seems to be very little code available for this chip.
Is there chip errata? I looked and couldn't find anything. Its too bad Google can't search the analog.com site.
The chip really does not seem that complicated, but maybe there is something missing from the documentation
Thanks for any help.
- Rod

ADV7842: Difficulty configuring for component input

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We are using the ADV7842 in our product and I am currently attempting to configure the device to capture component video. HDMI input works fine but I'm having a difficult time getting the component processor to lock on to the incoming component signal. The analog front end I believe is set up right; I set PRIM_MODE to 0x01 and VID_STD to 0x13 (and other values e.g. vertical frequency). Both CH1_STDI_DVALID and CH1_SSPD_DVALID read 1 so it appears that the STDI block is getting (near) valid results:

 

CH1_BL = 5088 (expected 5091)
CH1_LCF = 749 (expected 750)
CH1_LCVS = 5 (expected 4 to 5)
FCL = 1866 (expected 1868)

but the CP never seems to indicate a lock. What other configuration settings am I omitting? Can the inaccuracies above cause issues as well?


I have attached i2c register dumps of the AFE, CP, and IO spaces; I'll provide additional detail as needed.

Relation between V(LDOCC) and VDD of HMC920

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Hi,

I am using HMC920 to bias HMC637A.

Queries:

1)In HM920 what is the relation  between VDD and V(LDOCC)?

2)In order to bias HMC637A I need V(LDOCC)= 12.20. To get  V(LDOCC)= 12.20, my VDD has to be greater than 12.22(Correct me if I am wrong)

3)If above assumption is wrong can I get V(LDOCC)= 12.20 with VDD=5V

4)If my assumption in query 2 is right what is the Minimum VDD has to feed in to VDD terminal to get V(LDOCC)= 12.20

 

Noted Thank you.

How to Bias HMC8410 and HMC994

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Will Active bias controller(HMC920) support  HMC994 and HMC8410?

If yes why it is not listed out in the datasheet of HMC920?

If no Suggest me Active bias controller for HMC994 and HMC8410?

ADGM1304 RF Common Open

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The datasheet describes: "avoid RFx pins left open circuit".

Is this also valid for RFC?

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