Dear Support Team,

We have several custom boards with Zynq and AD9364. The layout of the digital board is largely based on the Zedboard.

The HDL and all the drivers for AD9364 work fine for all the boards apart from one (again all the boards are identical in the design). On that board the cf-ad9361-lpc driver does not exist in the Linux kernel (e.g. cat /sys/bus/iio/devices/iio\:device*/name doesnt show the above driver). Please see below the output form dmesg on Linux. The devicetree checked and it is the same as with the boards that it works with so nothing wrong with the devicetree, HDL or Linux. 

I suspected the hardware problem so i searched the forum and found this: cf_axi_adc failing to probe on 0x80000000  failed with error -5 and the possibility of some noises on traces, clocks, ets. Please note thought that although it says that the TX tuning failed the TX path seems to be working fine. I know that I can bypass the calibration in order to avoid this but I really wouldnt like to do that. I am also aware of Digital Interface Timing Verification [Analog Devices Wiki]  and i went through this document.  

Is there anything else i can do for some further debugging/testing or any other solution you would recommend?  

We desperately need to get this board working so any advice on what to do will be highly appreciated.

One constraint, I dont have physical access to the board (since it is in production) but have a full remote access for debugging and testing.

Many thanks,

Milos

===dmesg relevant output

platform 79020000.cf-ad9361-lpc: Driver cf_axi_adc requests probe deferral
ad9361 spi1.0: ad9361_probe : enter
ad9361 spi1.0: ad9361_probe : AD9361 Rev 2 successfully initialized
cf_axi_dds 79024000.cf-ad9361-dds-core-lpc: Analog Devices CF_AXI_DDS_DDS MASTER (8.00.b) at 0x79024000 mapped to 0xf00c2000, probed DDS AD9364
TCP: cubic registered
NET: Registered protocol family 17
can: controller area network core (rev 20120528 abi 9)
NET: Registered protocol family 29
can: raw protocol (rev 20120528)
can: broadcast manager protocol (rev 20120528 t)
can: netlink gateway (rev 20130117) max_hops=1
zynq_pm_ioremap: no compatible node found for 'xlnx,zynq-ddrc-a05'
zynq_pm_late_init: Unable to map DDRC IO memory.
Registering SWP/SWPB emulation handler
mmc0: new high speed SDHC card at address 0001
mmcblk0: mmc0:0001 016GB 15.2 GiB
mmcblk0: p1 p2 p3 p4 < p5 p6 >
SAMPL CLK: 61440000 tuning: RX
0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
0:# # # # # # # # # # # # # # # #
1:# # # # # # # # # # # # # # # #

ad9361 spi1.0: ad9361_dig_tune: Tuning RX FAILED!
SAMPL CLK: 61440000 tuning: TX
0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
0:# # # # # # # # # # # # # # # #
1:# # # # # # # # # # # # # # # #

ad9361 spi1.0: ad9361_dig_tune: Tuning TX FAILED!
cf_axi_adc: probe of 79020000.cf-ad9361-lpc failed with error -5

AD7740 CLKIN drived by 32.768kHz external clock.

When I used cylinder type crystal with 12.5pF Load capacitor ，AD7740 can work.

When I used  surface mount type crystal with 12.5pF Load capacitor,AD7740 can not work.

In datasheet page.8, I get the infomation about 32kHz watch crystal needed external circuitry.

MY question is  the 32khz watch crystal means 32.768kHz crystal ?

And  when I used cylinder type crystal with 12.5pF Load capacitor , AD7740 always can work without the external circuitry.

The AD8001 has no information on input pin differential and common mode input capacitance.  There is no open-loop gain/phase curve either.

Title: Data Controlled Asymmetric Clip threshold clipping issue

Description: The negative side of the sinewave is hard clipped at -1.0 even if Clip Down pin is set at -0.4 value. The positive side is clipped at 1.0 even if Clip Up pin is set at 0.6:

SigmaStudio Version: 3.14

OS: Windows 7

ADXL345   ACT唤醒问题请教？ 

想工作在这种情况：配置ADXL345工作在睡眠模式（0.1uA），当ACT超过门限值时，ACT中断产生。

现在的问题是：进入睡眠模式后，ACT无法唤醒，请帮忙看看配置有没有问题。

ADXL345_WriteReg(POWER_CTL,0x00); //待机模式
ADXL345_WriteReg(INT_ENABLE,0x00); //关闭中断
ADXL345_WriteReg(DATA_FORMAT,0x2B); //4位SPI 模式，中断低电平有效，全分辨率，右对齐
ADXL345_WriteReg(BW_RATE,0x0A); //采样率

ADXL345_WriteReg(INT_MAP,0x00); //ACT INT1
ADXL345_WriteReg(TIME_INACT,0x01); // 1s/LSB --> 1s
ADXL345_WriteReg(THRESH_ACT,0x05); //ACT门限值      62.5mg/LSB
ADXL345_WriteReg(THRESH_INACT,0x02);//INACT门限值   62.5mg/LSB

ADXL345_WriteReg(ACT_INACT_CTL,0xF0);//ACT交流，所有轴参与 
ADXL345_WriteReg(INT_ENABLE,0x10); //ACT  中断使能

ADXL345_ClearFlag();  //清除中断标志。ADXL345_ReadReg(ACT_TAP_STATUS);                            

                                       //                          ADXL345_ReadReg(INT_SOURCE);

ADXL345_WriteReg(POWER_CTL,0x04); //待机模式   配置为0x08为测量模式  ，为0x00也试过。

现在的情况是：能够进入睡眠模式，但不能唤醒

                          如果配置成测量模式，有40uA左右，这种情况下可以唤醒。

I am trying to interface to an AD5593R. I need 3 channels of conversion at a sample rate of 96 KHz per channel. I am using Python 3 with the following commands:<write_i2c_block_data(address,cmd,vals)> and <read_i2c_block_data(address,cmd)> . I get a result, but no matter what I input to the different channels, I always get the same result, no change. I can read the device address okay. I tried using several write commands and one read command, but no success there. I am not experienced in this area. Can you advise on how I should set up the parameters for the commands?

Hello,

I'm feeding a differential signal into the AD7124-4 where both signals have no reference to the ADC's ground. The ADC is supplied by battery, the signal is generated externally. Do I have to make sure that the signal has a common mode voltage, eg VDD/2, referring to the ADC ground? Or does the ADC support a differential signal like this without further circuitry?

Thanks!

Dir,I have a problerm about AD7173 set,I want to AD7173 work in  continue  convert all channels model,but I don't konow how to set,I have try my best for this,but I am fail.This is my code,thank you for  correct it.

1.GpioConfig(PDSW_DIS,OP_EN2_3, MUX_IO_DIS, SYNC_EN, ERR_DIS, ERR_DAT, GP_DATA3_HIGH, GP_DATA2_HIGH, IP_DIS1, IP_DIS0, OP_EN1, OP_EN0, GP_DATA1_LOW, GP_DATA0_LOW);
2.SetUpConfig(REG_SETUPCON0, UNI_POLAR, REF_BUF_DIS, AIN_BUF_DIS,BURNOUT_DIS, BUFCHOPMAX_DIS, REF_SEL_INT);
3.FilterConfig(REG_FILTCON0,SINC3MAP_DIS, ENHFILT_DIS, ENFILT_NO,ORDER_SINC5_SINC1,ODR_10SPS);
4.ADCModeConfig(REF_EN,SING_CYC_EN,DELAY_0US, MODE_CONT_CONV, CLOCKSEL_INTOS);
5.INTModeConfig(ALTSYNC_DIS, IOSTRENGTH_DIS,DOUT_RESET_DIS, CONTREAD_EN, DATA_STAT_EN, REG_CHECK_DIS,CRC_EN_XOR,WL24);

6.ConConv(); 

   thank you!

email:  zqskq@163.com
            

I am using a combination of 3 AD5380, all in stand-alone mode (control via SPI), to get desired voltage levels on any of the channels of this DACs. The SPI has different slave-select lines to select one of the 3 DACs for communication.

The SPI communication works as expected, but not for the first SPI transfer.

The first SPI transfer actually set the same channel on all the 3 DACs. There are actually 2 issues here

(a) in SPI: when I initialize my SPI-SW module for the first time, due to a HW feature!, all the salve select lines are pull low for a very short duration of 5us. This cannot be avoided.

(b) in AD5380, now since all the SYNC-N lines were pulled low for 5us, somehow all 3 DACs "become ready" to accept the command on DIN that would follow (note: the SCLK are also shared). Although the command would be targeted at only one of the DACs (whose slave select would be pulled low and the corresponding DACs SYNC-N pulled low), due to this strange issue in AD5380, the remaining 2 DACs also accept this command. Hence in all 3 DACs, that one channel (specified in the 24-bit SPI command) are set to a same voltage. This is not desired.

Can you please confirm if my observation is correct. From the data sheet, the value t6 says should be 33 ns (in Standalone), so this actually confirms my observation is correct; but I am not sure. If my observation is incorrect then I have to further look into my HW design if something nasty is happening, because other than this single issue, everything else seems to work fine.

Your help will be much appreciated. Thank you.

We’re currently using the Cirrus CS48LV12 (DSP) and CS42L73 (Codec). It appears that Cirrus isn’t interested in supporting the DSP/echo cancellation code, so I’m looking for an alternative. One option would be to purchase the code and run it on the NXP K65 that’s in the design, but we’re short on MIPs, so I either need to find a higher performance CPU or add a DSP/M4? to run the DSP code. Since we’re changing the DSP, I suspect I should also look at changing the CODEC to something simpler/lower cost. Any suggestions would be greatly appreciated.

Thanks,
Rick

Hello,

I've setup a quick test issuing non-chained DMA controlled SPI transfer on an ADSP-21469 Ezboard. The code repeatedly sends a small buffer over the SPIB interface and I've verified this is working fine. I'd like to trigger a DMA complete ISR but it's not firing. I'm using VisualDSP 5.1.2 and I've verified global interrupts are enabled, P18IMSK is unmasked in the LIRPTL register, and I can see the P18I interrupt being latched after every transfer when stepping through the code. I suspect that the way I am registering the ISR, using "interrupts(SPILI,spi_isr); " is incorrect but I can't be certain as all other examples I've seen were in assembler and I'm not yet up to speed on SHARC assembly. Attached is a copy of the C code I've thrown together, is there anything wrong with my setup code?

Thanks,

Mike Wolak

Hi,

My AD9854 chip is not responding .

I communicated using the SPI protocol.

My crystal is 100MHz (ASEM1-100.000MHZ-LC-T from Abracon LLC)

But  i think im not getting the crystal frequency to the AD9854, when i tried to probe it. My crystal might be damaged during the time of soldering.

1) So if the crystal is not working fine can i communicate with the SPI communication?

2)When i roamed around the link in EngineerZone AD9854 SPI programming , in the question part the questioner used the parallel port D5 ----> SDIO_Buffer_enable. What is meant by the SDIO Buffer enable he meant here? i'm  confused with the question.(He is also used SPI)

I would like to use the chip AD9854 and AD9912 for a long period and i haven't get any responds from both the chips.

If the chip is up then i can use the same for many projects and products that we are planning to use.

Regards

ArunKuttath

JLKeipLouijieCDSBKevin.G

i have an BF707-Blip2 board. when i debug the demo "VendorUsbDemo_BLIP2",  

when run to UsbInit->cld_bf70x_bulk_lib_init,   the first cld_bf70x_bulk_lib_init return CLD_ONGOING, but the second run cld_bf70x_bulk_lib_init , the debug cannot run next code. 

can something help?

I have run into an issue where once in a while when I boot my target connected to the AD9361 the RX BIST results show no valid data / clock windows. When this occurs, I checked the clock and frame signal coming from the AD9361, and the clock is present, but the frame signal is always low.

Here is the output of the /sys/kernel/debug/iio/iio:device1/bist_timing_analysis file:

CLK: 0 Hz 'o' = PASS
DC0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
0:. . . . . . . . . . . . . . . .
1:. . . . . . . . . . . . . . . .
2:. . . . . . . . . . . . . . . .
3:. . . . . . . . . . . . . . . .
4:. . . . . . . . . . . . . . . .
5:. . . . . . . . . . . . . . . .
6:. . . . . . . . . . . . . . . .
7:. . . . . . . . . . . . . . . .
8:. . . . . . . . . . . . . . . .
9:. . . . . . . . . . . . . . . .
a:. . . . . . . . . . . . . . . .
b:. . . . . . . . . . . . . . . .
c:. . . . . . . . . . . . . . . .
d:. . . . . . . . . . . . . . . .
e:. . . . . . . . . . . . . . . .
f:. . . . . . . . . . . . . . . .

normally when it is working properly I get:

CLK: 60000000 Hz 'o' = PASS
DC0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
0:o o o o . . . . o o o o o . . .
1:. o o o o . . . . . o o o o . .
2:. . o o o o . . . . . o o o o .
3:. . . o o o o . . . . . o o o o
4:. . . . o o o o . . . . . o o o
5:o . . . . o o o o . . . . . o o
6:o o . . . . o o o o . . . . . o
7:o o o . . . . o o o o . . . . .
8:o o o o . . . . o o o o . . . .
9:. o o o o . . . . o o o o . . .
a:. o o o o o . . . . o o o o . .
b:. . o o o o o . . . . o o o o .
c:. . . o o o o o . . . . o o o o
d:. . . . o o o o o . . . . o o o
e:o . . . . o o o o o . . . . o o
f:o o . . . . o o o o o . . . . o

After I reboot linux (not a full power cycle) it functions again.

What could cause the device to not output an RX Frame?

Thanks!

Dear Support Team,

We have several custom boards with Zynq and AD9364. The layout of the digital board is largely based on the Zedboard.

The HDL and all the drivers for AD9364 work fine for all the boards apart from one (again all the boards are identical in the design). On that board the cf-ad9361-lpc driver does not exist in the Linux kernel (e.g. cat /sys/bus/iio/devices/iio\:device*/name doesnt show the above driver). Please see below the output form dmesg on Linux. The devicetree checked and it is the same as with the boards that it works with so nothing wrong with the devicetree, HDL or Linux. 

I suspected the hardware problem so i searched the forum and found this: cf_axi_adc failing to probe on 0x80000000  failed with error -5 and the possibility of some noises on traces, clocks, ets. Please note thought that although it says that the TX tuning failed the TX path seems to be working fine. I know that I can bypass the calibration in order to avoid this but I really wouldnt like to do that. I am also aware of Digital Interface Timing Verification [Analog Devices Wiki]  and i went through this document.  

Is there anything else i can do for some further debugging/testing or any other solution you would recommend?  

We desperately need to get this board working so any advice on what to do will be highly appreciated.

One constraint, I dont have physical access to the board (since it is in production) but have a full remote access for debugging and testing.

Many thanks,

Milos

===dmesg relevant output

platform 79020000.cf-ad9361-lpc: Driver cf_axi_adc requests probe deferral
ad9361 spi1.0: ad9361_probe : enter
ad9361 spi1.0: ad9361_probe : AD9361 Rev 2 successfully initialized
cf_axi_dds 79024000.cf-ad9361-dds-core-lpc: Analog Devices CF_AXI_DDS_DDS MASTER (8.00.b) at 0x79024000 mapped to 0xf00c2000, probed DDS AD9364
TCP: cubic registered
NET: Registered protocol family 17
can: controller area network core (rev 20120528 abi 9)
NET: Registered protocol family 29
can: raw protocol (rev 20120528)
can: broadcast manager protocol (rev 20120528 t)
can: netlink gateway (rev 20130117) max_hops=1
zynq_pm_ioremap: no compatible node found for 'xlnx,zynq-ddrc-a05'
zynq_pm_late_init: Unable to map DDRC IO memory.
Registering SWP/SWPB emulation handler
mmc0: new high speed SDHC card at address 0001
mmcblk0: mmc0:0001 016GB 15.2 GiB
mmcblk0: p1 p2 p3 p4 < p5 p6 >
SAMPL CLK: 61440000 tuning: RX
0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
0:# # # # # # # # # # # # # # # #
1:# # # # # # # # # # # # # # # #

ad9361 spi1.0: ad9361_dig_tune: Tuning RX FAILED!
SAMPL CLK: 61440000 tuning: TX
0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
0:# # # # # # # # # # # # # # # #
1:# # # # # # # # # # # # # # # #

ad9361 spi1.0: ad9361_dig_tune: Tuning TX FAILED!
cf_axi_adc: probe of 79020000.cf-ad9361-lpc failed with error -5

i have one BF707-Blip2 board， i use CCES to compile the project "ColorConv_bf707". compile is OK.

but when in debug mode, lines ouptut

-----------------------------------------------------------

Loading application: "D:\Workspace\CCES\2.6.0\examples\imageprocessingtoolbox.blackfin_2.4.0\colorconv(707)\Example\adsp-bf707-CCES\colorconv_bf707\Debug\colorconv_bf707.dxe"
Load complete.

Core clock: 384000000 Hz
System clock: 192000000 Hz
System clock 0: 96000000 Hz
System clock 1: 192000000 Hz

------------------------------------------------------------------

then i run command next in PC

------------------------------------------------------------------

hostapp -u

<host> start servicing USBIO

------------------------------------------------------------------

CCES output is 

-----------------------------------------------------------------

pUSBCB->u32_Command = 2.
pUSBCB->u32_Command = 7.
USBIO_TaskStart begin.

---------------------------------------------------------------

the application dead in the code "Result = adi_stdio_USBD_InitUsb();" 

where can i do something ?

How can i interface AD9265 with CMOS single ended clock driver without using transformer ?

do i need a clock driver ? actually i am driving my clock from FPGA cyclone V.

Do you have any design file which interface this adc to cyclone V ?

What differential amplifier should i use for single ended analog input (AD8375/AD8370/ADA4938) ?

Hi,

I develop a code for sc589.

 I would like to read a .mp3 or .wav  audio  form sd card witch were encoded at 44.1kHz. The data exchange by SPI protocol.

I should increase the sample rate to 192kHz. 

Do you have any idea how i can realise this?

thank's

Hello,

           We are developing a linux application(ad9371-iiosteram.c) for AD9371. We are referring to ad9361-iiosteram.c and dummy-iiosteram.c file..

          Now we are able to Acquire local context, acquire both tx and rx devices and create tx and rx buffer. now I want to push IQ data to hardware. I am looping back tx and rx using RF cables ( TX1 => RX2 ). Then I want capture IQ samples from Rx2 port. But iio_channel_read API is giving me segmentation fault. What may be the reason ?

   PFA of ad9371_iiosteram.c