AD7091 needs a software reset sequence. But normal SPI controller can't pull CS high between the second and eighth SCLK cycles to short cycle the read operation. Can we use a normal 8 bits read to do this??
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ad7091 software reset
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AD7648 : slowest fclk and affect
Hello,
I have a question about AD7468 SAR ADC.
The AD7648 has a specification about fclk as followings. (tabel-4 of the datasheet)
Parameter Limit at TMIN,TMAX Unit Description
fSCLK 3.4 MHz max Mark/space ratio for the SCLK input is 40/60 to 60/40.
10 kHz min 1.6 V ≤ VDD ≤ 3 V; minimum fSCLK at which specifications are guaranteed.
20 kHz min VDD = 3.3 V; minimum fSCLK at which specifications are guaranteed.
150 kHz min VDD = 3.6 V; minimum fSCLK at which specifications are guaranteed.
It means that fclk has a limitation of lowest speed, affected by VDD.
Q1. Which performance will be affected if the fclk more slower than this ?
SNR ? DNR ?
Q2. Would you tell the lowest frequency of fclk when the VDD is 3.4V ?
Best regards,
ysuzuki
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Help to change the sampling rate with AD9371
Hi,
I am using the AD9371 with IIO oscilloscope for Linux and I am struggling with the sampling rate. I want to set the TX sampling rate to 55.18 MHz but I don't know how to do it. I guess I have to change filters' coefficients and IQ rate in the TX Settings tab of the AD9371 Advanced Plugin and then press the Save Settings button, but I can't find the right combination to have 55.18 MHz at the end. Do I have to change some things in the CLK Settings tab too? In the AD9361 it was done automatically just by changing the sampling rate and then the coefficients were calculated automatically to fit the desired sampling rate, so I am quite lost with the AD9371.
Can someone help me please?
PS: I attached some screenshots of the TX Settings and CLK Settings tab if you don't know what I'm talking about.
Thanks for your answers.
Yaël
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AD9680 Config Issues
Hi,
I am using AD9680BCPZ_1000 in my application. I am facing some configuration issues in bringing up the ADC. My ADC setting requirements are as below.
ADC Clock: 640MHz, LVDS
Sysref: 20MHz continuous, LVDS
Analog inputs: Differential 2MHz sine wave coming out of AD9152 DAC (for testing).
Analog input amplitude: Around 600mVp-p
SYNCINB: LVDS coming from FPGA
JESD Requirement:
L=4,
M=2
F=1
Lane rate: >6.25Gbps and <12.5Gbps
Don't want DDC and scrambling to be enabled
When I check the response from JESD204B receiver IP core on FPGA, it says ILAS is passed. But afterwards I am not getting any output in JESD lanes corresponding to the analog input.
I have attached the ADC configuration I am using and also the ADC register readback data. Request you to review the ADC configuration and let me know where I am going wrong. Kindly let me know if you need any more information.
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Document for ADRV9364-Z7020 and ADRV9361-Z7035
Hi,
I found two new EVBs, ADRV9364-Z7020 and ADRV9361-Z7035 at ADI web site.
But I couldn't find any document from the EVB site of each one.
Can I get some technical document of these including UserGuide, Schematic and PCB layout ?
Before purchasing these, I need to know How we can use it and How it works.
Thanks.
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ADAU 1450 I2S and GPIO output issues
Hello!
I'm currently working on system based on ADAU1450, it's my own hardware design board.
ADAU is working - I can communicate through SPI, write a program (using NumBytes and TxBuffer files generated by SigmaStudio) and read memory using microcontroller. The clocks (MCLK output, LRCLKs, BCLKs) are present at outputs after flashing DSP program. The thing is I can't output anything at serial audio ports.
For example, I set in register controls that SDATA_OUT0 acts as LRCLK, BCLK master, with 2 channel TDM.
Then I put Sources>Oscilators>Sine Tone block and fed it to the output channels 0 and 1, where SDATA_OUT0 in 2 ch TDM should be. The problem is SDATA_OUT0 pin stays low for whole time.
As in attached project I tried some DC output for SDATA_OUT1, white noise for SDATA_OUT2 - either doesn't work and stays low for whole time. Am I missing something? I want to communicate with external audio codec's DAC.
Also, I tried to source GPIO output - it doesn't respond to any block, only to MP7 Write register in SigmaStudio MULTIPURPOSE/AUXADC tab in hardware configuration can change it's output. When I link DC block to GPIO output it looks like DC block is completely ignored, whether it's set to 0 or anything non-zero.
The question is - where am I making mistakes? None of SDATA_OUT pins are pulled-up or pulled-down externally.
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error when building FFT code on ADZS BF 548
Hi everyone
Iam using ADZS BF 548 evaluation board,when i try to build the FFT code its showing error,can anyone suggest the reason for it and let me know how to solve the error.
the below error is displaying when i build the program.
.\rfft_fr16.asm
[Informational ea1056] ".\rfft_fr16.asm":583 Preg read after write which requires 3 extra cycles
.\twidfftf_fr16.c
.\twidfftrad2_fr16.c
.\uart.c
".\uart.c", line 34: cc1045: {D} warning: missing return statement at end of
non-void function "init_uart"
}
".\uart.c", line 171: cc0111: {D} warning: statement is unreachable
return 1;
.\vsprintf.c
Linking...
[Error li1040] ".\general purpose timer.ldf":353 Out of memory in output section 'bsz_L1_data_a' in processor 'p0'
Total of 0x70a0 word(s) were not mapped.
For more details, see 'linker_log.xml' in the output directory.
[Error li1040] ".\general purpose timer.ldf":435 Out of memory in output section 'bsz_L1_data_b' in processor 'p0'
Total of 0x70a0 word(s) were not mapped.
For more details, see 'linker_log.xml' in the output directory.
Linker finished with 2 errors
cc3089: fatal error: Link failed
Tool failed with exit/exception code: 1.
Build was unsuccessful.
find the attached code for the same and suggest what has to be changed in the LDF File.
thanks for reply in advance
Best Regards
Amar TR
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Using EV-ADRN-WSN-1Z for reading acceleration data from 4-5 nodes
I am working on a project to develop a wireless body area network where accelerometers will be placed on different parts of the body and send date wirelessly to a base station connected to a PC. I looked at your evaluation kit EV-ADRN-WSN-1Z and found it very reasonable for this application. My question is about the received raw data at the basestation, we need some method to extract the raw acceleration data with real time stamps at base station to be used later one by some custom built GUI to extract useful information, will that be possible and how?
Also can we accommodate more sensor nodes than only two provided by the development kit.
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Can a project have different include paths based on the Configuration?
Hello,
Working in CCES 2.4.0.0
The project I am working on has a common area of base code which needs to be compiled on a per-channel basis. The difference between these two compiles is a commonly named set of header files located in different folders which specify the channel unique parameters (addresses, memory space, etc).
Is there a way to setup a single project with different configurations (or a different method) that point to the unique header files and can build uniquely named ldr files? Or am I stuck making multiple projects?
Thanks!
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ADSP BF 548 FFT Libraries
Hi everyone
Iam new to blackfin,iam using ADZS BF 548 evaluation board,i need to compute FFT for the samples coming from the ADC, where do i find the Libraries (API's) for FFT for ADZS BF 548?
if available please attach the source and header file with the reply which will be very useful.
thanks for the reply in advance
Best regards
Amar TR
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Re: Sharc-21584 TDM mode testing.
1) How to test the TDM mode in Sharc processor.
2) If TDM8 mode is implemented how to observe the output?
3) Weather all 8channels output will be observed in single channel?
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AD9910 Sweep frequency source in DRG mode
Hello,I have some questions about AD9910 to consult.I want to use AD9910 to generate a circular sweep signal source .
The limit of sweep frequency:1MHZ—21MHZ
Step size:100HZ
Rate size:50ns
According to parameters set above,the total sweep time from 1MHZ to 21MHZ is 10ms,the Fsysclk is 800MHZ,belong are some parameters I wrote to the registers.
CFR1:0x00804200
CFR2:0x004e0820
CFR3:0x140f4128
DRLIMIT: 0x06b851ec0051eb85
DRSTEP:0x0000021900000219
DRRAMP:0x000a000a
But I find the step size of output is 50HZ and the total sweep time of output is 10ms by messuring the period of DROVER pin.so does it mean the actual rate size is 25ns? why is it different from what I set?what is more,when I double the value of step size in register,then the step size of output become 100HZ but the total sweep time of output become 5ms.I was confused.I want to know that how I can do to keep the step size 100HZ while the total sweep time is 10ms.
THANK YOU!
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About ADM2587E output impedance
Hi,
I would like to use ADM2587E.
So, I have a question.
Is the output maintaining high impedance when the power supply of ADM2587E is OFF?
best regards,
Yuya
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Will ADIsimRF 2.0 work in Windows 10
Will ADIsimRF 2.0 work in Windows 10?
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Is ADALM2k a open source project just like ADLAM1K?
and more related questions:
Why ALM2K choose to use different GUI interface, not use ALICE?
Is there a plan to provide case enclosure for alm1k? The usb port is not mounted rather than solder points. More or less like a prototype rather than a product.
How many alm1k has been produced? Are there any reversion on alm1k since hardware reversion D? David mentioned that there is a resistor value change on voltage regulation circuit. Any other changes? Would any change log recorded, e.g. in github?
alm2k is the replace to alm1k, or they both both have place in the product line for AD ALM ecosystem? Could anyone describe the vision and road map?
thanks
xio
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high impedance circuit design for ECG/EEG Using AD8244
1.Is it possible to make high input impedance circuit ecg acquition (to overcome for mismatch between source impedance of different leads, working against the input impedance of the front-end amplifier ) using ad8244
2.please give me the application circuit for high input impedance ecg using ad8244
3.Is it possible to make active electrode ciruit for EEg using ad8244.
3.please give me the application circuit for high input impedance EEG using ad8244
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ADF7242 Network MAC802154 Linux Driver
With Reference to the below link:
ADF7242 Network MAC802154 Linux Driver [Analog Devices Wiki]
We wanted to backport the driver to Linux kernel 3.14.79. What is the best way to do so? Has anyone tried this with success?
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No Os driver on hdl-2016-r1 branch
Hi,
I have build the project using hdl-2016-r1 branch for Arradio+Arrow SOC setup. Project was successfully build and .sof file was generated. When i downloaded the hardware image(.sof) and run the no OS driver, I am getting error that ad9361 init faild with invalid product id. I have probed the SPI_DI, SPI_SCLK and SPI_ENB all signal is normal but part is not giving data (no activity in SPI_DO of Arradio).
Please help me.
Regards
J S Hyanki
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AD9467 +interposer FMC+ LM605 capturing data
Dear all,
I am working with the LM605 xilinx, the AD9467 Evaluation Board and the FMC interposer. I have followed the documentation that you provided form the analog devices wiki: https://wiki.analog.com/resources/fpga/xilinx/interposer/ad9467
I uploaded the bit file to the FPGA and I have checked a sinusoidal signal using chipscope busplot to see the captured signal. The system is working correctly after checking the messages through tera-term.
But I would like to save all data from the DDR3 512MB to my computer. In order to print data to the UART terminal, I modified the cf_ad9467_ebz.c including the attached code at the end:
*********************************************************************
xil_printf("testing DMA acquisition . . . \n\r");
adc_capture(50000, DDR_BASEADDR);
for(i=0;i<50000;i++)
{
xil_printf(".");
rdata = Xil_In32(DDR_BASEADDR+(i*4));
xil_printf("data[%d]=0x%x\r\n",i,rdata);
}
xil_printf("cleaning up.\r\n");
cleanup_platform();
xil_printf("done\n\r");
************************************************************
I performed the project in the following steps:
1) Using iMPACT, programmed the FPGA with the initial system.bit from XPS provided by the wiki page of analog device
1) Opened the reference design in XPS. Built netlist and bitstream, then exported to SDK.
2) Created new “Hello, World!” project in XPS. Replaced contents of helloworld.c with contents of cf_ad9467_elf.c
3) Built the project (“Debug” configuration. Attempting “Release” as I type this message)
4) The elf file was built from SDK itselfThen I went to the Project Explorer (left hand side), expanded "sw -> Binaries", I saw the helloworld.elf file. Right click and then "Run As -> Launch on Hardware".
The chipscope was launched and I had a UART terminal ready before you run the software.
The system doesn´t respond and I need to restart the LM605 board due to the chipscope is not working and SDK doesn´t respond.
I am wondering how could I print data to the UART terminal without changes on the bit file.
If I decide to use XMD tool to connect to the FPGA and read the data directly from the memory, I can find an example of a tcl script here. How could I use it in SDK? I need to create elf file and launch to the FPGA?
There is an example of how could I save or print data using an analog device ADC with the LM605?
Thanks in advance
Regards
Carlos
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hydrogen poisoning
Are the HMC424 and HMC232 sensitive to hydrogen poisoning?
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