Hi, 

I have a few questions regarding the ADV748X and ADV7613. I have attached the specs and block diagram flow for references of my customer's project.

It is a HDMI to LCD application involving scaler and some drivers.

1. I can't seem to get the spec differences between ADV7480, 7481 and 7482. Besides number of lanes for their output paths, any feature should I take note based on my application?

2. Does ADV748X support audio stereo of 2.6W ?

3. Does this chip able to perform/support the Scaler to the output setting, as stated below, the LCD output is 1280x480.

4. Is there any CSI-2 to LVDS converter from ADI based on my customer's application?

5. Based on ADV7613, I believe I do not need a LVDS converter based on the spec... Any advise on this comparing to ADV748X?

Thanks!

Greetings,

We have an application where we plan to use both REFin1 and REFin2, where REFin1 is used for a differential measurement on AIN1/2, and REFin2 for a differential measurement for AIN3/4.

Question1:  If I lose one of the references, do I get a NOREF for only the channel being measured?

The datasheet claims the conversion results will be clamped to all 1's on a NOREF. 

Question2:  Will this clamping only occur on the data coming from the channel whose reference is low?

If I have an "overvoltage" (say my ref is 2.5V and I put 4V across AIN1/2), the ERR bit should be set and the data should be all 1's (all 0's if I swap AIN1/2 pins around; fake "negative").

Question3:  Will this ERR only be present for that channel whose input is overvolt?

Thank you!

Dan

Hello,

My customer is considering to use AD9824 in their IR comera product.

For deceiding to use AD9824, they say that they need to simulate this device with PSPICE tool frist.

They say that they already downloaded BXL file of AD9824 and tryed to convert this to PSPICE files using your Ultra Librarian Reader.

But  for this,it seems that additional license for PSPICE tool is needed.

So I request a simulation file of AD9824 which can be used in PSPICE tool.

Would you provide this simulation file of AD9824 that can be used in PSPICE tool?

Regards,

Se-woong

What is the physical location where gain tables stored. As per the documentation it is shown as

"/sys/bus/iio/devices/iio:device1# ls /lib/firmware/ad9*"

However when I went to iio:device1 folder, I could not find any folder with the name lib or firmware. Can you please point me to the correct location.

Our systems engineer came up with a custom gain table and I would like to try it on the FCOMMS2 folder. So, I would like to learn to do the following

1. Ability to locate the correct path to upload the file

2. To validate if the FCOMMS2 is pointed to the correct gain table

3. Do I have to program or run any other procedure like calibration etc before trying it on

4. How to read and verify if the new custom gain table is being used 

5. Understand any other procedure steps that I have missed stating above

I'm having trouble following what is considered a Link in the AD9691.  On page 49 of the datasheet:

The AD9691 has one JESD204B link. The device offers an easy

way to set up the JESD204B link through the quick configuration

register (Register 0x570). The serial outputs (SERDOUT0+/-} to

SERDOUT3+/-}) are considered to be part of one JESD204B link.

Note that only SERDOUT0-3 are mentioned.  What about SERDOUT4-7?  Are these part of the one JESD204B link, or are these considered a second link?

Similarly, on pg 44 of the datasheet:

The AD9691 JESD204B data transmit block maps up to two

physical ADCs or up to eight virtual converters (when DDCs

are enabled) over a link. A link can be configured to use one,

two, or four JESD204B lanes.

This statement only accounts for 4 of the 8 SERDOUT pairs.  Does this mean that there are actually 2 links of up to 4 lanes??

This statement seems to be in conflict with the statement from page 1:

Users can configure the Subclass 1 JESD204B-based high speed

serialized output in a variety of one-, two-, four- or eight-lane

configurations

Also, Pg 44 also states:

L is the number of lanes per converter device (lanes per

link) (AD9691 value = 1, 2, or 4)

However, Table 25 on pg 49 shows L = 1,2,4 or 8.

One further comment from page 69.  Register 0x58B, bits 2:0 show the L setting.  Value 111 is stated as indicating "7 lanes".  Surely this actually indicates 8 lanes??

Hello,

We have implemented the AD9913 in a design very simular to that of the AD9913 evalution board.

Board information:

         Connections to AD9913 chip:

- Reference clock: 25 MHz Crystal Oscillator

- Seperate 1,8V power supply for analog and digital pins.

- RSET = 4,64K

- A out and B out terminated in 200 Ohm resister to analog ground

- Reset controlled by uC

- Power Down input shorted to digital ground

- IO - Update input  controlled by uC

- SER/PAR input  shorted to digital ground

- CS input controlled by uC

- CLK input controlled by uC

- parallel adress lines inputs unused and shorted to digital ground

- Internal PLL set to 250 MHz

We are using the AD9913 in a single tone mode, generating a 3MHz output. Programming the device is no problem and the output waveform looks fine.

However the device seems to spontaneously reset sometimes.

Most of the time this means the 25 MHz reference clock stops and the output waveform stops.

Other times there is still some kind of oscillation present at the output but it looks very spurious, impossible to trigger on.(What is very strange is that in this situation there is no reference clock present, but there is still some sort of output signal)

A few times the 3 MHz output simply dropped to 84 kHZ.

By performing a reset (active high) and reprogramming the device we can restart the device.

We can repeat this behavior by generating a small ESD puls in the neigbourhood of the device, this pulse does not interfere with other digital components near the AD9913, such as a µC and memory..

We have tested 3 boards so far, all with the exact same behaviour.

Have you seen this behaviour before? I must emphasize that the ESD pulse is very small.

Any help is appreciated!

Thank you!

Best regards,

Our Team.

Hi,

I am using the AD9915 demonstration board to generate a CW for a precise duration (10ns to .655ms). The goal is to control an Acousto-Optic Modulator (AOM) as advertized on the data sheet.

For this I use the sweep mode with frequency jump enabled and no dwell high. This gives me DC=0, then CW, then DC=0. I am getting some erratic results however for the duration of my CW pulse. This approach was inspired by this thread in engineering zone: https://ez.analog.com/thread/81157.

The general settings are to provide a 10MHz clock from a GPS disciplined oscillator converted to ECL square signal with a Linear Devices LTC6957HMS-1 demonstration board. I use the AD9915 internal PLL to set the clock to 2.4GHz. I enable OSK, enable sin output, direct the DRG to frequency, use profile 0 and use the DRCTL pin to trigger the pulse.

The DRG settings are with the lower limit at 0 and the upper limit at 100MHz (M=0xaaaaaab). I set the rising step size to 1, set the lower jump point to 1 and upper jump point to M-1. I then vary the ramp rate according the pulse duration that I need (P=N=13 gives a 100ns pulse duration). This scheme provides one step size interval at 0Hz and one step size interval at 100MHz. With no dwell high enabled, the DDS returns to 0Hz at the end of those two step size intervals.

The problem that I have is that the latency seems to be erratic and because of that my pulse duration is unpredictable. Both values of the rising and falling ramp rate (P and N) influence the pulse duration (I would have thought that only the rising ramp rate would be important since I am using a positive ramp). For some values of P and N the timing is an integers of 10ns (e.g. 4 gives 40ns, 7: 60ns, 13: 100ns, 19: 140ns) while for other values this is not an integer at all.

Below is the registers dump that shows the problem with N and P set to 12:

<?xml version="1.0" encoding="utf-8"?>
<Settings ExternalClock="10">
<Registers>
<Register Address="00" Data="00010300" />
<Register Address="01" Data="008C6000" />
<Register Address="02" Data="0004787F" />
<Register Address="03" Data="00052120" />
<Register Address="04" Data="00000000" />
<Register Address="05" Data="0AAAAAAB" />
<Register Address="06" Data="00000001" />
<Register Address="07" Data="00000000" />
<Register Address="08" Data="000C000C" />
<Register Address="09" Data="00000002" />
<Register Address="0A" Data="0AAAAAAA" />
<Register Address="0B" Data="0AAAAAAB" />
<Register Address="0C" Data="0FFF0000" />
<Register Address="0D" Data="00000000" />
<Register Address="0E" Data="00000000" />
<Register Address="0F" Data="00000000" />
<Register Address="10" Data="00000000" />
<Register Address="11" Data="00000000" />
<Register Address="12" Data="00000000" />
<Register Address="13" Data="00000000" />
<Register Address="14" Data="00000000" />
<Register Address="15" Data="00000000" />
<Register Address="16" Data="00000000" />
<Register Address="17" Data="00000000" />
<Register Address="18" Data="00000000" />
<Register Address="19" Data="00000000" />
<Register Address="1A" Data="00000000" />
<Register Address="1B" Data="A3000024" />
</Registers>
</Settings>

I attaching a Python script which will simulate the problem. I hope that this timing issue problem can be addressed. The time invested in getting this to work is quite significant. I would be unfortunate to have to discard everything at this point.

Thanks,

Hello everyone,

for our telecom system, we need to cascade two selected amplifers (hmc618a, 1700 - 2200 MHz tuned) in order to obtain more than 30 dB gain.

We thought to follow the datasheet reference design.

Are there some guidelines or issues we have to know to do that? Or Have you some advices?

Could the two cascaded stages oscillate?

Many thanks.

best regards,

Antonio L.

Hello,

I saw your AD-FMCDAQ2-EBZ and it almost meets the need for what I want to do - but it does not have the option for an external ADC/DAC clock.

I saw some references to AD-FMCDAQ3-EBZ, but no product page.  Is this something that will be coming out soon?  Will it be like the FMCDAQ2 but provide an external clock capability?

Thank you!

hi 

i want to use AD7190 in weigh scale system but when i try to fetch data Continuously from ADC and plot them in STM Studio .you can see result varying with time (time in ms) !!! please help me to found that problem..

I am using no-os driver to configure an AD9364.

I have set the RX and TX sample rates to 60MHz.  This results in the following clock chain:

ad9361_set_trx_clock_chain: 960000000 480000000 240000000 120000000 60000000 60000000
ad9361_set_trx_clock_chain: 960000000 240000000 120000000 60000000 60000000 60000000

Both rx and tx FIR are disabled.

Looking at the AD9364 users guide "DIGITAL Rx BLOCK DELAY" it looks like I should be seeing a delay contribution from the digital filters of approx:

                  HB3           HB2           HB1    

RX path (2/240M) + (2/120M) + (7/60M) = 8.3ns + 16.6ns + 116ns = 140ns

TX path (2/120M) + (2/60M)  + 0             = 16.6ns + 33.8ns             =  50.4ns

= 190.4ns total delay for digital filters

I am using an ILA in Vivado to capture the TX and RX data just before clocking in/out to the AD9364.  I am seeing a delay of approx. 800ns.

I know that the 190ns is only the digital filter delay.  Is there a description somewhere of what the source migth be for the additional ~600ns delay I am measuring

Hello, neilw

I asked you for help before and I am now still need your help with different problems.

To understand easily I briefly describe my test setup.  I am using a AD9680-500 as a digitizer for a input signal from a Agilent generator. The SYSREF timing signal is produced by a AD9528 PLL device, and the SYNC signal by a on-board button with a jitter cleaner device MAX6816EUS+. I take the output of this digitizer as data source for the transmitter of links to the receiver board. In this test setup I experiment the data transmission in with Homologous clock( both transmitter and receiver use clock from the same clock) and non-Homologous clock which means I use different clock for the receiver side with the transmitter( clock multiplied from a on-board 40MHz clock for transmitter and recovered clock for the receiver). In both cases I received the expected increasing data samples for long time (more than half an hour) if use the predefined data in the ADC memory in the test mode.

In a normal data digitizing mode, I input the sin signal from Agilent generator to the ADC input with anamplifier ADL5565. I received also the sin shaped data for a short time roughly in mill-seconds, and only in mill-seconds in both recovered clock and non-recovered clock in the receiver side/board. I noticed a RXLOSSOFSYNC =2 which means a loss of synchronization on the link. If I short the inputs of ADC we have number 7FXX with a RXLOSSOFSYNC=0 in most time.

Could you please help me on how to get a stable working for a normal sin input signal? That is please have a think where I am wrong in using the ADC device?

We need to use either the TX1A or TX2A output of an Avnet board with AD9361 in it to generate a Signal on which we'll be changing the frequency doing a gradual sweep from 1 to 6 GHz. However we have observed that the strength of the TX signal gets reduced significantly as we increase the frequency in the TX LO, mainly when we go above ~4GHz.

We have 2 of these Avnet boards and we have observed the same behavior in both of them.

Has anybody experienced this TX signal strength reduction on high frequencies?,

If so, based on your experiences, is there something we can do to prevent this behavior?

Due to this limitation, until now we have had to use an external Signal Generator as TX source on our Application's prototypes, making use only of RX1 and RX2 on the Avnet AD9361 board, but it would be very cost convenient for our project it we could be able to use either TX1A or TX2A of AD9361 to generate our System's TX signal.

We would really appreciate it if somebody could give us any help to solve this problem.

Many Thanks in advance,

Sergio Garza

5.15.2017

I am working with an AD9959 and an Arduino Uno in manual mode. On the oscilloscope screen, i have  SYNC_CLK and Channel 0 connected. 

I am trying to write code to access the different DDS registers. I have not successfully done this before. All I want to do is enable the multiplier which should cause the SYNC_CLK output frequency to increase. It is currently running at 25Mhz. 

I have attached my code below for review. I have attempted to run this code, but there is not change on my oscilloscope screen.

Is there something or some command that I am missing that is preventing me from successfully changing the multiplier? I know my commands are being sent and that SPI communication is active because I have checked the bit stream directly on the oscilloscope. So neither of these things should be an issue.

Dear Sir/Madam:

We would like to get design files for HMC493 Evaluation PCB 107384.

Can you help us on this?

Thank you very much.

Regards,

Timothy

Hello,

I am looking for a DAC in order to proportionally steer a power wheelchair using a raspberry pi model 3.

This means we have a power source of 5 V.

The wheelchair requires the voltage signals to be -1,2 to +1,2 V to go backwards  and forwards . The resolution doesn't need to be especially high. Do I need a negative power supply as well?

I bought an AD5734, which I thought fits the mentioned requirements, however I don't get it to work. I soldered it to a PCB and connected it as well as I understood from the manual (The manual is not exactly a How To, which I probably need). What's the code I have to send? I tried hexadecimal, sending a "word" to address the output range select register and then sending a "word" corresponding to a certain output voltage I calculated. However I always measured 0 V on the output. Are there any other "words" I have to send first?

Sorry for the lengthy post.

Any help will be highly appreciated.

Thx

Konstantin

Hello,

I am attempting to have a TI MSP432 microcontroller communicate with the AD9956 via the SPI protocol. I have coded three iterative messages, where the first two attempt to write to CFR1 and CFR2 registers, while the third message writes to PCR0 (0x06), with its data being 0 phase and a specific frequency tuning word. I have confirmed the output signal from the MSP432 is correct, assuming that no time delay is necessary between sending the instruction byte and the actual data to the DDS. Is this assumption correct?

I do not unfortunately currently have the capacity to read from the DDS' registers. Earlier today I ensured the DDS was working by controlling it via PC software.

My code is attached below, and I can attach a screenshot of the logic analyzer screen depicting the output waveform if desired. Any help would be appreciated. In addition to the standard SPI protocol, three bits are assigned to be digital low to ensure the DDS chooses PCR0 as the active frequency register.

Please note: The code's name is vestigial, and does not perfectly correlate with the given TI sample code.

Thank you for your time.

Hi dear colleagues,

I had just ordered and received a set of EVAL-ADAU1761Z, and plan to use all the on board analog audio inputs (IN1, IN2, and IN 3/4) as the Mic1, Mic2 and stereo audio input respectively in a karaoke application.

However it seems to me that SigmaStudio Input Cell did not allow me to do this, as it has only two analog input channels (ch 0 and ch1) and the rest 8 channels are all digital (EVAL-ADAU1761Z.pdf said this)? How to configure the SigmaStudio such that I can use all IN1, IN2, and IN 3/4 from SigmaStudio Input Cell? Sorry that I am confused.

Thanks,

Kelvin

Hi guys,

I am trying to program the UART without library.

So I want to send a message and I wrote this code:

#include <stdlib.h>
#include <stdio.h>

//UART Register
#define COMCTL *((long*)0x40005030) // UART Control Register
#define COMDIV *((long*)0x40005028) // Baud Rate Divider Register 
#define COMFBR *((long*)0x40005024) // Fractional Baud Rate Register 
#define COMLCR *((long*)0x4000500C) // Line Control Register
#define COMTX *((long*)0x40005000) // Transmit Holding Register
#define COMRX *((long*)0x40005000) // Receive Buffer Register
#define COMLSR *((long*)0x40005014) // Line Status Register
#define COMIEN *((long*)0x40005004) // Interrupt Enable Register

//GPIO Register
#define GP0CON *((long*)0x40020000) // GPIO Port 0 Configuration
#define GP0OEN *((long*)0x40020004) // GPIO Port 0 Output Enable
#define GP0IEN *((long*)0x4002000C) // GPIO Port 0 Input Enable

main()
{
COMCTL = 0x0; //'UART enable

GP0CON = 0xA000; / PIN 0.7 and PIN 0.6 as Rx e Tx
GP0OEN |= 0x40; // pin 0.6 (Tx) as Output
GP0IEN |= 0x80; //pin 0.7 (Rx) as Input


COMIEN = 0x3A; // interrupts disable

//Baud Rate = 9600
COMDIV = 0x11; //COMDIV =17
COMFBR = 0x9883; // FBEN=1, M=3 e N=131

//start communication
COMTX = 0x1;
while(!(COMLSR && 0x60)); //wait till COMTX and Transmit Shift Register are empty in order to avoid overwrite
COMTX = 0x1;
while(!(COMLSR && 0x60));
COMTX = 0x1;
while(!(COMLSR && 0x60));
COMTX = 0x1;
while(!(COMLSR && 0x60));
COMTX = 0x1;
while(!(COMLSR && 0x60));
}

I am using Termite 3.2 as communication tool (I tried also UART_Terminal_NET_4.5) but the riceved word is always the same showed in the attached screenshot. 

What is wrong?

PS: obviously I tried to change the value of the sending bits and I checked the right configuration of 5 bit word, 1 stop bit, none parity check and Baud Rate for Termite. 

Hi,

I was wondering if there was a way that I could use this chip to create a high frequency pulse for some specified period of time. In Sweep mode I can create these pulses by switching the amplitude from 0 to 1 and back, but this creates repeated pulses. I would just like to be able to create a single pulse.

I would also like to be able to trigger this pulse off of an external source, but first the pulse creation is required.

I am doing quantum research and need different length pulses to excite quantum 2-state systems

Thanks!