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January 2, 2017, 4:22 am
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Building library error in DAQ2

January 12, 2017, 2:22 pm
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Hi,

 

While I build library in hdl_2016_r2, I can't finish in these 2 IPs. 

axi_adxcvr, util_adxcvr

Other all library is done successfully by using .tcl

But somehow these 2 folders kept Running forever.(I wait more than an hour.)

 

Here is the message. Please check what is wrong.

Thanks, Harold

 

-------------------------------

source ./axi_adxcvr_ip.tcl
# source ../../scripts/adi_env.tcl
## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]]
## set ad_phdl_dir $ad_hdl_dir
## if [info exists ::env(ADI_HDL_DIR)] {
## set ad_hdl_dir $::env(ADI_HDL_DIR)
## }
## if [info exists ::env(ADI_PHDL_DIR)] {
## set ad_phdl_dir $::env(ADI_PHDL_DIR)
## }
# source $ad_hdl_dir/library/scripts/adi_ip.tcl
## if {![info exists REQUIRED_VIVADO_VERSION]} {
## set REQUIRED_VIVADO_VERSION "2016.2"
## }
## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} {
## set IGNORE_VERSION_CHECK 1
## } elseif {![info exists IGNORE_VERSION_CHECK]} {
## set IGNORE_VERSION_CHECK 0
## }
## proc adi_ip_create {ip_name} {
##
## global ad_hdl_dir
## global ad_phdl_dir
## global REQUIRED_VIVADO_VERSION
## global IGNORE_VERSION_CHECK
##
## if {!$IGNORE_VERSION_CHECK && [string compare [version -short] $REQUIRED_VIVADO_VERSION] != 0} {
## return -code error [format "ERROR: This library requires Vivado %s." $REQUIRED_VIVADO_VERSION]
## }
##
## create_project $ip_name . -force
##
## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO
## set_msg_config -id {IP_Flow 19-2999} -new_severity INFO
## set_msg_config -id {IP_Flow 19-1654} -new_severity INFO
## set_msg_config -id {IP_Flow 19-459} -new_severity INFO
##
## set lib_dirs $ad_hdl_dir/library
## if {$ad_hdl_dir ne $ad_phdl_dir} {
## lappend lib_dirs $ad_phdl_dir/library
## }
##
## set_property ip_repo_paths $lib_dirs [current_fileset]
## update_ip_catalog
##
## set proj_dir [get_property directory [current_project]]
## set proj_name [get_projects $ip_name]
## }
## proc adi_ip_files {ip_name ip_files} {
##
## set proj_fileset [get_filesets sources_1]
## add_files -norecurse -scan_for_includes -fileset $proj_fileset $ip_files
## set_property "top" "$ip_name" $proj_fileset
## }
## proc adi_ip_constraints {ip_name ip_constr_files {processing_order late}} {
##
## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}]
## foreach f_name $ip_constr_files {
## ipx::add_file $f_name $proj_filegroup
## set_property type xdc [ipx::get_files $f_name -of_objects $proj_filegroup]
## set_property processing_order $processing_order [ipx::get_files $f_name -of_objects $proj_filegroup]
## }
## }
## proc adi_ip_ttcl {ip_name ip_constr_files} {
##
## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}]
## set f [ipx::add_file $ip_constr_files $proj_filegroup]
## set_property -dict [list \
## type ttcl \
## ] $f
## }
## proc adi_ip_bd {ip_name ip_bd_files} {
## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]]
## if {$proj_filegroup == {}} {
## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]]
## }
## set f [ipx::add_file $ip_bd_files $proj_filegroup]
## set_property -dict [list \
## type tclSource \
## ] $f
## }
## proc adi_ip_properties {ip_name} {
##
## adi_ip_properties_lite $ip_name
##
## ipx::infer_bus_interface {\
## s_axi_awvalid \
## s_axi_awaddr \
## s_axi_awprot \
## s_axi_awready \
## s_axi_wvalid \
## s_axi_wdata \
## s_axi_wstrb \
## s_axi_wready \
## s_axi_bvalid \
## s_axi_bresp \
## s_axi_bready \
## s_axi_arvalid \
## s_axi_araddr \
## s_axi_arprot \
## s_axi_arready \
## s_axi_rvalid \
## s_axi_rdata \
## s_axi_rresp \
## s_axi_rready} \
## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
##
## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
## ipx::add_memory_map {s_axi} [ipx::current_core]
## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]]
## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]
## set_property range {65536} [ipx::get_address_blocks axi_lite \
## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]]
## ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces s_axi_aclk \
## -of_objects [ipx::current_core]]
## set_property value s_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \
## -of_objects [ipx::get_bus_interfaces s_axi_aclk \
## -of_objects [ipx::current_core]]]
## }
## proc adi_ip_infer_interfaces {ip_name} {
##
## ipx::infer_bus_interfaces xilinx.com:interface:clock_rtl:1.0 [ipx::current_core]
## ipx::infer_bus_interfaces xilinx.com:interface:reset_rtl:1.0 [ipx::current_core]
## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core]
## }
## proc adi_ip_properties_lite {ip_name} {
##
## ipx::package_project -root_dir . \
## -vendor analog.com \
## -library user \
## -taxonomy /Analog_Devices
##
## set_property vendor_display_name {Analog Devices} [ipx::current_core]
## set_property company_url {www.analog.com} [ipx::current_core]
##
## set_property supported_families {\
## virtex7 Production
## qvirtex7 Production
## kintex7 Production
## kintex7l Production
## qkintex7 Production
## qkintex7l Production
## artix7 Production
## artix7l Production
## aartix7 Production
## qartix7 Production
## zynq Production
## qzynq Production
## azynq Production
## virtexu Production
## kintexuplus Production
## zynquplus Production
## kintexu Production
## virtex7 Beta
## qvirtex7 Beta
## kintex7 Beta
## kintex7l Beta
## qkintex7 Beta
## qkintex7l Beta
## artix7 Beta
## artix7l Beta
## aartix7 Beta
## qartix7 Beta
## zynq Beta
## qzynq Beta
## azynq Beta
## virtexu Beta
## virtexuplus Beta
## kintexuplus Beta
## zynquplus Beta
## kintexu Beta}\
## [ipx::current_core]
##
## ipx::remove_all_bus_interface -quiet [ipx::current_core]
## ipx::remove_all_address_block -quiet [ipx::get_memory_maps * -of_objects [ipx::current_core]]
## }
## proc adi_set_ports_dependency {port_prefix dependency} {
## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] {
## set_property ENABLEMENT_DEPENDENCY $dependency $port
## }
## }
## proc adi_set_bus_dependency {bus prefix dependency} {
## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]]
## adi_set_ports_dependency $prefix $dependency
## }
## proc adi_add_port_map {bus phys logic} {
## set map [ipx::add_port_map $phys $bus]
## set_property "PHYSICAL_NAME" $phys $map
## set_property "LOGICAL_NAME" $logic $map
## }
## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} {
## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
##
## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
## set_property "BUS_TYPE_VLNV" $bus_type $bus
## set_property "INTERFACE_MODE" $mode $bus
##
## foreach port_map $port_maps {
## adi_add_port_map $bus {*}$port_map
## }
## }
## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} {
## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name]
## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"]
## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]]
## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf
## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf
## set_property display_name $clock_inf_name $clock_inf
## set clock_map [ipx::add_port_map "CLK" $clock_inf]
## set_property physical_name $clock_signal_name $clock_map
##
## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf]
## set_property value $bus_inf_name $assoc_busif
##
## if { $reset_signal_name != "" } {
## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf]
## set_property value $reset_signal_name $assoc_reset
##
## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"]
## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]]
## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf
## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf
## set_property display_name $reset_inf_name $reset_inf
## set_property interface_mode $reset_signal_mode $reset_inf
## set reset_map [ipx::add_port_map "RST" $reset_inf]
## set_property physical_name $reset_signal_name $reset_map
##
## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf]
## set_property value "ACTIVE_LOW" $reset_polarity
## }
## }
## proc adi_ip_add_core_dependencies {vlnvs} {
## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] {
## foreach vlnv $vlnvs {
## ipx::add_subcore $vlnv $file_group
## }
## }
## }
## proc adi_if_define {name} {
##
## ipx::create_abstraction_definition ADI user ${name}_rtl 1.0
## ipx::create_bus_definition ADI user $name 1.0
##
## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs]
## set_property xml_file_name ${name}.xml [ipx::current_busdef]
## set_property bus_type_vlnv ADI:user:${name}:1.0 [ipx::current_busabs]
##
## ipx::save_abstraction_definition [ipx::current_busabs]
## ipx::save_bus_definition [ipx::current_busdef]
## }
## proc adi_if_ports {dir width name {type none}} {
##
## ipx::add_bus_abstraction_port $name [ipx::current_busabs]
## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]]
## set_property master_presence required $m_intf
## set_property slave_presence required $m_intf
## set_property master_width $width $m_intf
## set_property slave_width $width $m_intf
##
## set m_dir "in"
## set s_dir "out"
## if {$dir eq "output"} {
## set m_dir "out"
## set s_dir "in"
## }
##
## set_property master_direction $m_dir $m_intf
## set_property slave_direction $s_dir $m_intf
##
## if {$type ne "none"} {
## set_property is_${type} true $m_intf
## }
##
## ipx::save_bus_definition [ipx::current_busdef]
## ipx::save_abstraction_definition [ipx::current_busabs]
## }
## proc adi_if_infer_bus {if_name mode name maps} {
##
## ipx::add_bus_interface $name [ipx::current_core]
## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]]
## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if
## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if
## set_property interface_mode $mode $m_bus_if
##
## foreach map $maps {
## set m_maps [regexp -all -inline {\S+} $map]
## lassign $m_maps p_name p_map
## ipx::add_port_map $p_name $m_bus_if
## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if]
## }
## }
# adi_ip_create axi_adxcvr
INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter.
Current project path is 'C:/Users/hjang/Documents/Xilinx/ADI/hdl-hdl_2016_r2/hdl-hdl_2016_r2/library/xilinx/axi_adxcvr'
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2016.2/data/ip'.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Users/hjang/Documents/Xilinx/ADI/hdl-hdl_2016_r2/hdl-hdl_2016_r2/library'.
INFO: [IP_Flow 19-3656] If you move the project, the path for repository 'c:/Users/hjang/Documents/Xilinx/ADI/hdl-hdl_2016_r2/hdl-hdl_2016_r2/library' may become invalid. A better location for the repostory would be in a path adjacent to the project. (Current project location is 'c:/Users/hjang/Documents/Xilinx/ADI/hdl-hdl_2016_r2/hdl-hdl_2016_r2/library/xilinx/axi_adxcvr'.)
# adi_ip_files axi_adxcvr [list \
# "$ad_hdl_dir/library/common/up_axi.v" \
# "axi_adxcvr_es.v" \
# "axi_adxcvr_up.v" \
# "axi_adxcvr_mdrp.v" \
# "axi_adxcvr_mstatus.v" \
# "axi_adxcvr.v" ]
# adi_ip_properties_lite axi_adxcvr
INFO: [IP_Flow 19-459] IP file 'C:/Users/hjang/Documents/Xilinx/ADI/hdl-hdl_2016_r2/hdl-hdl_2016_r2/library/common/up_axi.v' appears to be outside of the project area 'C:/Users/hjang/Documents/Xilinx/ADI/hdl-hdl_2016_r2/hdl-hdl_2016_r2/library/xilinx/axi_adxcvr'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'C:/Users/hjang/Documents/Xilinx/ADI/hdl-hdl_2016_r2/hdl-hdl_2016_r2/library/common/up_axi.v' appears to be outside of the project area 'C:/Users/hjang/Documents/Xilinx/ADI/hdl-hdl_2016_r2/hdl-hdl_2016_r2/library/xilinx/axi_adxcvr'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-2228] Inferred bus interface 'm_axi' of definition 'ADI:user:if_xcvr_cm:1.0'.
INFO: [IP_Flow 19-2228] Inferred bus interface 's_axi' of definition 'ADI:user:if_xcvr_cm:1.0'.
INFO: [IP_Flow 19-2999] Will not infer bus interface "m_axi" for "xilinx.com:interface:aximm:1.0". The interface exists with different type "ADI:user:if_xcvr_cm:1.0".
INFO: [IP_Flow 19-2999] Will not infer bus interface "s_axi" for "xilinx.com:interface:aximm:1.0". The interface exists with different type "ADI:user:if_xcvr_cm:1.0".
INFO: [IP_Flow 19-4753] Inferred signal 'reset' from port 'axi_aresetn' as interface 'axi_aresetn'.
INFO: [IP_Flow 19-4728] Bus Interface 'axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4753] Inferred signal 'reset' from port 'up_pll_rst' as interface 'up_pll_rst'.
INFO: [IP_Flow 19-4753] Inferred signal 'clock' from port 'axi_clk' as interface 'axi_clk'.
INFO: [IP_Flow 19-4728] Bus Interface 'axi_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'axi_aresetn'.
# ipx::remove_all_bus_interface [ipx::current_core]
# set_property driver_value 0 [ipx::get_ports -filter "direction==in" -of_objects [ipx::current_core]]
# ipx::infer_bus_interface {\
# s_axi_awvalid \
# s_axi_awaddr \
# s_axi_awprot \
# s_axi_awready \
# s_axi_wvalid \
# s_axi_wdata \
# s_axi_wstrb \
# s_axi_wready \
# s_axi_bvalid \
# s_axi_bresp \
# s_axi_bready \
# s_axi_arvalid \
# s_axi_araddr \
# s_axi_arprot \
# s_axi_arready \
# s_axi_rvalid \
# s_axi_rdata \
# s_axi_rresp \
# s_axi_rready} \
# xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
# ipx::infer_bus_interface {\
# m_axi_awvalid \
# m_axi_awaddr \
# m_axi_awprot \
# m_axi_awready \
# m_axi_wvalid \
# m_axi_wdata \
# m_axi_wstrb \
# m_axi_wready \
# m_axi_bvalid \
# m_axi_bresp \
# m_axi_bready \
# m_axi_arvalid \
# m_axi_araddr \
# m_axi_arprot \
# m_axi_arready \
# m_axi_rvalid \
# m_axi_rdata \
# m_axi_rresp \
# m_axi_rready} \
# xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
# ipx::infer_bus_interface axi_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
INFO: [IP_Flow 19-4753] Inferred signal 'clock' from port 'axi_clk' as interface 'axi_clk'.
INFO: [IP_Flow 19-4728] Bus Interface 'axi_clk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi:m_axi'.
# ipx::infer_bus_interface axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
INFO: [IP_Flow 19-4753] Inferred signal 'reset' from port 'axi_aresetn' as interface 'axi_aresetn'.
INFO: [IP_Flow 19-4728] Bus Interface 'axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4728] Bus Interface 'axi_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'axi_aresetn'.
# ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces axi_clk \
# -of_objects [ipx::current_core]]
# set_property value s_axi:m_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \
# -of_objects [ipx::get_bus_interfaces axi_clk \
# -of_objects [ipx::current_core]]]
# ipx::add_memory_map {s_axi} [ipx::current_core]
# set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]]
# ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]
# set_property range {4096} [ipx::get_address_blocks axi_lite \
# -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]]
# for {set n 0} {$n < 16} {incr n} {
#
# if {($n%4) == 0} {
# adi_if_infer_bus ADI:user:if_xcvr_cm master up_cm_${n} [list \
# "sel up_cm_sel_${n} "\
# "enb up_cm_enb_${n} "\
# "addr up_cm_addr_${n} "\
# "wr up_cm_wr_${n} "\
# "wdata up_cm_wdata_${n} "\
# "rdata up_cm_rdata_${n} "\
# "ready up_cm_ready_${n} "]
# }
#
# adi_if_infer_bus ADI:user:if_xcvr_cm master up_es_${n} [list \
# "sel up_es_sel_${n} "\
# "enb up_es_enb_${n} "\
# "addr up_es_addr_${n} "\
# "wr up_es_wr_${n} "\
# "wdata up_es_wdata_${n} "\
# "rdata up_es_rdata_${n} "\
# "ready up_es_ready_${n} "]
#
# adi_if_infer_bus ADI:user:if_xcvr_ch master up_ch_${n} [list \
# "pll_locked up_ch_pll_locked_${n} "\
# "rst up_ch_rst_${n} "\
# "user_ready up_ch_user_ready_${n} "\
# "rst_done up_ch_rst_done_${n} "\
# "lpm_dfe_n up_ch_lpm_dfe_n_${n} "\
# "rate up_ch_rate_${n} "\
# "sys_clk_sel up_ch_sys_clk_sel_${n} "\
# "out_clk_sel up_ch_out_clk_sel_${n} "\
# "sel up_ch_sel_${n} "\
# "enb up_ch_enb_${n} "\
# "addr up_ch_addr_${n} "\
# "wr up_ch_wr_${n} "\
# "wdata up_ch_wdata_${n} "\
# "rdata up_ch_rdata_${n} "\
# "ready up_ch_ready_${n} "]
#

↧
↧

FMCDAQ2 - ADC 5Gbps operation

December 19, 2016, 10:51 pm
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Hi,

 

I am trying to reduce the sample lane rate of FMCDAQ2 - AD9680 to 5Gbps.  The provided design works in full BW mode and it uses 4 lanes 10Gbps each.

 

My goal is to set the decimation to 2 and operate lanes 4x5Gbps.

 

So I have two things to do.

1) Program AD9680 for decimation by two at 1GSps

2) Modify the GT core settings and recompile the FPGA code.

 

 

1) In ad9680.c,  ad9680_setup() I commented one line and added commands to place an HB Filter in-line.

 

///*Original*/

//*************************************//

//ad9680_spi_write(slave_select, AD9680_REG_CHIP_DEC_RATIO, 0x00);// full sample rate (decimation = 1)

//*************************************//

 

/* Modified for 5Gbps operation */

//*************************************//

ad9680_spi_write(slave_select, AD9680_REG_CHIP_APP_MODE, 0x01);      // DDC0 ON

ad9680_spi_write(slave_select, AD9680_REG_CHIP_DEC_RATIO, 0x01);     // (decimation = 2)

ad9680_spi_write(slave_select, AD9680_REG_JESD_LANE_CONTROL, 0x10); 

ad9680_spi_write(slave_select, AD9680_REG_DDC0_CONTROL, 0x83 );      // DDC0 (complex mixer; 0 dB gain; variable IF; complex outputs; HB1 filter)

ad9680_spi_write(slave_select, AD9680_REG_DDC0_INPUT_SEL, 0x04 );    // (DDC I input = ADC Channel A; DDC Q input = ADC Channel B)

//*************************************//

2) Using the Xilinx 7 Series Transceiver Wizard I generated an IP with the following settings. (TX turned off)

                Reference Clock: 500MHz

                Lane Rate      : 5Gbps

                External Data Width : 40

                Internal Data Width : 40

               

                Looking at the settings from the wizard generated code I modified the axi_daq2_gt. With the following settings.

               

           Pma Rsv 0-7      0x001E7080

           Rx Cdr Cfg 0-7   0x03000023ff40200020

           Rx Out Div 0-7   2

                The other settings are left as is since they already match the wizard generated one.

               

                Qpll0 Cfg    "000011010000000000110000001" = 0x680181

                Qpll0 Fbdiv  "0000110000"                  => Div by 20

                Qpll0 Refclk Div 1

               

               

The resultant bit file does not work properly. That is:

 

QPLL0 Locks                  - verified by jesd204b_gt_txrx_status()

The lane Sync achieved - measured the SYNCB pin with oscilloscope

AD9680 is left in the ramp mode and "i_system_wrapper/system_i/axi_ad9680_fifo_dma_wdata[15:0]" data is probed by a debug probe. The received data is not a ramp!

 

 

Whereas programming the FPGA with the original ADI bit file but using the same SDK project discussed here uncommenting the original code, commenting the modifed code (described above) in ad9680.c, I can see a ramp.

 

Is there anything I miss?

↧

FMCOMMS1 + VC707, adc_capture fail

January 12, 2017, 5:21 am
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Hello,

Using VC707+FMCOMMS1, generated bit file, launched SDK and now try to run example main

 

But design fails on adc_capture function

     /* Wait until the current transfer is completed. */
     do{
          reg_val =Xil_In32(baddr + AXI_DMAC_REG_IRQ_PENDING);
     }
     while(reg_val !=(AXI_DMAC_IRQ_SOT | AXI_DMAC_IRQ_EOT));

no-OS/test.c at master · analogdevicesinc/no-OS · GitHub 

reg_val always 1

#define AXI_DMAC_IRQ_SOT                    (1 << 0) //1
#define AXI_DMAC_IRQ_EOT                    (1 << 1) //2

 

What may be the reason DMA transaction fails?

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MuMIMO ZC706+FMCOMMS5

January 13, 2017, 1:29 am
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Hello,

 

I've experienced with ZC706+FMCOMMS5 board with AD reference designs and now I want to use two of this kits.

 

What I need

1) Load two different signals to both board. It's clear, how to do

2) Sync RF parts from extended LO (it's also clear)

3) And now I want at one moment start transmission from both boards. How do I see this process

- First board (Master) in Zynq processor generate launch signal on GPIO pin, SMA socket

- This SMA signal goes to another board, where it connected to IRQ port of another Zynq processor (Slave)

- So when Slave recieve interrupt, it launches DMA transaction and Master launches DMA in a several ticks, after it generated launch signal.

 

Is it right way?

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How to Control AD9910 Eval software RAM?

February 2, 2017, 7:13 pm
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Single Tone Mode and DRG Mode work well.

but RAM Control mode not worked.

 

The default setting is the same as Single Tone and DRG. (Ext CLK, En Multi...)

 

1. I want to see 100MHz sine wave.

2. I want to see the frequency increase from 10MHz to 250MHz.

 

 

using ram control

 

How do I configure the GUI?

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AD9834 SIGN BIT OUT

February 7, 2017, 10:12 am
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Hello,

 

i am struggling getting an output on the SIGN BIT OUT Pin. Do I need a special initialization sequence?

If i replace the OPBITEN with MODE,  I get the triangular output as expected.

Mclk=75MHz

SIGN BIT OUT= only connected to an oscilloscope

 

 // Bits in the Control Register

 

 #define B28         0x2000    //DB13 28bit frequency register MSB,LSB in one command
 #define HLB         0x1000    //DB12 ignored because B28 == true
 #define FSEL        0x0800    //DB11 select FREQ0 or FREQ1 data
 #define PSEL        0x0400    //DB10 select PHASE0 or PHASE1 data
 #define PIN_SW      0x0200    //DB09 0=functions are controlled using control bits
 #define RESET       0x0100    //DB08 1=reset int registers to 0; set DAC to mid scale
 #define SLEEP1      0x0080    //DB07 disable MCLK, DAC value is hold
 #define SLEEP12     0x0040    //DB06 power down chip DAC
 #define OPBITEN     0x0020    //DB05 enable the SIGN_BIT_OUT pin
 #define SIGN_PIB    0x0010    //DB04 configure the SIGN_BIT_OUT
 #define DIV2        0x0008    //DB03 digital output/2
 #define MODE        0x0002    //DB01 1 = triangle output, 0 = sin output

 

         AD9834_config =B28 | RESET | OPBITEN;
         spi_Write(AD9834_config); //0x2100
         spi_Write(FREQ0_ADDR | 0x0001);
         spi_Write(PHASE0_ADDR);
         spi_Write(FREQ1_ADDR | 0x001);
         spi_Write(PHASE1_ADDR);
         AD9834_config &=~RESET;
         spi_Write(AD9834_config); //0x2000


         AD9834_SetFrequency(3000000L);

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AD9954: Pin Configuration

February 15, 2017, 5:10 am
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AD9954: Pin Configuration - I am doing the layout for DDS AD9954 but in my circuit, I do not need the comparator output. So  Should I leave the 3 pins of the comparator (pin 28, 30 & 31) floating? Please advise because datasheet does not recommend anything. Note: The comparator can be turned off the comparator powerdown  bit, CFR1<6>.

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Search

AD9957 Eval board AD9957PCBZ

February 14, 2017, 1:11 am
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Hi , 

Is it  possible   to recieve the CPLD firmware (EPM240T100C4)   U4, which was located on  this PCB.   (Аfter  some experiments  the   CPLD was damaged. ) Also  ,  is it  possible to  use  more   available  EPM240T100C5  instead EPM240T100C4 ?

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AD9959 LFM(down chirp)

February 14, 2017, 11:09 pm
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Hellow. I`m KIM.

 

I have a question about LFM using the AD9959.

I want to create a waveform such as an attached file.

After the frequency has changed from E0 to S0, can the LFM waveforms be repeated again?

Current status does not return to E0.

How can I return to E0?

Thank you for your response.

↧

Register configuration issues on the HMC764

February 21, 2017, 5:22 am
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Find a typical register configuration for integer division.
Now no matter how many of the registers of the N divider ，the vco are oscillating at around 7.5GHz.

Phase frequency is 10MHz and  reference input is 50MHz.

The following is my register configuration：

02h <= 5d(R divider is 5)

03h <=  770d(N divider is 770,expected RF out is 7.7GHz)

04h <= 0

05h <= 50894C

06h <= 703387

07h <= 4FA

08h <= 31DF

09h <= 900000

0Ah <= 0

0Bh <= 72

0Ch <= 0

0Dh <= A

 

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ADAU1761 no sound

February 13, 2017, 6:00 am
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Hi

 

I'm using it on my own board with ADAU1761 and MCU (STM32L476) configured as master. The idea is to play and record 22.05kHz audio.I made a simple schematic in SigmaStudio to check if ADAU1761 is working (see image below). Sine tone is generated and sent to DAC0 and DAC1 but there is no audio on the outputs. Using this presentation I managed to send SigmaStudio exported data via I2C to ADAU1761. LOUTP and LOUTN are connected to external speaker with amplifier (SSM2305), RHP and LHP are connected to headphone jack (I'm not using capless configuration). Clock source is MCLK from MCU, 5.647MHz (~256 x fs). I'm also using serial interface in full-duplex mode (I also tried to send sine tone though DIG0 and DIG1). PLL is set to: X = 1, R = 8 to get >41MHz clock, input master clock freq is 1024 x fs. I'm really confused with PLL and MCLK. I also used USBi to load SigmaStudio data, so I think it's not I2C fault. I attach full project from SigmaStudio.

 

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AD6676 SYSREF calculation

February 20, 2017, 8:52 am
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Hello,

 

I'm playing with synchronization of two AD6676 and I have a problem.

 

I did a calculation of SYSREF frequency and set it up for design. It seems like I have a delay in data streams between these two ADc - like 2~10 samples so synchronization doesn't work.

Everything (FPGA+both ADc) is feeded from same source ( HMC7044)

 

Can someone please check my SYSREF calculation before I dig deeper into the design looking for the problem (cables, jesd/ADc setting, sysref mode periodic/one-shot...)?

 

Calculations:

Fadc = 2949MHz, Fref= 245,76MHz , DEC = 12 (IQ_rate = 245,76MSPS)

lanes = 2, F = 2, K = 32, S = 1, 10/8bit encoding

 

frame clock FC = Fadc/DEC/S = 245,76MHz (or calculated as lane rate/ (10 x F) )

lane rate = 4915,2Mbps  (chosen as 20x to fit datasheet requirements, can be calculated as FC x F x 10)

LMFC = 7,68MHz = maximal SYSREF value (can be calculated as FC/K or as Fadc/(DEC x K x S) )

 

I tried 3,84MHz and 960kHz values with similar effect.

 

Thanks!

 

With kind regards,

Daniel

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Can I connect inputs on AD667 directly to digital outputs on Atmel SAM3X8E ARM Cortex-M3 CPU?

February 22, 2017, 12:12 pm
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I'd like to connect the 12 ea. digital input lines on one of your DAC AD667 chips directly to the digital output lines on an Atmel SAM3X8E ARM Cortex-M3 CPU. Will that work, or do I need to use some type of level-shifting to accommodate Atmel's 3.3V logic? Thank you. #JMLQ1 

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Dies of "AD9254" and "AD9254S"

February 19, 2017, 5:39 pm
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Dear Sir/Madam,

 

  I know that "AD9254" is a commercial grade ADC and "AD9254S" is a space grade ADC.

  My question is,  are the dies of AD9254 and AD9254Ssame or different?

 

THANKS!

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Search

AD5934 measurement

February 15, 2017, 7:00 am
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i am using big 8051 development board mcu c8051f040 . i am  interfacing ad5934 for impedence measurement . i have connected  RFB=220k and Z =220k want to measure but not getting  result  .please help me with example source code . i am micro  c compiler for 8051

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CGS on AD9371

February 22, 2017, 2:35 pm
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I have a customer, Vanteon, who is having trouble getting past the CGS state in the JESD interface when connecting the AD9371 with a Xilinx FPGA.

 

Note that they are trying to get the Tx side of the AD9371 running, so the FPGA is the JESD transmitter, and the AD9371 is the JESD receiver.

 

They are asserting the sync signal (sync = low) and they are seeing the K characters generated on the JESD lines from the FPGA. However, the sync line is not de-asserting itself.

 

This problem is identical to a problem I had with another customer recently when they were trying to use the AD9162 DAC. In that case, the problem was solved when the product line told us that there was a reserved bit in the 9162 reg map that actually needed to be set to one. Is it possible that this is the same problem? I think here at ADI, a lot of our JESD cores probably have a common origin.

 

If this reserved bit is not an issue, can you please give me a short list of possible problems that could lead to trouble getting out of the CGS phase in the JESD interface?

 

thanks,

 

Steve

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AD5260/5262 Vlogic power supply

December 15, 2016, 7:24 pm
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Hi all.

I have a question about Vlogic power supply.
Question : Does VL need to be always less than VDD?

Our customer are using VDD=5V, VL=5V nomaly. but sometime VL > VDD.


In D/S of AD5260 ”ABSOLUTE MAXIMUM RATINGS”

　　　　　VL to GND   0 V to +7 V

Since there is no correlation between VDD and VL, I understand that I have no problem.

However, despite similar absolute maximum ratings, the AD5263 has the following limitations.

"The logic supply voltage should always be less than or equal to VDD."


Is there any limitations on the AD5260 / AD5262?  There is no similar description in D/S.


Best regards
Hiroshi

 

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ad9361 more than two ip

February 20, 2017, 8:35 am
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I am trying to add 3 axi_ad9361 ip to my Picozed SDR SOM board and so far has been able to do only 2 based on FMCOMMS5 devicetree design, but not 3.

 

I made sure that hardware is ok as well as PL side to connect the SPI channels. Is there anything on the Linux Kernel rather than devicetree to be modified?

 

here is a snippet of my device tree:   -------> ad9361-phy-C@2 

 

spi@e0007000 {
compatible = "xlnx,zynq-spi-r1p6";
reg = <0xe0007000 0x1000>;
status = "okay";
interrupt-parent = <0x1>;@@@@@
interrupts = <0x0 0x31 0x4>;
clocks = <0x2 0x1a 0x2 0x23>;
clock-names = "ref_clk", "pclk";
#address-cells = <0x1>;
#size-cells = <0x0>;

ad9361-phy@0 {
#address-cells = <0x1>;
#size-cells = <0x0>;
#clock-cells = <0x1>;
compatible = "ad9361-2x";
reg = <0x0>;
spi-cpha;
spi-max-frequency = <0x989680>;
clocks = <0x5 0x0>;
clock-names = "ad9361_ext_refclk";
clock-output-names = "rx_sampl_clk", "tx_sampl_clk";
adi,digital-interface-tune-skip-mode = <0x0>;
adi,pp-tx-swap-enable;
adi,pp-rx-swap-enable;
adi,rx-frame-pulse-mode-enable;
adi,lvds-mode-enable;
adi,lvds-bias-mV = <0x96>;
adi,lvds-rx-onchip-termination-enable;
adi,rx-data-delay = <0x4>;
adi,tx-fb-clock-delay = <0x7>;
adi,xo-disable-use-ext-refclk-enable;
adi,2rx-2tx-mode-enable;
adi,frequency-division-duplex-mode-enable;
adi,rx-rf-port-input-select = <0x0>;
adi,tx-rf-port-input-select = <0x0>;
adi,tx-attenuation-mdB = <0x2710>;
adi,rf-rx-bandwidth-hz = <0x4c4b40>;
adi,rf-tx-bandwidth-hz = <0x4c4b40>;
adi,rx-synthesizer-frequency-hz = <0x0 0x6df87740>;
adi,tx-synthesizer-frequency-hz = <0x0 0x6df87740>;
adi,rx-path-clock-frequencies = <0x4c4b4000 0x9896800 0x4c4b400 0x2625a00 0x1312d00 0x1312d00>;
adi,tx-path-clock-frequencies = <0x4c4b4000 0x9896800 0x4c4b400 0x2625a00 0x1312d00 0x1312d00>;
adi,gc-rx1-mode = <0x0>;
adi,gc-rx2-mode = <0x0>;
adi,gc-adc-ovr-sample-size = <0x4>;
adi,gc-adc-small-overload-thresh = <0x2f>;
adi,gc-adc-large-overload-thresh = <0x3a>;
adi,gc-lmt-overload-high-thresh = <0x320>;
adi,gc-lmt-overload-low-thresh = <0x2c0>;
adi,gc-dec-pow-measurement-duration = <0x2000>;
adi,gc-low-power-thresh = <0x18>;
adi,mgc-inc-gain-step = <0x2>;
adi,mgc-dec-gain-step = <0x2>;
adi,mgc-split-table-ctrl-inp-gain-mode = <0x0>;
adi,agc-attack-delay-extra-margin-us = <0x1>;
adi,agc-outer-thresh-high = <0x5>;
adi,agc-outer-thresh-high-dec-steps = <0x2>;
adi,agc-inner-thresh-high = <0xa>;
adi,agc-inner-thresh-high-dec-steps = <0x1>;
adi,agc-inner-thresh-low = <0xc>;
adi,agc-inner-thresh-low-inc-steps = <0x1>;
adi,agc-outer-thresh-low = <0x12>;
adi,agc-outer-thresh-low-inc-steps = <0x2>;
adi,agc-adc-small-overload-exceed-counter = <0xa>;
adi,agc-adc-large-overload-exceed-counter = <0xa>;
adi,agc-adc-large-overload-inc-steps = <0x2>;
adi,agc-lmt-overload-large-exceed-counter = <0xa>;
adi,agc-lmt-overload-small-exceed-counter = <0xa>;
adi,agc-lmt-overload-large-inc-steps = <0x2>;
adi,agc-gain-update-interval-us = <0x3e8>;
adi,fagc-dec-pow-measurement-duration = <0x40>;
adi,fagc-lp-thresh-increment-steps = <0x1>;
adi,fagc-lp-thresh-increment-time = <0x5>;
adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x8>;
adi,fagc-final-overrange-count = <0x3>;
adi,fagc-gain-index-type-after-exit-rx-mode = <0x0>;
adi,fagc-lmt-final-settling-steps = <0x1>;
adi,fagc-lock-level = <0xa>;
adi,fagc-lock-level-gain-increase-upper-limit = <0x5>;
adi,fagc-lock-level-lmt-gain-increase-enable;
adi,fagc-lpf-final-settling-steps = <0x1>;
adi,fagc-optimized-gain-offset = <0x5>;
adi,fagc-power-measurement-duration-in-state5 = <0x40>;
adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable;
adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0xa>;
adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable;
adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x0>;
adi,fagc-rst-gla-large-adc-overload-enable;
adi,fagc-rst-gla-large-lmt-overload-enable;
adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0xa>;
adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable;
adi,fagc-state-wait-time-ns = <0x104>;
adi,fagc-use-last-lock-level-for-set-gain-enable;
adi,rssi-restart-mode = <0x3>;
adi,rssi-delay = <0x1>;
adi,rssi-wait = <0x1>;
adi,rssi-duration = <0x3e8>;
adi,ctrl-outs-index = <0x0>;
adi,ctrl-outs-enable-mask = <0xff>;
adi,temp-sense-measurement-interval-ms = <0x3e8>;
adi,temp-sense-offset-signed = <0xce>;
adi,temp-sense-periodic-measurement-enable;
adi,aux-dac-manual-mode-enable;
adi,aux-dac1-default-value-mV = <0x0>;
adi,aux-dac1-rx-delay-us = <0x0>;
adi,aux-dac1-tx-delay-us = <0x0>;
adi,aux-dac2-default-value-mV = <0x0>;
adi,aux-dac2-rx-delay-us = <0x0>;
adi,aux-dac2-tx-delay-us = <0x0>;
en_agc-gpios = <0x6 0x62 0x0>;
sync-gpios = <0x6 0x63 0x0>;
reset-gpios = <0x6 0x64 0x0>;
enable-gpios = <0x6 0x65 0x0>;
txnrx-gpios = <0x6 0x66 0x0>;
linux,phandle = <0xe>;
phandle = <0xe>;
};

ad9361-phy-B@1 {
#address-cells = <0x1>;
#size-cells = <0x0>;
#clock-cells = <0x1>;
compatible = "ad9361";
reg = <0x1>;
spi-cpha;
spi-max-frequency = <0x989680>;
clocks = <0x5>;
clock-names = "ad9361_ext_refclk";
clock-output-names = "rx_sampl_clk", "tx_sampl_clk";
adi,digital-interface-tune-skip-mode = <0x2>;
adi,pp-tx-swap-enable;
adi,pp-rx-swap-enable;
adi,rx-frame-pulse-mode-enable;
adi,lvds-mode-enable;
adi,lvds-bias-mV = <0x96>;
adi,lvds-rx-onchip-termination-enable;
adi,rx-data-clock-delay = <0x0>;
adi,rx-data-delay = <0x4>;
adi,tx-fb-clock-delay = <0x7>;
adi,tx-data-delay = <0x0>;
adi,xo-disable-use-ext-refclk-enable = <0x1>;
adi,2rx-2tx-mode-enable;
adi,frequency-division-duplex-mode-enable;
adi,rx1-rx2-phase-inversion-enable;
adi,rx-rf-port-input-select = <0x0>;
adi,tx-rf-port-input-select = <0x0>;
adi,tx-attenuation-mdB = <0x2710>;
adi,rf-rx-bandwidth-hz = <0x4c4b40>;
adi,rf-tx-bandwidth-hz = <0x4c4b40>;
adi,rx-synthesizer-frequency-hz = <0x0 0x6df87740>;
adi,tx-synthesizer-frequency-hz = <0x0 0x6df87740>;
adi,rx-path-clock-frequencies = <0x4c4b4000 0x9896800 0x4c4b400 0x2625a00 0x1312d00 0x1312d00>;
adi,tx-path-clock-frequencies = <0x4c4b4000 0x9896800 0x4c4b400 0x2625a00 0x1312d00 0x1312d00>;
adi,gc-rx1-mode = <0x0>;
adi,gc-rx2-mode = <0x0>;
adi,gc-adc-ovr-sample-size = <0x4>;
adi,gc-adc-small-overload-thresh = <0x2f>;
adi,gc-adc-large-overload-thresh = <0x3a>;
adi,gc-lmt-overload-high-thresh = <0x320>;
adi,gc-lmt-overload-low-thresh = <0x2c0>;
adi,gc-dec-pow-measurement-duration = <0x2000>;
adi,gc-low-power-thresh = <0x18>;
adi,mgc-inc-gain-step = <0x2>;
adi,mgc-dec-gain-step = <0x2>;
adi,mgc-split-table-ctrl-inp-gain-mode = <0x0>;
adi,agc-attack-delay-extra-margin-us = <0x1>;
adi,agc-outer-thresh-high = <0x5>;
adi,agc-outer-thresh-high-dec-steps = <0x2>;
adi,agc-inner-thresh-high = <0xa>;
adi,agc-inner-thresh-high-dec-steps = <0x1>;
adi,agc-inner-thresh-low = <0xc>;
adi,agc-inner-thresh-low-inc-steps = <0x1>;
adi,agc-outer-thresh-low = <0x12>;
adi,agc-outer-thresh-low-inc-steps = <0x2>;
adi,agc-adc-small-overload-exceed-counter = <0xa>;
adi,agc-adc-large-overload-exceed-counter = <0xa>;
adi,agc-adc-large-overload-inc-steps = <0x2>;
adi,agc-lmt-overload-large-exceed-counter = <0xa>;
adi,agc-lmt-overload-small-exceed-counter = <0xa>;
adi,agc-lmt-overload-large-inc-steps = <0x2>;
adi,agc-gain-update-interval-us = <0x3e8>;
adi,fagc-dec-pow-measurement-duration = <0x40>;
adi,fagc-lp-thresh-increment-steps = <0x1>;
adi,fagc-lp-thresh-increment-time = <0x5>;
adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x8>;
adi,fagc-final-overrange-count = <0x3>;
adi,fagc-gain-index-type-after-exit-rx-mode = <0x0>;
adi,fagc-lmt-final-settling-steps = <0x1>;
adi,fagc-lock-level = <0xa>;
adi,fagc-lock-level-gain-increase-upper-limit = <0x5>;
adi,fagc-lock-level-lmt-gain-increase-enable;
adi,fagc-lpf-final-settling-steps = <0x1>;
adi,fagc-optimized-gain-offset = <0x5>;
adi,fagc-power-measurement-duration-in-state5 = <0x40>;
adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable;
adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0xa>;
adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable;
adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x0>;
adi,fagc-rst-gla-large-adc-overload-enable;
adi,fagc-rst-gla-large-lmt-overload-enable;
adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0xa>;
adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable;
adi,fagc-state-wait-time-ns = <0x104>;
adi,fagc-use-last-lock-level-for-set-gain-enable;
adi,rssi-restart-mode = <0x3>;
adi,rssi-delay = <0x1>;
adi,rssi-wait = <0x1>;
adi,rssi-duration = <0x3e8>;
adi,ctrl-outs-index = <0x0>;
adi,ctrl-outs-enable-mask = <0xff>;
adi,temp-sense-measurement-interval-ms = <0x3e8>;
adi,temp-sense-offset-signed = <0xce>;
adi,temp-sense-periodic-measurement-enable;
adi,aux-dac-manual-mode-enable;
adi,aux-dac1-default-value-mV = <0x0>;
adi,aux-dac1-rx-delay-us = <0x0>;
adi,aux-dac1-tx-delay-us = <0x0>;
adi,aux-dac2-default-value-mV = <0x0>;
adi,aux-dac2-rx-delay-us = <0x0>;
adi,aux-dac2-tx-delay-us = <0x0>;
en_agc-gpios = <0x6 0x53 0x0>;
sync-gpios = <0x6 0x54 0x0>;
reset-gpios = <0x6 0x55 0x0>;
enable-gpios = <0x6 0x68 0x0>;
txnrx-gpios = <0x6 0x67 0x0>;
linux,phandle = <0x10>;
phandle = <0x10>;
};

ad9361-phy-C@2 {
#address-cells = <0x1>;
#size-cells = <0x0>;
#clock-cells = <0x1>;
compatible = "ad9361";
reg = <0x2>;
spi-cpha;
spi-max-frequency = <0x989680>;
clocks = <0x5>;
clock-names = "ad9361_ext_refclk";
clock-output-names = "rx_sampl_clk", "tx_sampl_clk";
adi,pp-tx-swap-enable;
adi,pp-rx-swap-enable;
adi,rx-frame-pulse-mode-enable;
adi,lvds-mode-enable;
adi,lvds-bias-mV = <0x96>;
adi,lvds-rx-onchip-termination-enable;
adi,rx-data-clock-delay = <0x0>;
adi,rx-data-delay = <0x4>;
adi,tx-fb-clock-delay = <0x7>;
adi,tx-data-delay = <0x0>;
adi,xo-disable-use-ext-refclk-enable = <0x1>;
adi,2rx-2tx-mode-enable;
adi,frequency-division-duplex-mode-enable;
adi,rx1-rx2-phase-inversion-enable;
adi,rx-rf-port-input-select = <0x0>;
adi,tx-rf-port-input-select = <0x0>;
adi,tx-attenuation-mdB = <0x2710>;
adi,rf-rx-bandwidth-hz = <0xf42400>;
adi,rf-tx-bandwidth-hz = <0xf42400>;
adi,rx-synthesizer-frequency-hz = <0x0 0x6df87740>;
adi,tx-synthesizer-frequency-hz = <0x0 0x6df87740>;
adi,rx-path-clock-frequencies = <0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;
adi,tx-path-clock-frequencies = <0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;
adi,gc-rx1-mode = <0x0>;
adi,gc-rx2-mode = <0x0>;
adi,gc-adc-ovr-sample-size = <0x4>;
adi,gc-adc-small-overload-thresh = <0x2f>;
adi,gc-adc-large-overload-thresh = <0x3a>;
adi,gc-lmt-overload-high-thresh = <0x320>;
adi,gc-lmt-overload-low-thresh = <0x2c0>;
adi,gc-dec-pow-measurement-duration = <0x2000>;
adi,gc-low-power-thresh = <0x18>;
adi,mgc-inc-gain-step = <0x2>;
adi,mgc-dec-gain-step = <0x2>;
adi,mgc-split-table-ctrl-inp-gain-mode = <0x0>;
adi,agc-attack-delay-extra-margin-us = <0x1>;
adi,agc-outer-thresh-high = <0x5>;
adi,agc-outer-thresh-high-dec-steps = <0x2>;
adi,agc-inner-thresh-high = <0xa>;
adi,agc-inner-thresh-high-dec-steps = <0x1>;
adi,agc-inner-thresh-low = <0xc>;
adi,agc-inner-thresh-low-inc-steps = <0x1>;
adi,agc-outer-thresh-low = <0x12>;
adi,agc-outer-thresh-low-inc-steps = <0x2>;
adi,agc-adc-small-overload-exceed-counter = <0xa>;
adi,agc-adc-large-overload-exceed-counter = <0xa>;
adi,agc-adc-large-overload-inc-steps = <0x2>;
adi,agc-lmt-overload-large-exceed-counter = <0xa>;
adi,agc-lmt-overload-small-exceed-counter = <0xa>;
adi,agc-lmt-overload-large-inc-steps = <0x2>;
adi,agc-gain-update-interval-us = <0x3e8>;
adi,fagc-dec-pow-measurement-duration = <0x40>;
adi,fagc-lp-thresh-increment-steps = <0x1>;
adi,fagc-lp-thresh-increment-time = <0x5>;
adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x8>;
adi,fagc-final-overrange-count = <0x3>;
adi,fagc-gain-index-type-after-exit-rx-mode = <0x0>;
adi,fagc-lmt-final-settling-steps = <0x1>;
adi,fagc-lock-level = <0xa>;
adi,fagc-lock-level-gain-increase-upper-limit = <0x5>;
adi,fagc-lock-level-lmt-gain-increase-enable;
adi,fagc-lpf-final-settling-steps = <0x1>;
adi,fagc-optimized-gain-offset = <0x5>;
adi,fagc-power-measurement-duration-in-state5 = <0x40>;
adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable;
adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0xa>;
adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable;
adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x0>;
adi,fagc-rst-gla-large-adc-overload-enable;
adi,fagc-rst-gla-large-lmt-overload-enable;
adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0xa>;
adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable;
adi,fagc-state-wait-time-ns = <0x104>;
adi,fagc-use-last-lock-level-for-set-gain-enable;
adi,rssi-restart-mode = <0x3>;
adi,rssi-delay = <0x1>;
adi,rssi-wait = <0x1>;
adi,rssi-duration = <0x3e8>;
adi,ctrl-outs-index = <0x0>;
adi,ctrl-outs-enable-mask = <0xff>;
adi,temp-sense-measurement-interval-ms = <0x3e8>;
adi,temp-sense-offset-signed = <0xce>;
adi,temp-sense-periodic-measurement-enable;
adi,aux-dac-manual-mode-enable;
adi,aux-dac1-default-value-mV = <0x0>;
adi,aux-dac1-rx-delay-us = <0x0>;
adi,aux-dac1-tx-delay-us = <0x0>;
adi,aux-dac2-default-value-mV = <0x0>;
adi,aux-dac2-rx-delay-us = <0x0>;
adi,aux-dac2-tx-delay-us = <0x0>;
en_agc-gpios = <0x6 0x6b 0x0>;
reset-gpios = <0x6 0x63 0x0>;
linux,phandle = <0x11>;
phandle = <0x11>;
};
};

 larsc mhennerich

↧

(ADV7511W)Can ADV7511W change the format to RGB from YUV422?

February 21, 2017, 3:35 am
$
0
0

Hi !

 

Our customer are using ADV7511W for the ADAS R&D.

They are thinking to input RGB data to ADV7511W.

The question is this.

Q1)

Can ADV7511W change the format to RGB444 from YUV422?

Q2)

If it can , do you have a script for this?

 

Best regards.

Kawa 

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