I see in several entries here people discussing the USB/HID example.  I must be blind, because I cannot find it.  Could someone please tell me where it is?

Note that we do NOT want to use Micrium, bare metal only.

Thanks,

-Erik

Are any S parameters available (w/ or w/o hybrid) for image reject mixer HMC8191?

Hi team,

I am working on a project where I need to interface AD7888 with a micro-controller (I am using MSP430F6736). The MCU has a SPI interface. Could anyone help me out with the steps from where I need to start and what steps do I need to follow?

Thank you.

Hello everyone, I have a question that is more or less described in the title.

I am a software engineer, that like tinkering with devices and stuff, and sometimes I do have ideas of something that either doesn't exists at all, or nobody produces it yet. Right now I have in mind a small DYI audio project that I personally want to use and after ton of research I've found out great AD SigmaDSP processor family that perfectly fits to what I want to assemble.

The issue is that I'm not a hardware engineer, but software engineer. So from all the docs and specs I see that this thing fits me perfect, and I would gladly order some third party freelancer to hardware design a board based on SigmaDSP if I would be totally sure that it all is going to work out. And to be sure I need the evaluation board to test things and firmware. And all of them which fits my needs are 200$, which is way over DYI project budget just to try it out!

So, is there any way to get an eval board except buying it? Rent? Buy used cheaper? Engineering sample on sale? Some enthusiast program of AD itself? I don't have much to offer, but since I'm pretty into programming ARM microcomputers I write articles and reviews from time to time on various IT resources and can make a review of the board... Writing an article about DYI project based on AD boards and DSP's would be an interesting post. Customer reach is a customer reach.

BTW the project I want to build is a digital mixer with 4 SPDIF inputs and SPDIF output. With separate volume control for each input, so basically I need 4 I2S inputs, 4 AUXADC, 4 ASRC and 1 SPDIF output. 1451, 1452, 1463-300 and 1466 are my target DSP's and I would absolutely love to have hands on either on EVAL-ADAU1466 or EVAL-ADAU1467Z because they have rotary encoders on them.

I want to use multiple AD9164 DDS DACs#:  each would be set to the same frequency but the phase of each signal needs to be independently and statically adjusted with high resolution and accuracy.  Other ADI #DDS parts have a Phase Offset Register that I think statically adjusts the output phase; does the AD9164 have something analogous to it?

Hello, 

How to I change my engineer zone user name ? lallison

Best Regards,

Hello, i need to accurately measure a AM SSB signal peak power at a frequency starting from 1.5 to 30MHz: according to you it is better to use the ADL5910  or a log detector like LT5537 or the LTC5507? For me it is important the temperature behaviour, the linearity and the slope (to have more mV per dB). 20-30dB of theorically dynamics is enough

thank you

I want to use the AD9163 in 1.3V mode (overclocked) to the VDDx (as described on the top of page 5)

In the datasheet the requirement is for -/+2% for this voltage.

Questions:

1. what is the load change that the LDO will see from the DAC ? I need it to select the required "load regulation" spec for my LDO. 

2. If I use the 1.3V for the serdes as mentioned, give that my FPGA's serdes is 1.2V , is this ok or will there be a problem?  if so, what do u recommend to do?

3. can I use the same 1.3V LDO to also supply DVDD or will it impact performance or some other problem?

Hi,

I am just getting started with using ADXL372 IC. I am currently facing few issues getting it to work according to my requirements.

I am using an EVAL-ADXL372Z development module along with an ATSAMD21G18 microcontroller with an Arduino core to get of ADXL372. I started off with the ADXL example code mentioned here. I was able to get that working.

I am planning to use ADXL to measure an impact force for my experiments. My requirement is to set ADXL372 in a low power mode till the time an impact occurs(Wake up or Instant ON mode), I need to analyse the data of the impact. For this, I need to store the data in the FIFO(360 samples after the impact and 150 samples after the impact).

I modified the example code, to match the above requirements.

• Configured FIFO to be in Triggered mode.
• Operation mode was set to Instant On Mode
• Configured the INT1 pin to trigger HIGH when FIFO is full(360 samples)
• Getting the FIFO data and display it on Serial port

I have attached the code which I am using.

What seems to be happening is that ADXL_INT1_PIN is always getting triggered always and not specifically at an impact exceeding the low threshold(like it should in the Instant On mode)

Please Note that in the code I modified the INT1, INT2, CS Pins to suit my development board.

Can someone help me with this problem? I maybe making some mistake in my code.

jwang

if i generate a sine signals from DDS, and then send to ad9163 , is M0S0 is the first point and  M0S1 the second point ,

M1S0 is the third point  M1S1 is the fourth point ？？？ AM I can got a sine signals form the OUT if NCO is disable .

I am trying to figure out the best IC for a small IoT that can

1. Solar Energy Harvest

2. Charge a single cell Lithium Ion 4.2v

3. Provide a 3.3v regulated power supply

My system will be small <20mA ... and very very periodic a sensor + a BLE beacon

Seems like ADP5091/5092 or LTC4121-4.2 or LTC3331 all fit the bill.

I was originally planning to use a 1 watt 6v solar cell.. though I could use something smaller.

My questions

1. What is the difference between 5091/5092

2.  What is your recommendation?

Thanks,
Alan

I would like to use multiple LT3045s to produce a quiet, well regulated, bipolar power supply.  The input to the two linear regulators will be from two isolated DC/DC converters.  My intent would be to treat each DC/DC converter-LT3045 subsystem as an electrically independent subsystem and then to tie together, at the subsystem outputs, the "ground" of the positive voltage subsystem to the +voltage rail of the negative voltage subsystem to form the common return path for the bipolar power supply.  I am not sufficiently experienced to know if there are issues in accomplishing this that I do not understand.  I am exploring this as a option because I have not been able to identify a negative linear voltage regulator that has similar characteristics to the LT3045.

Hi everyone,

Currently, I am evaluating the performance of AD9172 with ADS7-V2. I go through the user guide (AD917x-FMC-EBZ Evaluation Board User Guide [Analog Devices Wiki] ) and AD9172 schematic diagram. However, I am quite confused about the direct clock option described in the user guide.

Q1:

In the user guide, to direct clock AD9172, we need to rotate C36 and C38 to instead be populated on C34 and C35. Connect a high-performance clock with >=12dBm output level to J34 for the direct clock option. In addition to this, a second low phase noise, high frequency clock source (3.84MHz , 7.68MHz, 15.36MHz, 30.72MHz, 61.44MHz, 122.88MHz, 245.76MHz and 491.52MHz) with 0 dBm output level that is the reference clock of the HMC7044 should be connected to the SMA connector J41. However, after studying the schematic diagram, I am quite confused why we need the second clock source connected to J41. Here is the circuit diagram:

When we rotate C36 and C38 to instead be populated on C34 and C35, we disable the HMC7044_CLKIN_N and HMC7044_CLK_P. The signal fed into J34 will go directly to AD9172 (CLKIN_P and CLK_N). In this case, why is it still necessary to connect a second clock source to J41? I think if we change the position of C36 and C38, we basically disable the HMC7044. Am I correct?

Q2: 

In addition to this, I have another question about HMC7044 and AD9172. For our application, we need to synchronization AD9172 with other devices. Therefore, it is required to make sure all clocks are from one common high quality oscillator. We are trying to connect our high quality 10MHz oscillator to J41 as HMC7044 reference clock. And the output of HMC7044 will go to AD9172 via HMC7044_CLK_N and HMC7044_CLK_P (through CLKOUT2 of HMC7044). In this case, how can we configure ACE? Here is a screenshot of ACE:

For the HMC7044 PLL1 Ref Clock source configuration, I set HMC7044 PLL1 Ref Clock Source to 'User Input (J41)'. For HMC7044 PLL1 Ref Clock, I set to 'Other frequency', since 10MHz is not in the list. Am I correct?

How about the AD917x setting? My understanding is that, if I set AD917x PLL Ref Clock to 100MHz (for example), the HMC7044 will generate 100MHz from 10MHz input reference clock and output this 100MHz to AD9172. Is it the way how it works? If not, please correct me!

Regards

Zichuan Zhou

Hi There,  I'm using a ADAU 1701 to create guitar effects in my new product.  I have 3 sounds: Distortion, Chorus, and reverb.  The Distortion and Chorus sound great, but I can't seem to get the Reverb to sound anywhere near where I want it.  It seems the more delay time I add, the more "latency" it adds to the sound...

I have done some research on the web and some have said that this chip just does not have enough on-board memory to create a good sounding reverb... Is this the case?  Does anyone have any experience with this?  I'm running out of time on this product and really need to find an answer on this.

Thanks for any help,

Kevin

   Hello,

   It's well known that some of the ADAU1701's 1024 instructions (at 48K sample rate) are needed for what's generally described as "overhead."  Is there a better-defined answer for exactly how many must be left on the table?  For example, a bug fix has resulted in one of the DSPs in the mixer we make to run 1015 instructions.  The code compiles and the prototype I tried it in works fine.  Is there any downside in running this close to the edge?  I once thought that if the exported TxBuffer file shows a few NOPs (code 0x00, 0x00, 0x00, 0x00, 0x01), it's good to go.  Yet in this case the 9 NOPs I see adds up to 1024 -- so apparently this doesn't reflect the overhead either.  It would be good to know what's involved with this "overhead."

Edit:  I just reworked some logic in an attempt to shrink the project.  What I had thought was quite clever saved me exactly one instruction.  It's down to 1014 now.

   Thanks, Bob

Hi !

I have a question about ADV7282AM.

At user guide, this is written.

Our customer will input NTSC(4:3) and change to 480p.

So this means input will be 640*480.

But output resolution is 720*507.

Q1)

How do you change resolution for horizontal 640 to 720?

Does the device add blanking area?

Q2)

How do you change resolution for vertical 480 to 507?

Does the device add blanking area?

Like this?

*Blue area will be blanking area

Or like this?

Or up scale to 720*507?

Best regards

Kawa

Hi,

I'm testing the DC1646A (demo board for the RF power detector LTC5564) and I'm having trouble getting a clean VCOMP. I'm not sure if it is due to noise or if I need to adjust some elements of the demo PCB.

I'm attaching some measurements. Parameters:

VCC = 5V, RFIN = 5.8 GHz, input power at the demo board 0 dBm.

CH1 (yellow) is VOUT

CH2(cyan) is VCOMP.

GAIN 1, otherwise I will specify it.

- NO RFIN.

- RFIN ON.

- RFIN OFF. (Now also showing VCOMP)

- RFIN OFF, VREF = 0.34V. Notice how VOUT has some transients and VCOMP goes high. The threshold, VREF 340 mV, is far from the 282 mV of VOUT.

-RFIN ON, VREF = 0.34 V. Looks like VOUT is noisy when VREF is ON. VCOMP is HIGH (makes sense since VOUT>>VREF)

-RFIN ON, VREF = 0.84  V. Now VCOMP is LOW (makes sense since VOUT<VREF)

-RFIN ON, VREF = 0.470  V. Now VCOMP is going LOW too often. As far as I understand, this is not how it should be since VOUT>VREF.

- RFIN ON, VREF = 0.70  V. Now VCOMP is going HIGH sometimes. As far as I understand, this is not how it should be since VOUT<<VREF.

Is this how it is supposed to work? I'm using a R&S lab power supply, I'm assuming it is a fairly clean power supply. 

Thank you,

Gerard

Hello,

I have a question about the quiescent current of ADP5304.

The output is set to 1.8 volts and the input is 3.6 volts.

For the sake of meeting the spec about 180 nA with occasional switching, there were some common mistakes that I try to avoid.

1. There is no probe connected with input & output node 

2. Use DMM ( 34465A ) 's smooth filter function 

However the lowest quiescent current from my measure result is about 280 nA. ( The attachment shows my average result )

Is there something I should do to meet the spec ?

Thanks for sharing the information.

Ian.

Having the AD9912 with a SI5351 at 25Mhz/670mV/pp as input for the DDS.

The communication is working ok (I guess) I have a start frequence S4-S1 (0,1,0,0)

so I get the 77,75879Mhz. After a software 1-time run of updating the registers the frequency changes

to +/- 85,560Mhz. Here after doing a FTW programming, but no frequency is changed.

Do I need something to do with S4-S1 after startup? Or do I have my registers not good?

The datasheet is a bit unclear in my vision about this and setting multipliers.

/////////////////////////////////////////////////////
//                                                 //
// Power-down & enable                             //
// Register 0x0010 default 0xC0 or 0xD0 [2]        //
//                                                 //
/////////////////////////////////////////////////////

  uint8_t Powerdown_digital      = 0;       // bit 0
  uint8_t Powerdown_full         = 0;       // bit 1
  uint8_t Not_used_1             = 0;       // bit 2
  uint8_t Not_used_2             = 0;       // bit 3
  uint8_t Powerdown_sysclock_pll = 0;       // bit 4*
  uint8_t Enable_output_doubler  = 0;       // bit 5*
  uint8_t Enable_CMOS            = 0;       // bit 6*
  uint8_t Powerdown_HSTL         = 1;       // bit 7

/////////////////////////////////////////////////////
//                                                 //
// Register 0x0012 default 0x00 [3]                //
//                                                 //
/////////////////////////////////////////////////////

  uint8_t Reset_DDS              = 0;       // bit 0

/////////////////////////////////////////////////////
//                                                 //
// Power-down & reset                              //
// Register 0x0013 default 0x00 [4]                //
//                                                 //
/////////////////////////////////////////////////////

  uint8_t Not_used_3             = 0;       // bit 0
  uint8_t Reset_sdivider         = 0;       // bit 1
  uint8_t Not_used_4             = 0;       // bit 2
  uint8_t Reset_sdivider2        = 0;       // bit 3
  uint8_t Not_used_5             = 0;       // bit 4
  uint8_t Not_used_6             = 0;       // bit 5
  uint8_t Not_used_7             = 0;       // bit 6
  uint8_t Powerdown_fund_DDS     = 0;       // bit 7

/////////////////////////////////////////////////////
//                                                 //
// System clock N-divider                          //
// Register 0x0020 default 0x12 [5]                //
// 25Mhz = 20                                      //
/////////////////////////////////////////////////////

  uint8_t N_divider0             = 0;       // bit 0*
  uint8_t N_divider1             = 0;       // bit 1*
  uint8_t N_divider2             = 1;       // bit 2*
  uint8_t N_divider3             = 0;       // bit 3*
  uint8_t N_divider4             = 1;       // bit 4*
  uint8_t Not_used_8             = 0;       // bit 5
  uint8_t Not_used_9             = 0;       // bit 6
  uint8_t Not_used_10            = 0;       // bit 7

/////////////////////////////////////////////////////
//                                                 //
// PLL parameters                                  //
// Register 0x0022 default 0x04 [6]                //
//                                                 //
/////////////////////////////////////////////////////

  uint8_t Charge_pump1           = 0;       // bit 0*
  uint8_t Charge_pump2           = 0;       // bit 1*
  uint8_t VCO_range              = 1;       // bit 2
  uint8_t Reference_2x           = 0;       // bit 3*
  uint8_t Not_used_11            = 0;       // bit 4
  uint8_t Not_used_12            = 0;       // bit 5
  uint8_t Not_used_13            = 0;       // bit 6
  uint8_t VCO_autorange          = 0;       // bit 7

Hi,

we have developed our own hardware, which is similar to the ZC702 with the FMCOMMS5-EZB. We have removed and added some interfaces, but basically the design/architecture is the same. Obviously the PL and the XDC files have been modified, since we are not having the same schematic. Nevertheless, we have some issue bringing up the board.

We were able to build and execute the FSBL from SDK and also running some no-os applications (hello world, memery test etc.). Now we are trying to start the linux os system. Unfortunalely, we have some issues with u-boot, which seems not to be executed. We tried to use JTAG boot mode and SD boot mode. Here is the debug response from UART:

Xilinx First Stage Boot Loader

Release 2016.2<9>Jul 26 2018-12:11:32

Devcfg driver initialized

Silicon Version 3.1

Boot mode is SD

SD: rc= 0

SD Init Done

Flash Base Address: 0xE0100000

Reboot status register: 0x60400000

Multiboot Register: 0x0000C000

Image Start Address: 0x00000000

Partition Header Offset:0x00000C80

Partition Count: 3

Partition Number: 1

Header Dump

Image Word Len: 0x0009B120

Data Word Len: 0x0009B120

Partition Word Len:0x0009B120

Load Addr: 0x00000000

Exec Addr: 0x00000000

Partition Start: 0x000075D0

Partition Attr: 0x00000020

Partition Checksum Offset: 0x00000000

Section Count: 0x00000001

Checksum: 0xFFE2745E

Bitstream

In FsblHookBeforeBitstreamDload function

PCAP:StatusReg = 0x40000A30

PCAP:device ready

PCAP:Clear done

Level Shifter Value = 0xA

Devcfg Status register = 0x40000A30

PCAP:Fabric is Initialized done

PCAP register dump:

PCAP CTRL 0xF8007000: 0x4C00E07F

PCAP LOCK 0xF8007004: 0x0000001A

PCAP CONFIG 0xF8007008: 0x00000508

PCAP ISR 0xF800700C: 0x0802000B

PCAP IMR 0xF8007010: 0xFFFFFFFF

PCAP STATUS 0xF8007014: 0x00002A30

PCAP DMA SRC ADDR 0xF8007018: 0x00100001

PCAP DMA DEST ADDR 0xF800701C: 0xFFFFFFFF

PCAP DMA SRC LEN 0xF8007020: 0x0009B120

PCAP DMA DEST LEN 0xF8007024: 0x0009B120

PCAP ROM SHADOW CTRL 0xF8007028: 0xFFFFFFFF

PCAP MBOOT 0xF800702C: 0x0000C000

PCAP SW ID 0xF8007030: 0x00000000

PCAP UNLOCK 0xF8007034: 0x757BDF0D

PCAP MCTRL 0xF8007080: 0x30800100

DMA Done !

...................................................................................................

FPGA Done !

n FsblHookAfterBitstreamDload function

Partition Number: 2

Header Dump

Image Word Len: 0x00020E2E

Data Word Len: 0x00020E2E

Partition Word Len:0x00020E2E

Load Addr: 0x04000000

Exec Addr: 0x04000000

Partition Start: 0x000A26F0

Partition Attr: 0x00000010

Partition Checksum Offset: 0x00000000

Section Count: 0x00000001

Checksum: 0xF7EFAC14

Application

Handoff Address: 0x04000000

In FsblHookBeforeHandoff function

SUCCESSFUL_HANDOFF

FSBL Status = 0x1

UNDEFINED_HANDLER

FSBL Status = 0xA301

This Boot Mode Doesn't Support Fallback

In FsblHookFallback function

We were using the same u-boot as did with the evaluation boards, the ps7_init has been changed with the custom board settings.

Do you have any idea what goes wrong?

Thanks and kindly regards

Jan