Hi,
Can i know how to check the code size written and uploaded into ADSP-21469 evaluation board from Cross Core Embedded Studio?
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How to check the code size in Cross Core Embedded Studio?
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type capacitors for filtering ADM202JRNZ
I use ADM202JRNZ.
Can use SMD ceramic capacitors for filtering?
What is nominal voltage SMD ceramic capacitors?
What is type dielectric SMD ceramic capacitors (NPO, X7R, X5R)?
What is nominal value current R1OUT?
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AD9371 Initialize Problem.
Hello Team,
Now I have a board used ad9371 ad9528 ,and same as adrv9371 board.
It has the following problem:
There are many differences with adrv9371 initialize spi transfer.
The attachment is my own board start linux log .
Can you help me to analyze the cause of the problem?
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AD9371 TXx/RXx enable control
My customer wants to control AD9371 TXx or RXx path enable respectively via API command.
Is it possible ? and Which API command should they use ?
Thanks.
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AD9371 ARM load problem
I use ZC706+AD9371Evaluation board，A problem found when SDK run headless() function.
if (pllLockStatus & 0x01)
{
if ((mykError = MYKONOS_initArm(&mykDevice)) != MYKONOS_ERR_OK)
{
/*** < Info: errorString will contain log error string in order to debug failure > ***/
errorString = getMykonosErrorMessage(mykError);
}
/*** < Action: User must load ARM binary byte array into variable binary[98304] before calling next command > ***/
if ((mykError = MYKONOS_loadArmFromBinary(&mykDevice, &binary[0], count)) != MYKONOS_ERR_OK)
{
/*** < Info: errorString will contain log error string in order to debug why
* ARM did not load properly - check binary and device settings > ***/
/*** < Action: User code > ***/
errorString = getMykonosErrorMessage(mykError);
}
}
when I run MYKONOS_loadArmFromBinary() , the PLLLOCKSTATUS is 0x01 and MYKONOS_initArm() also succeed. But MYKONOS_loadArmFromBinary() run failed. The value（calculatedChecksum） in function(MYKONOS_verifyArmChecksum()) is always 0x00.
I found the MYKONOS_loadArmFromBinary() is also have problem. The founction is write reg 0xD04, 0xD05, 0xD06, 0xD07, 0xD04, 0xD05, 0xD06, 0xD07 .....etc.But i read these regs, it is all 0x00.
E.g.：I write 0x90 to 0xd04, when write done, i read 0xd04 Immediately. The value is 0x00.
I wonder how to load the file to arm in AD9371.
The bin file "Mykonos_M3.bin" is found in C:\Program Files (x86)\Analog Devices\AD9371 Transceiver Evaluation Software\Resources
The SPI write function and SPI read function is verified by others regs.E.g.：I write 0x10 to 0x028, when write done, i read 0x028 Immediately. The value is 0x10.
Best Regards.
Thanks!
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Where should I connect DACGND of AD5060?
AD5060 has two grounding pins: AGND and DACGND.
DACGND is described as "DAC core ground input".
I'm pretty accustomed to A/D circuits having different ground terminals for digital and analog parts, and if DACGND was labeled as "Digital ground input" I wouldn't be as confused as I am now.
So the question is - which ground plane should I connect DACGND to? Should it be digital plane with MCU and other fast switching ICs or should it be analog plane?
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AD9361 DAC Explanation
Hi all,
I'm working with AD9361 integrated in Xilinx ZedBoard, and I'm pretty much new in this area. I made HDL design using this project(analogdevicesinc/hdl · GitHub) projects->fmcomms2->zed. Also run SDK with this software(no-OS/ad9361 at master · analogdevicesinc/no-OS · GitHub).
The problem I have is that i can't realize how to send some data throw DAC to output of ad9361? I defined DAC_DMA and when I call function dac_init(ad9361_phy, DATA_SEL_DMA, 1); I can see LUT values in address space, but I don't know how to start conversion to send those LUT values on TX line and see it on osciliscope? Also, can someone explain me why sw make theese changes on LUT values:
data_i1 = (sine_lut[index_i1] << 20);
data_q1 = (sine_lut[index_q1] << 4);
Xil_Out32(DAC_DDR_BASEADDR + index * 4, data_i1 | data_q1); // I have plotted this data in MATLAB and see that this is sine wave.
Where does this 20 and 4 vaues come from?
Hope that someone can help me
Best regards,
Nemanja
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Issues building the ADRV9009/ZCU102 HDL Project
There were two issues. For both I found workarounds. (Building with Vivado 2018.2.)
Issue 1: Project build errors.
Excerpt from build log:
...
## source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl
...
### ad_connect sys_ps8/emio_spi0_ss_i_n VCC
...
ERROR: [IP_Flow 19-3460] Validation failed on parameter 'Const Width(CONST_WIDTH)' for "Const Value is out of range -0:1 allowed by width"
. BD Cell 'sys_ps8_emio_spi0_ss_i_n_VCC'
ERROR: [IP_Flow 19-3460] Validation failed on parameter 'Const Val(CONST_VAL)' for Const Value is out of range -0:1 allowed by width
. BD Cell 'sys_ps8_emio_spi0_ss_i_n_VCC'
Workaround 1: In zcu102_system_bd.tclcommented out offending lines 100 and 113 :
100 #ad_connect sys_ps8/emio_spi0_ss_i_n VCC
113 #ad_connect sys_ps8/emio_spi1_ss_i_n VCC
Issue 2: In synthesis got two errors (subsequently)
ERROR: [Synth 8-1766] cannot open include file inc_id.h [/data/nas/md12-fs17/md12-fs17/ES/ECAD/stargazer_fpga/users/walsh/RS/debug/hdl-master/projects/adrv9009/zcu102/adrv9009_zcu102.srcs/sources_1/bd/system/ipshared/6002/address_generator.v:74]
ERROR: [Synth 8-1766] cannot open include file resp.h [/data/nas/md12-fs17/md12-fs17/ES/ECAD/stargazer_fpga/users/walsh/RS/debug/hdl-master/projects/adrv9009/zcu102/adrv9009_zcu102.srcs/sources_1/bd/system/ipshared/6002/response_generator.v:58]
Workaround 2: Copied the missing files from other folders. Completed synthesis/implementation/bit file generation in the GUI.
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LTC2321-16
Hi
I have a question LTC2321-16.
Is it okay if we can change the 220pF in front of the ADC to 10pF?
Best Regards
HOD
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The capacitor value of EVALPRAHVOPAMP-1RZ_UG-670
Hi,
I need to know if I take C5, C7 as 1000µF/100V and C6,C8 as 100nF/100V is that the correct value ?
You can see in this figure 10.
Thanks for your answer.
But I have already a regulated supply and probably it not necessary to add theses capacitors.
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Characteristics ADA4700
Hello,
I'll working with ADA4700 Amplifier, can you confirm in the datasheet with this component, the current is about 30 mA, Output voltage +/-48V thus the power is about 2.88 W for this product ? I find 2 supply power and in the datasheet I can see "Supply Current per Amplifier" max is 2.2 mA if I take 2 supply power with 0.5A or 1A each one, it'll work properly with this choice ? Thanks for your answer
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ADXL355
Hi
I have a question ADXL355.
Data sheet p22
Please tell me about over range protection specification of ADXL 355.
"Floating state towards zero", but in the case of the axis in the direction of gravitational acceleration,
Can I think that it costs 1 G offset?
When applying sinusoidal vibration of 1 G or more in the direction of gravitational acceleration, the value of the sinusoidal vibration around 0 G was output.
Below is the setting environment.
· Input vibration: 20 Hz amplitude 1 G stronger
· Sensor setting: Range ± 2 G ODR 250 Hz External sample mode (measurement frequency 200 Hz)
Best Regards
HOD
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Setup of AD9144
Hello Everyone,
I am trying to connect the AD-FMC-DAQ2 to KCU105 FPGA, and reccently I met the problem with setting up the AD9144. I have used the following code to do the basic setup, then I give the digital signal and get the waveform from the oscilloscope, from which the frequency is 250MHz. Now I want to make the change so I can get the different frequency，and I have several questions about the setup code, which is referred from : EngineerZone: Message List
1. The input reference clock sourced from input port is 1GHz, I am confused about the DAC CLK, does it use the DAC PLL or directly use the input reference CLK?
2. In the section of required device configurations, why set (0x1c4, 0x73) since I found it should be set 0x7e in AD9144 manual.
3. What does (0x291, 0x49) mean since I didn't find it in the manual.
int wr_reg_spi (int dev, unsigned long offset, unsigned long data)
{
//ioctl ( 3, 0xffff & (~(0x1 << (dev-1))));
*((uint32_t *) map_base + (0x0002) ) = 0xffff & (~(0x1 << (dev-1)));
usleep(1000);
//printf("wr_reg:%X\n", 0xffff & (~(0x1 << (dev-1))));
//ioctl ( 4, ((offset<<8)+data)<<8);
*((uint32_t *) map_base + (0x0000) ) = ((offset<<8)+data);
*((uint32_t *) map_base + (0x0001) ) = 0x1;
usleep(1000);
//printf("wr_reg:%X\n",((offset<<8)+data)<<8);
//ioctl ( 3, 0xffff);
*((uint32_t *) map_base + (0x0002) ) = 0xffff ;
usleep(1000);
//printf("wr_reg:%X\n",0xffff);
return 0;
int cfg_DAC()
{
wr_reg_spi(1,0x000, 0x81); // reset
wr_reg_spi(1,0x000, 0x00); // reset
wr_reg_spi(1,0x011, 0x00); // dacs - power up everything
wr_reg_spi(1,0x080, 0x00); // clocks - power up everything
wr_reg_spi(1,0x081, 0x00); // sysref - power up/falling edge
// required device configurations
wr_reg_spi(1,0x12d, 0x8b); // data-path
wr_reg_spi(1,0x146, 0x01); // data-path
wr_reg_spi(1,0x520, 0x1c); // sysref-armed
wr_reg_spi(1,0x040, 0x00); // current
wr_reg_spi(1,0x041, 0x02); //
wr_reg_spi(1,0x042, 0x00); //
wr_reg_spi(1,0x043, 0x02); //
// wr_reg_spi(1,0x146, 0x00); //
// wr_reg_spi(1,0x520, 0x1e); //
// wr_reg_spi(1,0x521, 0x00); //
// wr_reg_spi(1,0x522, 0x00); //
// wr_reg_spi(1,0x523, 0x00); //
// wr_reg_spi(1,0x524, 0x00); //
wr_reg_spi(1,0x2a4, 0xff); // clock
wr_reg_spi(1,0x1c4, 0x73); // dac-pll
wr_reg_spi(1,0x291, 0x49); // serde-pll
wr_reg_spi(1,0x29c, 0x24); // serde-pll
wr_reg_spi(1,0x29f, 0x73); // serde-pll
wr_reg_spi(1,0x232, 0xff); // jesd
wr_reg_spi(1,0x333, 0x01); // jesd
// digital data path
wr_reg_spi(1,0x112, 0x00); // 2x interpolation
wr_reg_spi(1,0x110, 0x00); // 2's complement
wr_reg_spi(1,0x111, 0xa0); // fdac/4 modulation
wr_reg_spi(1,0x13c, 0xff); // I gain
wr_reg_spi(1,0x13d, 0x07); // I gain
wr_reg_spi(1,0x13e, 0xff); // Q gain
wr_reg_spi(1,0x13f, 0x07); // Q gain
// transport layer
wr_reg_spi(1,0x200, 0x00); // phy - power up
wr_reg_spi(1,0x201, 0x00); // phy - power up
wr_reg_spi(1,0x300, 0x01); // single link - link 0
wr_reg_spi(1,0x450, 0x00); // device id (0x400)
wr_reg_spi(1,0x451, 0x00); // bank id (0x401)
wr_reg_spi(1,0x452, 0x04); // lane-id (0x402)
wr_reg_spi(1,0x453, 0x83); // descrambling, 4 lanes
wr_reg_spi(1,0x454, 0x00); // octects per frame per lane (1)
wr_reg_spi(1,0x455, 0x1f); // mult-frame - framecount (32)
wr_reg_spi(1,0x456, 0x01); // no-of-converters (2)
wr_reg_spi(1,0x457, 0x0f); // no CS bits, 16bit dac
wr_reg_spi(1,0x458, 0x2f); // subclass 1, 16bits per sample
wr_reg_spi(1,0x459, 0x20); // jesd204b, 1 samples per converter per device
wr_reg_spi(1,0x45a, 0x0a); // HD mode, no CS bits
wr_reg_spi(1,0x45d, 0x49); // check-sum of 0x450 to 0x45c
wr_reg_spi(1,0x46c, 0x0f); // enable deskew for all lanes
wr_reg_spi(1,0x03a, 0xc1); // sysref-armed
wr_reg_spi(1,0x476, 0x01); // frame - bytecount (1)
wr_reg_spi(1,0x47d, 0x0f); // enable all lanes
// physical layer
wr_reg_spi(1,0x2aa, 0xb7); // jesd termination
wr_reg_spi(1,0x2ab, 0x87); // jesd termination
wr_reg_spi(1,0x2b1, 0xb7); // jesd termination
wr_reg_spi(1,0x2b2, 0x87); // jesd termination
wr_reg_spi(1,0x2a7, 0x01); // input termination calibration
wr_reg_spi(1,0x2ae, 0x01); // input termination calibration
wr_reg_spi(1,0x314, 0x01); // pclk == qbd master clock
wr_reg_spi(1,0x230, 0x28); // cdr mode - halfrate, no division
wr_reg_spi(1,0x206, 0x00); // cdr reset
wr_reg_spi(1,0x206, 0x01); // cdr reset
wr_reg_spi(1,0x289, 0x04); // data-rate == 10Gbps
wr_reg_spi(1,0x280, 0x01); // enable serdes pll
wr_reg_spi(1,0x280, 0x05); // enable serdes calibration
wr_reg_spi(1,0x268, 0x62); // equalizer
// cross-bar
wr_reg_spi(1,0x308,0x11); // lane selects
wr_reg_spi(1,0x309,0x03); // lane selects
// data link layer
wr_reg_spi(1,0x301, 0x01); // subclass-1
wr_reg_spi(1,0x304, 0x00); // lmfc delay
wr_reg_spi(1,0x305, 0x00); // lmfc delay
wr_reg_spi(1,0x306, 0x0a); // receive buffer delay
wr_reg_spi(1,0x307, 0x0a); // receive buffer delay
wr_reg_spi(1,0x03a, 0x01); // sync-oneshot mode
wr_reg_spi(1,0x03a, 0x81); // sync-enable
wr_reg_spi(1,0x03a, 0xc1); // sysref-armed
wr_reg_spi(1,0x300, 0x01); // enable link
// dac calibration
wr_reg_spi(1,0x0e7, 0x38); // set calibration clock to 1m
wr_reg_spi(1,0x0ed, 0xa6); // use isb reference of 38 to set cal
wr_reg_spi(1,0x0e8, 0x03); // cal 2 dacs at once
wr_reg_spi(1,0x0e9, 0x01); // single cal enable
wr_reg_spi(1,0x0e9, 0x03); // single cal start
wr_reg_spi(1,0x0e7, 0x30); // turn off cal clock
return 0;
}
I really hope anyone who has the relevant experience can help me with it, thank you soooo much!!
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AD9172 custom design mismatching jesd204 parameters
Hi,
I'm currently developing a project based on the AD9172. For that purpose, I bought one eval board and the ADS7v2.
They work correctly together and now I want to use another FPGA board (the ZCU102), so I designed a simple FPGA project based on the JESD204 IP from Xilinx.
I want to use JESD204 mode 2 (3 lanes). I configured the IP like this (IP core shared in design):
I program the FPGA and then I set the DAC with ACE like this:
I must change some registers because my clocking scheme is the following:
For the AD9172:
Registers | Value | Comments |
0x308 | 0x8 | physical lane 0 correspond to logical lane 0, phy 1 to log 1 etc. |
0x309 | 0x10 | |
0x95 | 0x0 | Enable PLL |
0x790 | 0 | Required |
0x791 | 0 | Required |
0x796 | 0xE5 | Required |
0x7A0 | 0xBC | Required |
0x794 | 0x08 | Recommended CP current |
0x797 | 0x10 | Required |
0x797 | 0x20 | Required |
0x798 | 0x10 | Required |
0x7A2 | 0x7F | Required |
Pause 100 ms | ||
0x799 | 0xC3 | Output clk = dac clock /4, N div=3 |
0x793 | 0x18 | Input divider = 1 |
0x94 | 0x00 | DAC clock = VCO / 1 |
0x792 | 0x2 | Reset VCO |
0x792 | 0 | |
Pause 100 ms | ||
0x7B5 | READ | If locked, equals 1 |
For the HMC7044:
Registers | Value | Comments |
3 | 0x2C | Disable PLLs |
5 | 0x6F | CLKIN1 as external VCO input |
0x64 | 0x1 | External VCO |
0xED | 0 | CLKOUT3 output mux = channel divider |
0x151 | 0 | CLKOUT13 output mux = channel divider |
0x14B | 0x40 | CLKOUT13 divided by 64 -> 500 / 64 = 7.8125 = sysref to FPGA |
0x14C | 0 | |
0xE7 | 0x40 | CLKOUT3 divided by 64 -> 500 / 64 = 7.8125 = sysref to DAC |
0xE8 | 0 | |
0xE3 | 0 | CLKOUT2 output mux = channel divider |
0x147 | 0 | CLKOUT12 output mux = channel divider |
0xDE | 0 | CLKOUT2 divided by 2 -> 500 / 2 = 250 = data rate clock unused because external dac clock |
0xDD | 0x2 | |
0x142 | 0 | CLKOUT12 divided by 2 -> 500 / 2 = 250 = data rate clock to FPGA |
0x141 | 0x2 |
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Can I change the center frequency of AD9361 through FPGA rather than ARM in zc7030?
Now we can realize changing the center frequency of AD9361 through No_os Arm in zc7030,but we want to try if we can control some parameters such as frequency through FPGA in zc7030.Can this be done?Do you know the way?
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LTC4020 heavy duty battery charger
Hi, do you think is feasible to use LTC4020 for a 24V/30A battery charger?
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Connecting 2 FMCOMMS5 board with a single Zc706 carrier board !
Hello,
I'm working on FMCOMMS5 board with the xilinx ZC706 SoC as carrier board. At a time one such FMCOMMS5 can be attached with the zc706 board through 400 pin HPC FMC interface. I have 2 units of FMCOMMS5 boards and I was thinking of using both of them connecting them simultaneously through the HPC interface with the help of some 1 to 2 cabling arrangement. Is this possible? If so, where I can find such a connector?
Thanks,
Tanmoy
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Adding the DMA IP Core to the official project,some errors occurred.
Dear all,
I tried to add the DMA IP Core into the official project,when synthesis,some errors and critical warnings appeared as shown below.How to solve it?
Regards,
Wang.
2018-7-18
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LTC1859 Interfacing with Arduino Due in Bipolar Range
Hello,
I am using Arduino Due board and trying to interface LTC1859 with it.
Physical Connections are as follows:
AVDD, DVDD : Connected to 5V through 10uF (electrolytic) and 0.1uF (Ceramic) capacitor
OVDD : Connected to 3.3V through 10uF (electrolytic)
COM : Connected to GND
CH0 : Input
SDI : SPI MOSI
SDO : SPI MISO
SCK : SPI SCK
CONVST : Pin 10
RD : GND
All Grounds are common.
And program is
#include <SPI.h>
#define CONVST 10 //IC PIN 28
#define BUSY 9 //IC PIN 22
// IC UNO DUE(SPI)
// SCK(26) 13 3
// SDO(23) 12 1
// SDI(25) 11 4
int k = 1;
byte x = 0; byte y = 0;
word data[1000] = {0};
float voltage = 0, avg = 0;
void setup() {
Serial.begin(115200);
SPI.begin();
SPI.setClockDivider(12);
SPI.setBitOrder(MSBFIRST);
SPI.setDataMode(SPI_MODE0);
pinMode(CONVST, OUTPUT);
pinMode(BUSY, INPUT);
digitalWrite(CONVST, LOW);
Serial.print("setup done");
}
void loop() {
//record k ADC samples
for (int i = 0; i < k; i++) {
x = SPI.transfer(B10001000); // Single ended input at channel 0, 0V to 5V range (See LTC185x datasheet p15-16)
y = SPI.transfer(B00000000); // Filler
delayMicroseconds(2);
//Trigger a conversion with a fast pulse
noInterrupts();
digitalWrite(CONVST, HIGH);
digitalWrite(CONVST, LOW);
interrupts();
//Wait for conversion to be finished
while (!digitalRead(BUSY)) {
}
delayMicroseconds(4);
data[i] = word(x, y);
Serial.print(data[i]);
Serial.print(" ");
}
delay(100);
for (int i = 0; i < k; i++) {
voltage = (float)data[i];
voltage = voltage / 65534 * 10; //*5 for 0 to 5V and *10 for 0 to 10V
avg += voltage;
}
Serial.println(avg / k, 9);
avg = 0;
}
OUTPUT
for 0-5v Range
for -+5v Range
for 0-10v Range
for -+10v Range
The IC- LTC1859 is performing accurately in the unipolar single ended range of 0-5v and 0-10v. But it is not responding in bipolar single ended range of -5v to +5v and -10v to +10v. In this range it is getting only 2.5v for -+5v and 5v for -+10v for any input. Any help would be appreciable.
Thanks.
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Where the code stores?
Hi,
ADSP-21469 EZBRD has external Memory DDR2 and flash Memories are available.If we upload any code into board from Cross Core Embedded Studio ,where the data will store either internal memory or external memory (that to DDR2 or Flash).
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