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AD5933 Vpp excitation voltage setting

June 25, 2018, 6:28 am
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Hi all,

 

I am trying to undertsand how to AD5933 works, but I'm having trouble as in the documentation I find two things about setting the Vpp for the excitation voltage quite contradictory:

1) Vpp scales with the Vdd: "VDD*1/3.2=VoltageExcitationOutput(p-p)"

2) Vpp is set by the user using control registers 0x80, 0x81: "The user has the added flexibility to select one of four possible output excitation peak-to-peak ranges by setting Bit D8 and Bit D9 in the control register"

 

So, how does this actually work?

Thanks to everybody

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ADRV9375-N/PCBZ TES DPD GUI GPIOs

March 21, 2018, 4:38 am
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Hello,

We bought ADRV9375-PCBZ ADi evaluation board. The board came with 2 SD-cards. I use the windows-based TES and DPD software.

I am now designing my own board and would like to use the TES/DPD GUI directly and feed my PA.

 

It seems you dont use the GPIOs with both software, am I correct? In that case, instead of routing all the GPIOs, I could simplify pcb connections and use only the GPIOs I need. Then I will program required GPIO usingTES.

 

Thank you for your help.

 

Best,

Chris

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ADRV9375 Eeprom erased

June 13, 2018, 10:39 am
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Hello all,

 

I made a mistake, I erased the memory (M24C02) of my ADRV9375. Now the TES is not working. Do I need to send the board back to ADi so you can program the memory? Or is there a fix?

 

Thanks for your help.

 

Best,

 

Chris

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(ADV7282A-M)To quit fast switch.

June 21, 2018, 6:46 pm
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Hi !

 

I have a question about ADV7282A-M

Our customer is using fast switch mode.

After they run fast switch script which ADI made they want to quit fast switch mode.

　・42 0E 80 ;  ADI Required Write [Fast Switch]

　・42 D9 44 ;  ADI Required Write [Fast Switch]

　・42 0E 40 ; Select User Sub Map 2 [Fast Switch]

　・42 E0 01 ; Select fast Switching Mode [Fast Switch]

　・42 0E 00 ; Select User Map [Fast Switch]

This script is for fast switch.

To quit fast switch without device reset, what should they do?

 

Best regards

Kawa

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800x600 RGB to 16 bit YUV422 on ADV7403

June 19, 2018, 3:18 am
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We are developing a product that takes in VGA or component video using an ADV7403 to convert to 16 bit YUV422 for capture.  I have been attempting to program the ADV part and it seems to be having trouble locking on to the signal.  I have adapted the following register settings from the example:

  {03,0x09},
    {0x05, 0x02}, // ; Prim_Mode =010b for GR
    {0x06, 0x01}, // ; VID_STD=0001b for 800x600 _@ 60
    {0x1D, 0x47}, // ; Enable 28MHz Crystal
    {0x3A, 0x11}, // ; set latch clock settings to 001b, Power Down ADC3
    {0x3B, 0x80}, // ; Enable External Bias
    {0x3C, 0x5D}, // ; PLL_QPUMP to 101b
    {0x6A, 0x00}, // ; DLL Phase Adjust
    {0x6B, 0xC3}, // ; Swap Pr & Pb
    {0x73, 0x90}, // ; Set man_gain
    {0xbf, 0x00},
    {0xF4, 0x3F}, // ; Max Drive Strength
    {0x0E, 0x80}, // ; ADI Recommended Setting
    {0x52, 0x46}, // ; ADI Recommended Setting
    {0x54, 0x00}, // ; ADI Recommended Setting
    {0x0E, 0x00}, // ; ADI Recommended Setting

The result is that the chip fails to lock on to my 800x600 VGA source; disabling the "blue screen" output enabled me to capture the attached picture, which shows that the syncs are not aligned correctly.

 

I have tried using the following register settings for CSC but these simply turned the picture green:

  {0x52, 0x00}, // conversion from RGB->YPrPb
    {0x53, 0x00}, // CSC start
    {0x54, 0x07}, // CSC Register
    {0x55, 0x0C}, // CSC
    {0x56, 0x94}, // CSC
    {0x57, 0x89}, // CSC
    {0x58, 0x48}, // CSC
    {0x59, 0x08}, // CSC
    {0x5A, 0x00}, // CSC
    {0x5B, 0x7a}, // CSC
    {0x5C, 0xe1}, // CSC
    {0x5D, 0x00}, // CSC
    {0x5E, 0x19}, // CSC
    {0x5F, 0x48}, // CSC
    {0x60, 0x08}, // CSC
    {0x61, 0x00}, // CSC
    {0x62, 0x20}, // CSC
    {0x63, 0x03}, // CSC
    {0x64, 0xa9}, // CSC
    {0x65, 0x1a}, // CSC
    {0x66, 0xb8}, // CSC last

What register settings should I use to fix the colour space and to align the syncs?

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Can I change the center frequency of AD9361 through FPGA rather than ARM in zc7030?

June 25, 2018, 6:40 am
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Now we can realize changing the center frequency of AD9361 through No_os Arm in zc7030,but we want to try if we can control some parameters such as frequency through FPGA in zc7030.Can this be done?Do you know the way?

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ADV7181C For STANAG3350B Receiver

June 20, 2018, 12:30 am
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Hi,

In one of our application, we need to receive STANAG3350B differential signals, Convert it into Single ended and digitize RGsB signals.

We have selected AD8145 to receive Differential RGsB, and ADV7181C Video Decoder for Digitize.

I have few queries regarding the connectivity of the RGsB signals into Video Decoder.

   > As per the Functional Block Diagram shown in Page 3 of datasheet, ADC0 output is connected to Sync Extract and ADC0, ADC1 and ADC2 are connected to Standard Definition Processor block. ADC1, ADC2 and ADC3 are connected to Component processor Block.

   > If I connect inputs as recommended by datasheet (Page16, Table 8), Gs -> Ain6, R-> Ain5, B -> Ain4 and use ADC0, ADC1 and ADC2 respectively, can I use Sync Extract to extract Sync on Green, and use CP block for processing RGB. How it will work ?

   > Please recommend how I can extract Sync from Green and process RGB video received in STANAG3350B standard.

 

--

Regards

Ramakrishna D C 

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AD9523-1 Status REFA

June 22, 2018, 3:53 am
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In AD9523-1 register 0x22C, bits 2 and 3 indicate the status of the two reference inputs. The bits are set when the corresponding input is 'OK'. But what does OK actually mean? That transitions have been detected on the reference input pin? That a clock within a usable frequency range is present?

 

UPDATE: I've configured the STATUS0 output pin to show REF A status and probed the line with an oscilloscope. With no reference connected, I can see occasional 840ns pulses on STATUS0, perhaps 1 every 30 - 100us. Connecting a signal generator to the reference input, I see the pulses becoming more and more frequent as I increase the reference frequency. By 2.7MHz, STATUS0 is a square wave, 800ns on, 680ns off. Above 2.8MHz, STATUS0 stays high permanently. Note that this is with the AD9523-1 set up to expect a 10MHz reference input.

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ADA4930 Common Mode Voltage / Diff-Amp Calculator

June 19, 2018, 4:04 am
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Hi,

 

I want to use a 1.8 V high speed ADC in combination with the ADA4930. I'm analyzing two signals, one is single ended and the other one is a differential one.

 

According to the dataseeht, the ADA4930 does not create its own input common mode voltage e.g. VDD/2, in single supply operation. Thus for an AC coupled input signal e.g. ±1.5 V, I have to provide the input common mode voltage e.g. with resistors as shown on page 22 in the datasheet. So I tried to analyze the circuit behaviour by two different ways.

 

  1. I downloaded the Spice model and performed a single ended to differential simulation. The input signal swings from +0.5 V to -0.5 V (AC coupled, and no additional bias voltage). Interestingly, the output does not clip, as I would expect as -0.5 V are far below the minimum common mode input voltage of 0.3 V. It seems the Spice model provides its own input common mode voltage, which is equal the output common mode voltage.
  2. I tried to analyze the amplifiere with the Diff-Amp Calculator. Unfortunatly it doesn't works on a Windows 10 OS. Anyway, I have also access to a PC with Windows 7 (64-Bit). I'm using version 4.0.34.8, but it seems some thing went terrible wrong (see attached image). The input and output signals always clipped, and it is not possible to change the output common mode voltage. There are only two values available 8,000 V (8 kV) and -19,000 V (-19 kV).

 

So does the ADA4930 provides its own input common mode voltage (I don't think so), and is the Spice model correct?

 

BR

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ADV7280A I2C Failure

June 21, 2018, 3:04 am
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Hi

I'm using ADV7280A decoder. Following voltage is supplied : DVDDIO =3.3V , AVDD=DVDD=PVDD=1.8V.

ALSB pin is grounded so slave address to write register is  hex(40).

Reset sequence is done as follows :

1) power down and reset is made zero for 10mS

2) then power down is made high

3) 30mS after power down high, reset is made high

4) 40mS after reset high, we start I2C communication.

Pull-up resistor used for I2C (SCL,SDA) are 4.7K and is pulled-up to 3.3V.

But decoder is not responding to the slave address and SDA remains high. Kindly suggest a method to debug. How to check whether IC is gone bad?

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ADV7393 internal test pattern issues

June 20, 2018, 1:29 pm
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I am trying to output the ADV7393 internal color test pattern on our custom board. The output is CVBS using NTSC square pixel and I am providing the device a 24.5454MHz clock. While I am producing a bar test pattern, there are numerous issues that include no color as well as noise throughout the image.

 

Here are my settings:

x17 x02
x00 x1C
x82 xDB
x84 x40

 

Does this device support outputting the internal color test pattern for this NTSC square pixel format?

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2289A-B with LTC2380-24

June 22, 2018, 6:52 am
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Hi,

I work with demo circuit 2289A-B and the LTC2368-24 but i would change it to LTC2380-24, is it possible? Or may I change anything else on the demo bord ?

 

Kind regards

Pierre-louis

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LTC2309 : ADC analog inputs sinking current!!

June 7, 2018, 9:30 am
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I'm using the  ADC LTC2309 to convert analog signals coming from an opam. The analog voltage to measure ranges from 2 to 3.5 V. The signal has very low fluctuations so we can say that it is almost a DC signal.

In one of my experiments I was measuring 2.4V at input 7  and suddenly  the voltage went up by 0.7 V. Hence the measured voltage became 3.1V. I verified this value either by collecting the data via I2C or by measuring directly on  this input.

 

I thought it was the opam that was giving the wrong signal. Verifying the circuit, it was effectively the ADC pin that was giving the wrong signal.

 

The connection of components going from the opam output to the ADC input is a 100 Ohm resistor  with a 47pF capacitor from the ADC input  to ground, as recommended in the last figure in the datasheet.

The Vref pin is connected to ground while the Refcomp pin is connected to +5V. I retreive data from the ADC input via I2C using the command F8 that addresses the 7th channel in unipolar mode and seting the ADC in nap mode. Then leaving the ADC in sleep mode, the result is the same.

 

Observing this, I realize that the ADC input is sinking current which explains the increase of measured voltage at its input.

Another test that I made was removing the 100 Ohm resistor and connecting the output of the opam directly to the ADC input.

The read value was oscillating around  2.55V . Another observation is that the same value applied on input 8 is also present in other pins of the ADC which are not connected.

 

The question that arises is why the ADC would start sinking current with no apparent reason. ?

 

I will really appreciate any hint or advices you can provide.

 

Regards,

 

Fausto

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LTC4015 doesn't start charging

May 17, 2018, 8:23 am
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In our PCB design, in many cases the LTC4015 doesn't start charging (sometimes it does).

The battery is 4 cells LiFePO4, same problem with "LiFePO4 Programmable" and "LiFePO4 Fixed Standard Charge".

A 10K NTC is connected, with a 10K bias resistor (register 0x40 reads 0x5547).

When it doesn't start charging:

bit bat_missing_fault=1 (register 0x34 = 0x0002). The battery is connected, I measure 13.3V on BATSENS pin.

when removing input power, register 0x34 = 0x0100 (suspend).

when re-applying input power, register 0x34 = 0x0002 (battery missing).

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LT3471 Load Transient Response

June 23, 2018, 8:25 pm
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Dear All:

I want to know LT3471 output load transient response depend on datasheet page 1 picture Vout1 & Vout2 ,have any detail information to me refer. thanks

 

 

Best Regards,

Jack

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Differences in Using LTC6804 Instead of LTC6811

June 25, 2018, 7:25 am
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Hi, I used the LTC6811 footprint to create a PCB for a battery management unit. I then discovered that there is no stock in Canada (we need it quickly).  Looking around I see that the 6811 replaced the 6804 and I do not see any big differences between them beside speed.  Would there be any issue in using the 6804 in place of the 6811?

 

Thanks for the help,

 

Nick

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LTC4281 EEPROM problem

June 18, 2018, 10:43 am
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Hello,

 

we have a problem with LTC4281. In EEPROM stored 0x55, 0xAA, 0x55, 0xAA ..... values, and it can not be changed over i2c.

RAM registers are changing after i2c transactions by MCU just fine, but EEPROM registers ignore it.

We checked WP pin, it is pulled-down.

Could you please explain how to write to EEPROM registers?

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AD9173 - issues with STPL test and not outputting data on DAC1

June 22, 2018, 3:20 pm
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I've used the AD9173 Eval FMC with both the USB interface in "standalone" mode, and on an KC705 HPC FMC.  The "serial port configuration over SPI" works reliably, we have validated this. I am experiencing two curious behaviors which suggest maybe my eval board has bad silicon.

1- When I put the chip in DC test mode with the main NCO programmed at 1GHz, and the two amplitude registers set to 0x50ff, DAC0 will output the tone as expected, DAC 1 will not.  However, if I setup the Channel NCO to output a tone, both DACs behave correctly.  Is this normal behavior?  This is behavior is consistent whether I use our own software or the FMC plugged into USB with ADI ACE.

2- We are using the DAC in dual JESD link mode.  The PRBS test succeed, the link setup and stabilize.  I get CGS, FS, CHECKSUM, and ILA bits set for the links and lanes in use.  I have the proper JESD mode configured and when I poll registers 0x450 and on, it reports the proper settings from the JESD transmitter.  When I run short_tpl test, it always passes... even when I program the check registers with a bad value!  However, if I don't disable the test mode as described in step 9 of the data sheet on page 44 of the STPL test, it always fails, even with the right test pattern programmed.  Furthermore, the chip will randomly not output data on DAC1 (or DAC0).  All of the status regs (470-473) show a good link, and registers 4b0 - 4b7 show good links as well, and the sync out is solid high (view it on chips cope).  We've run out of options.  We are suspecting the silicon on the sample board may be bad. We would like to know if there is any status which we can read that ensures the DAC is streaming data on both ports?  To remedy the problem, without reprogramming the device, we enter the PRBS test mode on the JESD links.  Incidentally, both links show pass and 0 error count on all lanes, and when we return from the test, the DACs successfully stream data.  We thought it might have to do with an overflow/underflow condition, so we even check the FIFO status bits, and they both show that we are neither empty nor full, so the DAC is definitely able to keep up with the data flow. 

3- Some other observations:  we are using physical lanes 4-7.  4 and 5 are link 0, with the crossbar sending them to logical lane 0 and 1 for link 0.  Lanes 6 and 7 are mapped to logical lane 4 and 5 supplying lane 0 and lane 1 of link 1.  Again, every register that we can think of that shows status suggest we have a working link.  We just can't verify proper streaming.  For our test, the main NCO for each DAC is set to 1GHz, and the Channel NCO FTW is set to 0.  However, we have both main and channel NCOs configured to use the NCO because we have complex interpolation (24x) enabled (JESD MODE 3 with 8x and 3x interp for main and channel), so we are consistent with the data sheet (reg 112 bit 3 and reg 130 bit 6 are set) and we can verify proper behavior (when the chip is working).  From the init, the boot loader successful flag is set (reg 705), the DAC PLL is locked (register 7b5), the DAC DLL is locked (register c3), DACs all complete calibration (register 52), the JESD mode is valid (register 110), the FTWs load (register 113), and SERDES PLL lock (register 281).

Incidentally, all register addresses are in hex.  Just to clarify.

Please advise on how to determine the silicon is behaving as it should.  Thank you!

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AD9783-DPG2-EBZ FPGA Reference Design

May 22, 2018, 5:52 pm
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I'm attempting to use the AD9783-DPG2-EBZ evaluation board with a ZCU102 FPGA board but I don't see any reference designs for an FPGA. We're on a very tight schedule, is there a reference design available or one for a similar part?

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Only some GPIOs work with supplied SDK

May 31, 2018, 1:16 pm
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I can control Port 4, pin 0 or 1 quite well but when it comes to Port 1, Pin 5, it always goes back to high. 

 

I am enabling the pull up, setting the output enable and input enable before pulling it high or low through the supplied functions then looking at the outputs. 

 

Do you know why I can't set Port 1 Pin 5 to be low continuously? When I set it low, and then sense the input, it immediately reads high. 


This does not happen with the other port I tested Port 4 Pin 1 or 0. 

 

Please help me understand how to set GPIO Port 1 Pin 5 low continuously. 

 

Thanks. 

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