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Could not update the AD9371 filter profile

June 7, 2018, 6:21 am
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Hii

I am trying to update the filter profile of 20/100/40  with MATLAB Profile Generator for AD9371 [Analog Devices Wiki] 

generated profile files which is attached.

but am getting the error like

 

[  208.859644] ad9371 spi1.0: deframerStatus (0x21)

[  208.867465] WARNING: 136: Mismatch detected in MYKONOS_jesd204bIlasCheck()

[  208.876555] ad9371 spi1.0: ILAS mismatch: c7f8

[  208.883185] ad9371 spi1.0: ILAS lanes per converter did not match

[  208.891467] ad9371 spi1.0: ILAS scrambling did not match

[  208.898931] ad9371 spi1.0: ILAS octets per frame did not match

[  208.906900] ad9371 spi1.0: ILAS frames per multiframe did not match

[  208.915286] ad9371 spi1.0: ILAS number of converters did not match

[  208.923574] ad9371 spi1.0: ILAS sample resolution did not match

[  208.931592] ad9371 spi1.0: ILAS control bits per sample did not match

[  208.940118] ad9371 spi1.0: ILAS bits per sample did not match

[  208.947897] ad9371 spi1.0: ILAS checksum did not match

 

My previous filter is configured for 75/200/100.

I am able to update the files of 40/200/100 bandwidth and getting the exact bandwidth.

 

Please suggest whats wrong with it?

Is it the problem of AD9371 kernel file which is used in my Peta-Linux project  or in the filter profile generation.

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ADAU1962 Popping noise after Power-ON

May 22, 2018, 12:37 am
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Dear Team,

Initially popping noise is observed at ADAU1962 DAC output after enabling Master Power-Up bit of  PLL_CLK_CTRL0

register. Please find the attachment for ADAU1962 configuration code.

Could you please share the your feedback on this issue.

 

Hardware: ADSP-SC589 EZKit

Tools: CCES 2.7.0

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ADAU1962A Pop-up noise after Power-ON

May 24, 2018, 2:39 am
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Dear Team,

Initially pop-up noise is observed at ADAU1962A DAC output after enabling Master Power-Up bit of  PLL_CLK_CTRL0

register. Please find the attachment for ADAU1962A configuration code.

Could you please share the your feedback on this issue.

 

Hardware: ADSP-SC589 EZKit

Tools: CCES 2.7.0

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Question about LTC6813

June 10, 2018, 10:54 pm
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Hi All,

 

My battery spec is as follows.

- Battery total voltage: 378V, The number of cells: 120,  Voltage per cell: 3.15V (3.15Vx120=378V)

I cosinder to use 8 x LTC6813 to monitor each cell voltage. 8 x LTC6813s are connected in series and one (1) LT6813

monitors 15 cells as attached.

Any problem, especially high voltage is applied to upper LTC6813s, about this connection?

 

Regards,

Kazu

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ADV7604 DVI receiver damage

June 8, 2018, 5:06 am
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Hello,

We developed display controller card with ADV7604 with UXGA resolution with DVI and VGA interface. In DVI path we used ESD chip also.

 

When doing hot-plug the DVI cable with board power, some time the dvi receiver portion gets damaged. Any pin on input differential line is getting short with ground. Still now 4 ICs gone out of 20. All failures show similar effects in different differential input pin and resistance with ground like 2, 8, 180 ohms. After this there will not be any video output from IC through DVI input, but VGA works fine. Can you explain why this failure happens while doing in hot-plug the DVI cable?

 

Now we are redesigning this board. What precaution we have to take care apart from ESD protection?

Please guide us.

 

Regards,

Bala

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(ADV7281A)Datasheet revision change Rev0 to RevA

June 4, 2018, 5:15 pm
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Hi

 

I found ADI changed ADV7281A datasheet.

Rev.0

Rev.A

***************************************************************************************************************

Q1)

Why ADI changed this value?


Q2)

Which is correct? 0.2mm? 0.25mm?

http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp-32/CP_32_12.pdf 

This says the value is 0.25mm.

 

Q3)

Our customer will use ADV7281A and ADV7282A.

ADV7282A's document says the value is 0.25mm.

Is this value correct? Or 0.2mm is correct?

 

Q3)

Did ADI changed lead frame?

***************************************************************************************************************

 

Please answer this as soon as possible.

Maybe this will cause some problem at our customer.

 

Best regards.

Kawa

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Envelope Generator (ADSR) block for ADAU1701

May 9, 2016, 6:21 am
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Hi Guys,

 

an Aida DSP user builds analog synthesizers, he is curious about

the possibility to use ADAU1701 to realize some of the common blocks found in popular old analog synths.

One of the building blocks is the ADSR, I've found an excellent documentation about it here.

ADSR.gif

I know for more powerful processors (like ADAU144x which is supported by Aida DSP library) have Signal Envelope

block available, but for the smaller ADAU1701 there isn't.

The block needs six inputs:

  • Gate In
  • Trigger In (optional, to retrigger envelope after attack is complete)
  • Attack duration
  • Decay duration
  • Sustain duration
  • Release duration

And one output

  • Audio Envelope Out

 

Anyone has an idea on how to do it from scratch in Sigma Studio? I'm thinking about realizing time constants (capacitors) with first order low pass filters, but I don't know if there are other ways so I'm asking the community.

The final project and Arduino sketch will be available to the community here and on github.

 

Thank You

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ON pin of multiple ADA4870

June 7, 2018, 10:07 am
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Hello,

 

We have built a board with several ADA4870 working in parallel. These opamps share the ON pin for activation/protection purposes. I recently found two questions in the AD forums dealing with a shared signal for several ON pins:

 

Link1: https://ez.analog.com/thread/92651-ada4870-in-parallel-protection-features

Link2: https://ez.analog.com/thread/92633-ada4870-short-circuit-protection-using-issue

 

During regular operation the ON pins are floating. When one of the amplifiers detects a shortcircuit, it seems that its ON pin sets a voltage that drives the ON pin of the remaining active amplifiers.

 

According to the answer of Link2, the ON pin floats between Vee+1.8 and Vee+2.4V. However, I do not understand why this range falls within the values setting a power-down in the amplifier (ON pin between Vee+1.8V and Vee+5V, according to the datasheet).

 

Link2 also states that the ON pin voltage is set to Vee+1.71V when a shortcircuit is detected. This value is too high to set a low state in the ON pin of the other amplifiers, and too low to disable them. It is difficult to predict the behavior of this voltage driving the ON pins of the amplifiers.

 

According to the datasheet, the ON pin is simply modelled as a 20kΩ resistor. However, the behavior explained above seems more complex. Do you have any model or explanation that helps to understand how the ON pin behaves?

 

Thank you in advance,

 

Victor M.

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Unable to use the GUI for ADRF6602 (ADRF6x0x) on Windows XP/7/10.

June 10, 2018, 11:25 pm
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The Evaluation Board is not detected by the GUI, even after it is recognized by the PC. Hence, the PC is unable to communicate with the GUI.

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sine wave generator using ADAU1777

November 8, 2017, 6:44 am
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Hi everyone,

 

I am working on ADAU1777. I would want to know if there is any way to create a sine waveform generator by connecting the DAC output to unused ADC input.

 

Thank you,

Alekhya.

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Why is limiter is getting "stuck"

May 23, 2018, 11:07 am
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I am using Sigma Studio SHARC 3.14 + CCES. 2.3.0  targeting a SHARC 21489 DSP.

I have a pretty large project that uses a mix of filters, compressors, limiters, delays, mixers, etc. 

The project compiles and runs with spare memory and processing overhead.

 

All objects are working properly except the limiter.  The limiter is using default values - but when the threshold is hit - the output signal becomes permanently attenuated to the limit value.  So if the input signal is say 5db over therhsold, the signal will forever be attenuated by 5db.  It does not seem to reset.

I can verify it is specific to limiter by bypassing the limiter.

 

The compressors function as expected, and I suppose I could change out limiters to compressors - but these take up more resources.

 

Is there anything that I should look at that could be the cause of this behavior?

 

Thanks,

 

Ryan

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Can I design a variable frequency filter for a Wah Wah effect?

February 20, 2014, 3:53 pm
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Hey guys.

 

I am trying to design a Wah Wah effect for guitar using the 1701 evaluation board. The textbook I'm using shows a signal flow graph that has a time varying band pass filter with variable center frequency. A direct mix of the input signal is summed with the input going into the filter. I have tried to use the ADC 3 potentiometer and a VCO into the filter, but this doesn't change the frequency. I've tried to search for other posts, but I don't think I've found anything. So is it possible to use the potentiometer to vary a filter's frequency at all?

 

Thanks for any help. I can provide the graph and my program file if needed.

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The ADV7403 evaluation Tool from the FTP(ftp.analog.com) are corrupted.

June 11, 2018, 12:02 am
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I have download The ADV7403 evaluation Tools from ftp.analog.com and tried to unzip these files. But a zip file(ADV_Register_Control_Ver_7.0_Installation_ADV7403.zip) is corrupted as below.

Is any body know any web site where I can get this tool?

 

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How do you install the linux driver for the AD7768?

June 10, 2018, 7:24 pm
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HMC856 Delay Measurement

June 11, 2018, 12:09 am
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Dear Forum,

 

I recently acquired a HMC856 EVAL board - for characterization purposes of course. Now I'm interested in measuring the actual delay values per step as accurately as possible in order to characterize the chip for my desired application. I need to know the additional delay of each step as exactly as possible.

 

Now I'm wondering: what is the best/most exact way to measure the delay? I'm using an oscilloscope (20 GS/s) and it's not possible to simply measure the time increment of each single step due to oscilloscope jitter. The signals I'm measuring have a very low RMS jitter (<< 200 fs as measured with a phase noise analyzer) and are in the frequency range of 0-5 GHz.

 

How did ANALOG (or Hittite) measure the values given in the datasheet? Any hints or tips on how to measure these time delays would be very much appreciated. Maybe salemdar can give any tips?

 

Best Regards,

Michael

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AD9361 device initialization error in no os driver

May 3, 2018, 11:13 pm
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How to set the value for "GPIO_RESET_PIN " in parameter.h of no OS driver. I have set the value as '0' as i thought it is the reset signal for the AD9361.We use zed board with FMCOMMS2 board. When we run in hardware, it gave the error as "un supported product ID" while executing the  "ad9361_init(&ad9361_phy, &default_init_param);" command in main.c.

I have attached below the error message snapshot. 

Also how we have to map the GPIO pins  given in the following code of no OS driver(xgpiops.h) with that of the device in the board used(like zed board, picozed board )

-------------------------------------------------------------------------------------- 

#define XGPIOPS_BANK0 0 /**< GPIO Bank 0 */
#define XGPIOPS_BANK1 1 /**< GPIO Bank 1 */
#define XGPIOPS_BANK2 2 /**< GPIO Bank 2 */
#define XGPIOPS_BANK3 3 /**< GPIO Bank 3 */

#define XGPIOPS_MAX_BANKS 4 /**< Max banks in a GPIO device */
#define XGPIOPS_BANK_MAX_PINS 32 /**< Max pins in a GPIO bank */

#define XGPIOPS_DEVICE_MAX_PIN_NUM 118 /*< Max pins in the GPIO device
* 0 - 31, Bank 0
* 32 - 53, Bank 1
* 54 - 85, Bank 2
* 86 - 117, Bank 3
*/

----------------------------------------------------------------------------------------------------------

In zed board-FMcomms2 board, Ad9361 reset pin is connected to bank 35(pin number A16).

Thank you

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Could AD9643 or AD9684 inputs support the negative voltages?

June 5, 2018, 7:52 am
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Hello guys.

I decide to design a data acquisition system with AD9643 or AD9684 ADC and ZYNQ FPGA.

My question is : could this ADC support the negative voltage values in inputs and how to design the system that support both negative and positive values.

Thanks.

 

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Interfacing Kintex-7 FPGA to AD-9172 DAC EBZ board.

June 8, 2018, 10:28 am
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Hello,

 

I am trying to do a basic design before making a jump to the Microblaze. I have implemented the following block design in Vivado. I am using a ROM to store the data samples and a counter attached to it. The ROM is reading out the data samples to the Xilinx JESD204B IP core which is configured for 8 lanes per link. I am using the same configuration the other side i.e on the DAC. I am trying to interface Kintex-7 series (not Ultrascale) FPGA to AD9172 dual link DAC. I just want to test the design and hence I am going with this basic approach. Later, I plan to make the use of Microblaze Soft Core Processor and a BRAM. The problem now is I have implemented the design and have generated the bit file for it. I have programmed the FPGA and the AD9172 DAC EBZ board is attached to the FMC connector present on the board. I have configured the AD9172 for the same configuration Single link - Mode 11 i.e. 8 Lanes per link and in Subclass 1 mode. I have connected the signals as it appears in the design below and I am still not able to get the output on the DAC0. I am wondering whether I have made the right connections or am I missing some signals which are to be connected. 

 

Clocking wizard output: 100 Mhz for clk_out1 and clk_out2. All other signals on the left side except the diff_clock_rtl are coming from the AD9172 DAC board. I am just connecting the jesd204_0 txp and txn to the SERDES +- 0 to 7. Please let me know if I am missing something. 

 

I would appreciate the help. 

 

Loukik Pingle

 

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AD9102/AD9514 Clock Problem

June 11, 2018, 12:50 am
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Hello, I want to 40khz sine wave using AD9102/AD9514.

 

i have some problem in operation Waveform Generator Clock.

(I choose clock source 180Mhz crystal(XLL336180.000000I).)

 

 

 

i attached oscilloscope file and schematic . Please refer followings;

 

 

please check and send to me for confirmation.

 

thank you.

 

Best regards,

Tak Young

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Synchronization of RTC delays my return to hibernation for too long

May 27, 2018, 8:50 pm
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I have a custom Blackfin 533 design which can be hibernated. During hibernation, only VDD RTC is available. Wake Up from hibernation is successfully provided by an interrupt from the RTC on its 1 Hz tick. After a wakeup, my specification requires me to test for the presence of a known analog signal. This is implemented by a short section of proprietary code and isn't important to this discussion but takes about twenty milliseconds.  If the signal isn't present, I need to update the RTC for my next wakeup and return to hibernation as quickly as possible. Wakeups are periodic and may be at 1s intervals but could be anything from 2 s to 60 s periodicity depending on the user. 

 

My problem is that writes to the RTC are synchronized to the 1 Hz RTC clock (Fig 16-2 in the BF-533 hardware reference). If I write to the RTC registers and then shut down VDDINT power, my writes will be lost since they haven't yet been written from the shadow registers to the permanently powered RTC VDD powered registers. Uselessly looping until the write is confirmed means wasting battery power for 1 s - (Boot time + 20 ms). Since my application is battery powered and deployment duration is a hotly contested marketing feature, how can I return to the hibernation state immediately after my test without having to wait for the next 1 Hz tick to shift my next wakeup time into the RTC registers.

 

I understand why the synchronization of RTC writes was implemented but do you have any suggestions of how I can circumvent having to wait for the next 1 Hz tick?

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