Hi All,

I want to design a high-performance frequency synthesizer using discrete VCO, PFD and frequency divider. HMC385, HMC984 and HMC983 seem good components for my design. The tunning voltage of HMC385 is from 0 to 10 volts.

I was wondering that, is HMC984 (digital phase-frequency detector with integrated charge pump) capable of providing this tunning voltage?

The maximum charge pump supply of HMC984 is 5.5v. So it doesn't seem it could provide the required tunning voltage for HMC385.

Should I use active loop filters with appropriate passband gain to provide the required tunning voltage?

Is it recommended to use HMC385 in a PLL?

Thanks in advance,

Jack

Hello,

I am having issues with transmitting a CW tone using the RadioVerse TES software (version 2.0.68) with TES SD card image for AD9371 dated 11-30-2016. Both of these items were obtained from this page and assumed to be the latest available files. I am using the ADRV9371-W/PCBZ eval board with Xilinx ZC706. When connecting for the first time, I was prompted to update platform files, which i did.

The first issue is that I cannot run TX_QEC calibration. When attempting to program I receive the error shown in the image below. The specific error is ERROR during Mykonos.getInitCalStatus: ERROR:389, MYKONOS_getInitCalStatus() returned an ARM error while getting the init cal status information

If I program without TX_QEC calibration, the device programs successfully. However, the transmit waveform is very weak. I have a CW tone set at 0 dBFS with 0 dB attenuation, but the output tone is barely above -70 dBm on a signal analyzer. See images below for CW transmit tone and spectrum analyzer

If I generate a signal much less than -20 dBFS, I cannot even pick it out of the noise floor. 

I'm not entirely sure if my issues are with the TX_QEC calibration, or something else with the transmitter. 

Thanks!

Hi there

this is my first time here. Please be forbearing if i am doing anything wrong. :-) I am developing a solar charger to charge an 48V LIPO battery with a solar module using the LT8490. By now i am testing the (selfmade) board and it is not looking good. :-(

Testresults: The LT8490 seems to work as the status LED is blinking once (0.25s) every 3.5s. The fault LED is off. I tested the fault LED by using a 12V battery and then the fault LED showed an under-voltage fault as expected in the datasheet. The problem is, that the LT8490 is not charging although the status LED suggests stage 1 charging.

I can not measure any clock signal at the CLKOUT-pin.

Here are the facts:

Battery Voltage: 36.97V

SolarPanelVoltage: 35.36V (I am using a power supply for the tests as the solar panels have not arrived yet)

(MPP is supposed at 37V, open circuit is supposed at 48V)

INTVCC = 6.34V

SWEN = 0.72V

IMON_OUT = 0.7V (but there is no current. Actually imon_out is a pwm-signal from 0V-3.3V with a period of 27.4ms and a high-time of 6ms)

IMON_IN = 0.146V (i think this is normal as the imon_in circuit has an measurement offset of 7mV and there is no current flowing)

CSPOUT = 36.97V

CSNOUT = 36.97V

CSPIN = 35.36V

CSNIN = 35.36V

VBAT = 36.97V

VIN = 35.36V

TG1 = 0V

BG1 = 6.34V

TG2 = 0V

BG2 = 0V

FBIR/FBIN = 1.54V

FBOUT/FBOR = 1.2V

BOOST2 = 5.92V

BOOST1 = 5.92V

FBIW = 2.53V

I am using 4 pieces of IPT007N06N FET's.

I am using 2 CMMR1U-02 TR diodes between GATEVCC and BOOST1/2

MODE is tied to an external 3.3V source.

The input feedback network is configured for 60V using the resistor / capacitor values from the datasheet.

The stage 2 voltage limit (Vs2) is set to 48V.

Charge current limit is set by a poti to 4.8A.

Input current is limited to 20A.

TempSense is not used. (11.5k and 10k resistors)

I attached the essential part of the schematic as the hole board contains way more than just this circuit. Please be aware that i canceled some parts from the schematic for the tests. You will know once you take a look at the schematic.

Please help me finding the bug. I am searching for days and cant find it. It is getting really depressing. I think i am making some very basic mistakes because of some misunderstanding. (My English could be much better) Thanks a lot for every helpful comment!

Hi, I have purchased AD-FMCADC2-EBZ board and JESD204B license.

I'm going to use it with Xilinx's VC707 because it is one of supported carriers.

Since I'm a beginner in this field, I have a few basic questions.

1)
ADI AD-FMCADC2-EBZ Boards & Xilinx Reference Design [Analog Devices Wiki]  

at first I tried to use the above page. I think 'Quick Start Guide' is not still available.

In the No-OS software section, there's 'AD-FMCADC2-EBZ main driver' but it's not available now.

I think the link should be replaced with IT. am I right? and So do the 2nd,5th,6th links (platform, jesd drivers).

And here is the question..

this page says, 'The no-OS software contains a quick demonstration of the programming, RF conversion and data capture.'

This is exactly what I want to do. I want to monitor the signal using ILA.

Then I think I need to use the no-OS software. But I could't find any guidelines explaining how to use it.
Do I have to download all drivers in the no-OS software section? Is there any guide page for No-OS software?

Actually, the meaning of 'no-OS' is still confusing to me. When I followed this link to build HDL from here, I could make 'hdf' file. And I could see a Microblaze processor if I open the Vivado project file(.xpr) made. 

Then is it different from no-OS software since there 'IS' an OS?

2) 

AD-FMCADC2-EBZ FMC Board [Analog Devices Wiki] 

This is another guide page for FMCADC2. It has 'Linux' section. and this link (Linux on the VC707)

I'm using Windows 10. Do I need to switch my OS? Is it okay to use Cygwin instead?

In this page, there is 'Microblaze Quick Start Guide' which seems to be an opposite version of no-OS software.

I want to know the difference between this and this.  Which one is more recommendable for me?

I even wonder whether I understand the concept..

Thanks in advance.
Sorry for many questions. 

Hi,

We are using the ADRV9371 /ZC706 evaluation platform to play out waveforms through the AD9371. The waveform buffer on the evaluation platform is currently limited to about 4M samples. We have a need for longer waveforms. Our FPGA engineer says the waveform buffer is implemented by a DDR controller which looks like it is programmed to read out buffers of up to 2^24 bytes from the DDR memory. He says it can theoretically programmed in "2D" mode where it can handle N rows of 2^24 bytes.

As the software writer I am not sure where to start. I currently use the IIO library to access this buffer:

• iio_device_create_buffer() to create the buffer
• iio_buffer_first()  to get pointers to the start of I and Q channels
• iio_buffer_push() to start playing the waveform out.

This works very well.

How do I get access to lower level devices, drivers or registers to program the DDR controller allow longer buffers?

Or is there another way of achieving what we need?

Thank you

I've been working on building a port for the AD9739A-FMC Analog code, for the AC701 Xilinx board.

After working through all the necessary changes (I think), including part name, board name, constraints Vivado version number etc...

I have tried to run make as the first step to creating the project, using Cygwin on windows.

However, I believe it does not complete its execution, and it seems to reference products that have not been created.

I have attached the output (if there is a way to create a verbose log file of this, please let me know).

Please help...

Owner@Quantum /cygdrive/c/Users/Owner/Documents/adi/hdl
$ make -C projects/ad9739a_fmc
make: Entering directory '/cygdrive/c/Users/Owner/Documents/adi/hdl/projects/ad973 9a_fmc'
#-make -C zc706 all
make -C ac701 all
make[1]: Entering directory '/cygdrive/c/Users/Owner/Documents/adi/hdl/projects/ad 9739a_fmc/ac701'
make -C ../../../library/axi_ad9739a
make[2]: Entering directory '/cygdrive/c/Users/Owner/Documents/adi/hdl/library/axi _ad9739a'
rm -rf *.cache *.data *.xpr *.log component.xml *.jou xgui *.ip_user_files *.srcs *.hw *.sim .Xil
vivado -mode batch -source axi_ad9739a_ip.tcl >> axi_ad9739a_ip.log 2>&1
make[2]: Leaving directory '/cygdrive/c/Users/Owner/Documents/adi/hdl/library/axi_ ad9739a'
make -C ../../../library/axi_clkgen
make[2]: Entering directory '/cygdrive/c/Users/Owner/Documents/adi/hdl/library/axi _clkgen'
rm -rf *.cache *.data *.xpr *.log component.xml *.jou xgui *.ip_user_files *.srcs *.hw *.sim .Xil
vivado -mode batch -source axi_clkgen_ip.tcl >> axi_clkgen_ip.log 2>&1
make[2]: Leaving directory '/cygdrive/c/Users/Owner/Documents/adi/hdl/library/axi_ clkgen'
make -C ../../../library/axi_dmac
make[2]: Entering directory '/cygdrive/c/Users/Owner/Documents/adi/hdl/library/axi _dmac'
make -C ../util_axis_fifo/
make[3]: Entering directory '/cygdrive/c/Users/Owner/Documents/adi/hdl/library/uti l_axis_fifo'
make -C ../util_cdc/
make[4]: Entering directory '/cygdrive/c/Users/Owner/Documents/adi/hdl/library/uti l_cdc'
rm -rf *.cache *.data *.xpr *.log component.xml *.jou xgui *.ip_user_files *.srcs *.hw *.sim .Xil
vivado -mode batch -source util_cdc_ip.tcl >> util_cdc_ip.log 2>&1
make[4]: Leaving directory '/cygdrive/c/Users/Owner/Documents/adi/hdl/library/util _cdc'
rm -rf *.cache *.data *.xpr *.log component.xml *.jou xgui *.ip_user_files *.srcs *.hw *.sim .Xil
vivado -mode batch -source util_axis_fifo_ip.tcl >> util_axis_fifo_ip.log 2>&1
make[3]: Leaving directory '/cygdrive/c/Users/Owner/Documents/adi/hdl/library/util _axis_fifo'
make -C ../util_axis_resize/
make[3]: Entering directory '/cygdrive/c/Users/Owner/Documents/adi/hdl/library/uti l_axis_resize'
rm -rf *.cache *.data *.xpr *.log component.xml *.jou xgui *.ip_user_files *.srcs *.hw *.sim .Xil
vivado -mode batch -source util_axis_resize_ip.tcl >> util_axis_resize_ip.log 2>& 1
make[3]: Leaving directory '/cygdrive/c/Users/Owner/Documents/adi/hdl/library/util _axis_resize'
make -C ../util_cdc/
make[3]: Entering directory '/cygdrive/c/Users/Owner/Documents/adi/hdl/library/uti l_cdc'
make[3]: Nothing to be done for 'all'.
make[3]: Leaving directory '/cygdrive/c/Users/Owner/Documents/adi/hdl/library/util _cdc'
rm -rf *.cache *.data *.xpr *.log component.xml *.jou xgui *.ip_user_files *.srcs *.hw *.sim .Xil
vivado -mode batch -source axi_dmac_ip.tcl >> axi_dmac_ip.log 2>&1
make[2]: Leaving directory '/cygdrive/c/Users/Owner/Documents/adi/hdl/library/axi_ dmac'
make -C ../../../library/axi_hdmi_tx
make[2]: Entering directory '/cygdrive/c/Users/Owner/Documents/adi/hdl/library/axi _hdmi_tx'
rm -rf *.cache *.data *.xpr *.log component.xml *.jou xgui *.ip_user_files *.srcs *.hw *.sim .Xil
vivado -mode batch -source axi_hdmi_tx_ip.tcl >> axi_hdmi_tx_ip.log 2>&1
make[2]: Leaving directory '/cygdrive/c/Users/Owner/Documents/adi/hdl/library/axi_ hdmi_tx'
make -C ../../../library/axi_spdif_tx
make[2]: Entering directory '/cygdrive/c/Users/Owner/Documents/adi/hdl/library/axi _spdif_tx'
rm -rf *.cache *.data *.xpr *.log component.xml *.jou xgui *.ip_user_files *.srcs *.hw *.sim .Xil
vivado -mode batch -source axi_spdif_tx_ip.tcl >> axi_spdif_tx_ip.log 2>&1
make[2]: Leaving directory '/cygdrive/c/Users/Owner/Documents/adi/hdl/library/axi_ spdif_tx'
make[1]: *** No rule to make target 'ad9739a_fmc_ac701.sdk/system_top.hdf', needed by 'all'. Stop.
make[1]: Leaving directory '/cygdrive/c/Users/Owner/Documents/adi/hdl/projects/ad9 739a_fmc/ac701'
Makefile:10: recipe for target 'all' failed
make: [all] Error 2 (ignored)
make: Leaving directory '/cygdrive/c/Users/Owner/Documents/adi/hdl/projects/ad9739 a_fmc'

Should the marking be 787A or H787A?

Is this old revision correct? (see the last page) HMC787ALC3BTR datasheet(18/18 Pages) AD | Conversion loss: 9 dB typical at 3 GHz to 9 GHz 

Today there is a new revision of this datasheet and there is 787A. I think it's correct.

But we have old supply of 2016.

A similar case has already been: HMC3587LP3 ;  What is the correct package marking , H3587 or 3587, datasheet has contradictory information? 

Our application is SERDES limited, and needs to operate on the fewest lanes possible. Could the AD9635 lane rate be pushed 2.5% to 6.665Gbps?

Hello community,

Can you please help me to figure out best solution for firmware downloading in BF 531 processor in production environment?

Due to mishandling and other issues, ICE 1000 emulators gets short circuited with production team. Is there any cost effective solution to update firmware in BF 531 processor?

Can you give me some idea about isolation between debugger and computer, so that it can't get short circuit? 

Greetings,

I'm trying to get a PicoZed SDR to transmit samples generated by me.

I downloaded the reference design of the PicoZed SDR from the git repository site of the analog. I also downloaded the No-OS software. Through the No-OS software, I can generate a signal at a desired frequency. What I intended now was modulate my samples instead of modulating this signal.

In Vivado (In the block desing) there is a block of the AD9361 and with  IQ pins and is these are connected to a FIFO.

I turned off Fifo's inputs and plugged them into my system where my samples are generated. I compiled, programmed the FPGA but the AD9361 continues to transmit the signal it transmitted before the system was changed by me.

I have little experience with FPGA, I only started working with them a few months ago but I think in this case there is a registry that allows to change the signal that is being transmitted to my samples that are entering on  the IQ ports in AD9361. However I can not find. Can someone point me in the right direction? Maybe I'm even thinking badly and the problem is not what I'm thinking, but right now I'm out of ideas.

Thank you for you're time.

ad9361; picozedsdr

I have a board that is daisy chaining 4x AD7765's and have it happily working in DEC_RATE = 0 (256x), BUT I cannot get 128x to work correctly.

Q1: What level do I set DEC_RATE to 128x? Do I drive it high or set it floating?

Here is a trace of it running in 128x where I have driven DEC_RATE = high

The bottom 4 signals contain the 4 channels parallel data where the LS status byte is set to 98'h

From AD7765 data sheet:

FILTER-SETTLE = '1', DEC_RATE 1 = '1', Don't care = '1' = 98'h

So, the 4x ADC's appear to think they are in 128x decimation.

Q2: Why is the NFSO timing incorrect? (i.e. the same as 256x decimation) Unless I misunderstand, NFSO should be running at double the rate. (i.e. no gap between CH1-4 sample bursts)

Note: If I set DEC_RATE to float I get 90'h (i.e. Don't Care = '0')

Thanks for any help!

I intend to use the HMC952ALP5GE Amplifier; and i need to choose a bias controller for it. i've seen on the website that there's two Bias controller that can work with this amplifier (HMC980 and HMC980LP4E) since they both provide a Vdd=5 and Idd up to 1.6mA.

But on these bias controllers datasheet there's a table at the end of the document showing the amplifiers it can work with. but i can't find the one i want to use? did i overlook a criteria for choosing a bias controller?

Thank you in advance.

Hello,

My company is designing acquistion board and we targeted AD9253 as its ADC. We will use FPGA to configure ADC and PLL and to retreive data from it. Due to the limit of available pins on our FPGA I want to minimize interfaces as much as possible.

I read AD9253 datasheet and I don't understand if SDIO and SCK pins can be shared among AD9253 and other devices(for example AD9510). I also read AN-877.

SDIO and SCK pin have other function when not used in SPI mode.

For example.

AD9253 in SPI mode

    AD9253 has  its own CSB pin(not shared )    ; lets call it ADC_CSB

    AD9510  has  its own CSB pin(not shared )   ; lets call it PLL_CSB

    SCK shared between AD9510 and AD9253

    SDIO shared between AD9510 and AD9253

If ADC_CSB is set temporary set high and PLL_CSB set low, and SDIO and SCK data streamed to write/read to/from AD9510.

Will that data on SDIO and SCK signals be interpreted as OLM and DTP(Lane pin setting and digital test pattern settings) in ADC?

Kind Regards,

Vedran

Hello all,

I wondered if it is possible to set the I2C addresses of components manually in Sigma Studio. In my project I have some DC generators I want to set every 100ms which I have to do with safeloads. But I can only set one DC generator at a time with one safeload. It would be nice to have the option to set three or four components in one safeload, that would spare a lot of I2C hardware transmission time :-) The DSP I use is ADAU1450

Any suggestions?

With kind regards,

Reini

Hi All,

I want to design a high-performance frequency synthesizer using discrete VCO, PFD and frequency divider. HMC385, HMC984 and HMC983 seem good components for my design. The tunning voltage of HMC385 is from 0 to 10 volts.

I was wondering that, is HMC984 (digital phase-frequency detector with integrated charge pump) capable of providing this tunning voltage?

The maximum charge pump supply of HMC984 is 5.5v. So it doesn't seem it could provide the required tunning voltage for HMC385.

Should I use active loop filters with appropriate passband gain to provide the required tunning voltage?

Is it recommended to use HMC385 in a PLL?

Thanks in advance,

Jack

Hi All,

I'm looking for a suitable attenuator covering the following low frequency range.

- Digital step and 6 bits DSA

- Attenuate 21dBm or 12 dBm input  to 10dBm

- Input signal frequency range is from 400kHz to 100MHz

Please take a look at the attached attenuation performance of the four parts. HMC624A shows flat attenuation

until very low frequency. Does HMC624A cover my requests, or do you have better part?

is AD-FMCOMMS5-EBZ compatible with Xilinx zcu102?

Can i use AD8369 at 500 MHz? 

What is the performance of AD8369 at 400 MHz &  500 MHz. 

like :

Voltage Gain
Gain Flatness
Noise Figure
Output IP3
IMD3
HarmonicP1dB
Distortion 

............ Please let us Know 

Hi all,

Our customer will be going to select power IC, mult ch output.
They will be concerned the output coupling, and switching noise.

In the datasheet LTC3633A, page 12 "OPERATION" say following.
"One potential disadvantage to this configuration occurs when one channel is operating at 50% duty cycle.
In this situation, switching noise can potentially couple from one channel to the other, resulting in frequency jitter on one or both channels.
This effect can be mitigated with a well designed board layout."

Why occur to couple at 50% duty cycle ?
, and the condition is 50% duty cycle only ?

Best regards,
sss