Hi,
I have very strange problem with allocating memory to sdram. I am using DMA descriptors to switching memory banks where PPI is saving data.
When Im using : #pragma section ("sdram_bank0") i got only zeroes after PPI handler is executed.
When Im using :#pragma section ("sdram_bank1") everything works fine.
Any ideas why is that?
Regards
Adam
Hi !
i'm looking for a possibility to fold C/C++ code in CCES
for different given sections like
{
}
is there any Feature planned/possible or plugin available ??
Kind regards
Chris
Hi, I'm trying to understand the Short Transport Layer (STPL) Testing for the AD9164. As far as I can tell, I'm following the directions in the AD9164 datasheet, under "Transport Layer Testing", but when I check the SHORT_TPL_FAIL register at the end of the test, the result is always 0 (indicating a pass), even when I force a failing condition.
My JESD configuration is L=8, M=2, F=1, S=2. I confirm that the DAC has accepted these and achieved sync through register reads.
Here is the process I'm following:
Per steps 1 and 2, I start by establishing link and then setting my JESD transmitter (in an FPGA), to send a constant repeating set of 16 samples: A5B4, FFFF, FFFF, FFFF (repeated 4 times)
Step 3: I next set DAC Register 0x32E = 0xCC and Register 0x32D = 0xDD, which should tell the DAC that to expect a sample with a value of CCDD (which is deliberately wrong)
Step 4-6: I then follow the next steps to select sample 0 of DAC 0, enable the test, and reset the test:
Register 0x32C = 0x00 # select sample 0, DAC 0
Register 0x32C = 0x01 # enable test mode
Register 0x32C = 0x03 # reset
Register 0x32C = 0x01 # remove reset
Step 7: I then wait 10 seconds and then set register 0x32C = 0x0 to end the test.
Step 8: When I then read register 0x32F (SHORT_TPL_FAIL) I always get a value of 0x0, indicating a pass. I've tried this with multiple value for the expected sample and for the values sent from my transmitter in the FPGA, and the result is always 0 (passing).
Is there anything I'm doing wrong or interpreting wrong? I'd like to run this test as a double check that I'm formatting the sample data correctly.
Hi,
I have modified ad9361-iiostream example so that I could transmit data samples from a file and write received data to another file. I transmit a frame 6 times in a loop and the result I get is attached. My settings are:
frequency- 5 GHz, BW- 20 MHz, sampling rate- 20MSam/s, AGC in fast attack mode.
When I took fft of the first frame received, I noticed a large dc component (figure attached). I know that AD9361 AXI core implements dc correction in receive chain. Is there anyway that I can suppress this dc component?
-Suranga
Hello,
In our application we would like to use a mix of wall adapter and also solar panels. In a quick search, we find a part number, with I2C communication, which we consider interesting because it has an intern Coulomb Counter. However, looking at the applications, we find that the voltage output of the LTC4015 is not regulated. Our load can not be fed with high voltages such as solar panels. On the other hand, we would not like to feed directly from the battery, since we would lose PowerPath and gas gauge measurement. Is there any other part number that could supply us, or is there any way to regulate the SYS output voltage of the LTC4015?
Thanks in advance!
Joao
Hi,
I am using ADA 4571 IC for angle measurement. I have connected the IC to Data Acquisition Card and observing its output via Lab View. The problem that i am facing is that the two outputs i.e. Sin and Cosin are not out of phase by 90 degree as describe in Data Sheet. So, how can i resolve this do i have to built any external circuitry for making it correct. Kindly, help me how to resolve this problem.
Is the HMC546MS8G MMIC Falsafe Switch control line TTL or CMOS compatible?
Is it possible to read the Pixel packing phase of the general control packet in the ADV7619?
This is required to put in order in the 5 fragments received for 4 pixels in 10bits deep color on the 2x24 output bus.
Hi,
I'm having some trouble configuring the ADC subsystem of the ADuCM3029. I'm using the ADICUP3029 board and CrossCore Embedded Studio.
I choose channel 2 for a single conversion.
Although I set ADC_IRQ_EN.CNVDONE to 0x01, I'm waiting ADC_STAT.DONE2 to be set, but this bit is never 1.
What am I doing wrong?
===
/*
* ADuCM3029_Project_Test__ADC_Config.c
*
* Created on: 26 de jan de 2018
* Author: tiago.dezotti
*/
#include <sys/platform.h>
#include "ADuCM3029_Project_Test__ADC_Config.h"
#include "ADuCM3029_Project_Test__TMR_Config.h"
uint16_t config_ADC(void)
{
config_samptime(SAMPTIME);
powerup_adc();
program_adc();
return(0x0033);
}
uint16_t powerup_adc(void)
{
enable_powerup_adc();
set_powerup_wait_adc();
set_vref_adc();
set_refbuf_adc();
enable_adc();
config_3_5_ms_timer();
wait_3_5_ms_timer();
clear_ready_adc();
start_cal_adc();
return(0x0033);
}
uint16_t program_adc(void)
{
uint16_t adc2_value = 0x0000;
select_channel_adc(SEL_CHANNEL_ADC);
enable_int_adc();
start_conv_adc();
wait_conv_done_adc();
adc2_value = read_data_adc();
clear_flag_done_adc();
disable_adc();
return(adc2_value);
}
uint16_t config_samptime(uint8_t samp_time)
{
*pREG_ADC0_CNV_TIME |= samp_time;
return(0x0033);
}
uint16_t enable_powerup_adc(void)
{
//Set the ADC_CFG.PWRUP bit (0) to power up the ADC.
*pREG_ADC0_CFG |= 0x0001;
return(0x0033);
}
uint16_t set_powerup_wait_adc(void)
{
uint32_t clock_div = 0x00000000;
//Set ADC_PWRUP.WAIT bits as 526/(CLKG_CLK_CTL1.PCLKDIVCNT field).
clock_div = *pREG_CLKG0_CLK_CTL1 & 0x00003F00;
clock_div = clock_div >> 8;
*pREG_ADC0_PWRUP = 526/clock_div;
return(0x0033);
}
uint16_t set_vref_adc(void)
{
//Select 1.25 V as reference voltage using the ADC_CFG.VREFSEL bit (1).
*pREG_ADC0_CFG |= 0x0002;
return(0x033);
}
uint16_t set_refbuf_adc(void)
{
//Assert the ADC_CFG.REFBUFEN bit (2).
*pREG_ADC0_CFG |= 0x0004;
*pREG_ADC0_CFG1 |= 0x0001;
return(0x0033);
}
uint16_t enable_adc(void)
{
//Assert the ADC_CFG.EN bit (4).
*pREG_ADC0_CFG |= 0x0010;
return(0x0033);
}
uint16_t clear_ready_adc(void)
{
//Write 1 to clear the ADC_STAT.RDY bit (15).
*pREG_ADC0_STAT |= 0x8000;
return(0x0033);
}
uint16_t start_cal_adc(void)
{
uint16_t wait_adc_cal = 0x0000;
//Set the ADC_CFG.STARTCAL bit (5) to start the calibration cycle.
*pREG_ADC0_CFG |= 0x0020;
//Wait ADC_STAT.CALDONE bit (14).
wait_adc_cal = *pREG_ADC0_STAT & ADC_CAL_BIT;
while (wait_adc_cal != ADC_CAL_BIT)
{
wait_adc_cal = *pREG_ADC0_STAT & ADC_CAL_BIT;
}
return(0x0033);
}
uint16_t select_channel_adc(uint16_t sel_ch)
{
//Set ADC_CNV_CFG.SEL bits (7-0) and select channel for conversion (for instance, channel 2).
*pREG_ADC0_CNV_CFG |= sel_ch;
return(0x0033);
}
uint16_t enable_int_adc(void)
{
//Set ADC_IRQ_EN.CNVDONE = 0x1 to enable interrupt when conversion is done.
*pREG_ADC0_IRQ_EN |= 0x0001;
return(0x0033);
}
uint16_t start_conv_adc(void)
{
//Set ADC_CNV_CFG.SINGLE bit (14) to start the conversion.
*pREG_ADC0_CNV_CFG |= 0x4000;
return(0x0033);
}
uint16_t wait_conv_done_adc(void)
{
uint16_t wait_adc_ch2_conv_done = 0x0004;
//Wait ADC_STAT.DONE2 bit (2).
wait_adc_ch2_conv_done = *pREG_ADC0_STAT & ADC_CH2_CONV_DONE;
while (wait_adc_ch2_conv_done != ADC_CH2_CONV_DONE)
{
wait_adc_ch2_conv_done = *pREG_ADC0_STAT & ADC_CH2_CONV_DONE;
}
return(0x0033);
}
uint16_t read_data_adc(void)
{
//Read ADC_CH2_OUT.RESULT to read the conversion result.
return(*pREG_ADC0_CH2_OUT);
}
uint16_t clear_flag_done_adc(void)
{
//Set ADC_STAT[0] to clear the interrupt.
*pREG_ADC0_STAT |= 0x0001;
return(0x0033);
}
uint16_t disable_adc(void)
{
*pREG_ADC0_CNV_CFG &= 0xFFEE;
return(0x0033);
}
===
===
/*
* ADuCM3029_Project_Test__ADC_Config.h
*
* Created on: 26 de jan de 2018
* Author: tiago.dezotti
*/
#ifndef ADUCM3029_PROJECT_TEST__ADC_CONFIG_H_
#define ADUCM3029_PROJECT_TEST__ADC_CONFIG_H_
#define SAMPTIME 0x80
#define ADC_RDY_BIT 0x8000
#define ADC_CAL_BIT 0x4000
#define ADC_CH2_CONV_DONE 0x0004
#define SEL_CHANNEL_ADC 0x0004
uint16_t config_samptime(uint8_t);
uint16_t enable_powerup_adc(void);
uint16_t set_powerup_wait_adc(void);
uint16_t set_vref_adc(void);
uint16_t set_refbuf_adc(void);
uint16_t enable_adc(void);
uint16_t clear_ready_adc(void);
uint16_t start_cal_adc(void);
uint16_t powerup_adc(void);
uint16_t select_channel_adc(uint16_t);
uint16_t enable_int_adc(void);
uint16_t start_conv_adc(void);
uint16_t wait_conv_done_adc(void);
uint16_t read_data_adc(void);
uint16_t clear_flag_done_adc(void);
uint16_t disable_adc(void);
uint16_t program_adc(void);
uint16_t config_ADC(void);
#endif /* ADUCM3029_PROJECT_TEST__ADC_CONFIG_H_ */
===
Dear Community Team,
I construct a simple magnitude measurement of signal source to obtain frequency and amplitude sweep response. I used No GUI, Run to Completion so that I can add/modify generated python code in order me to add python features, like numpy , matplotlib etc.. The initial structure as shown in figure below.
Then I developed a program and run the python script and successful plotted as what I’m expected.
Now I just add FMCOMMS2 sink and source as shown in figure below.
Basically its just add those two blocks and some modification on self.connect. Overall program is similar as initial program above.
Now the problem is the program is wait forever/hang up after execute the python script.
Then I find the possibility root cause is tb.wait() where my program is stuck here after I add iio_fmcomms2 blocks as shown in following figure.
If I disable/remove iio_fmcomms2 block and restore connection without fmcomms2 block, I able to run again without a problem.
There is something parameters should I define on fmcomms2 block? Buffer size maybe ? I also referring to https://gnuradio.org/doc/doxygen/page_operating_fg.html for tb.wait() issue.
Fyi backgound: Zedboard + FMCOMMS2 , running on VM Ubuntu 32 bit, Remote PC connection
Best Regards,
I'm trying to set analog LPF bandwidth by using rxProfile->rxBbf3dBCorner_kHz = 50000; however, it seems not to applied(frequency response still the same with the bandwidth = 100MHz). What is right way to set this bandwidth?
I'm currently running a basic flow graph
Sig Source -> Complex to IShort-> FMComms2/3/4 Sink
Samp Rage = 3M Attenuation Tx1 = 0
LO Freq= 2.46Ghz Attenuation Tx2 = 0
RF Port Select = A
RF BW = 20M
When I execute the flow graph I get
" Fontconfig warning: ignoring C.UTF-8" not valid language tag
Using Volk machine: neon hardfp"
>>>>> Done (return code -9
The flow graph doesn't execute.
Any Ideas on a fix??
I would like to obtain the reference design data and application notes for the ADATE320.
Also, is there a newer model that operates at a higher speed?
The ADClk signal seems to be coupling to VINR. The layout has these two traces on the opposite side of the 4 layer PCB. Any other ideas on how this can be removed?
Using the external reference the voltage difference (CAPB-CAPT) appears to be half of the range set to 4V or 2V (so capb-capt = 2V or 1V respectively). Shouldn't the voltage difference be equal to the range setting or is there some additional gain of 2 on the input signal? This is all with the gain set to 1.
Also is there a recommended value for CAPB and CAPT relative to the input signal? The video signal input level we have is about 300-760mV depending on the imaging device used. Previous posts seem to indicate it should be around the input signal level, but that doesn't seem to be the case here.
For both cases we are operating in 1-10 MHz range.
Hello.
Could anyone tell what SNR has AD9736? Thanks.
I just purchased an EVAL-ADAS1000SDZ for a project. I would like help configuring it so it can measure respiratory rate using just two electrodes.
Hello
Can we get a working script for the ADV7511 with the default values for all the registers and the setting of the relevant registers we need to configure for the below setting:
The input video (BT656):
OUTPUT (HDMI):
Thanks
Freddy
I'm trying to understand the AD9694 - according to the datasheet, "By default, the AD9694 is configured to use four converters and four lanes."
However, it looks like that is *total* number of lanes, and that the device actually uses 2 lanes per *link*, and 2 converters per *lane*.
Is this correct, or am I way off?
Thanks all!
The EVAL-ADL5240 features an USB interface. It is somehow unclear on how one could communicate with it with software of our own. As I could gleam by having a quick look at the drivers, an unfortunate Cypress USB chip has to be spoken to on an extremely low level. Eventually there are 8 pins to be controlled on the ADL5240.
In what kind of time frame is the planned Analog Devices SDP board to be expected ? And what functionality is to be expected ?
In the meantime I'd prefer to feed my own SPI signal, perhaps through the connector to the future SDP board. Is it assumed, that the Cypress USB chip is high impedance while not connected, meaning I can just provide the signals required by the ADL5240 in a static manner, without an additional disable signal to the cypress ?
Hi,
I am facing couple of issues with CN0326 design.
Problem 1: With custom board and as well as CN0326 dev board. The code is written in C for a micro-controller to use SPI communication. The same steps have been followed as per the reference code. First the temperature is calculated. The I try to read the PH but then it fails. Same happens if I read PH first and then the temperature. Basically changing the channel is having some issue. So currently I have a work-around i.e. I initialize AD7793 everytime before I read either temperature or the PH.
WORK AROUND
CN0326_CalculateTemp();
delayVar = 50000;
while(--delayVar);
AD7793_Init();
delayVar = 50000;
while(--delayVar);
CN0326_CalculatePH();
AD7793_Init();
delayVar = 50000;
while(--delayVar);
Problem 2: Temperature reading also doesn't work as expected. It reads out a huge value. I have to read repeatedly till I get the value in the permissible range. Only then It works for me. Example as below.
do{
CN0326_CalculateTemp();
delayVar = 50000;
while(--delayVar);
}while((temperatureVal > 60.0)|| (temperatureVal < -10.0));
Problem 3: Now I have several custom boards. The PT100 RTD is same. But each boards behave differently. The temperature variations between boards are in the range of + or - of 10 degree centigrade. I have followed almost same guidelines as in the development board. Not sure what is the issue.
Please help.
Thanks and regards,
Girisha.