We are trying to power down complete receive path of AD 9364. Could we use   ad9361_set_en_state_machine_mode  API to power down RX path.

-Thanks,Deepak

I would like to connect AD9361 to a DSP with SERDES interface. I am planning to design an interface board to route the digital interface from FMCOMMS3 board to a DSP board with AMC interface.

1. Assuming we are only receiving from AD9361. Is it possible to use SERDES interface with AD9361? 

2. Which DSP board is suggested for AD9361? I can only see suggestions for FPGA boards.

Thank you

We are using DM388 SOC Display out which is connected to AD723 Encoder

What are the supported input resoltion for AD723?

We are Valitated the RGB out from DM388 to VGA conncetor it working fine.

The same RGB passed to AD723 for S-video conversion but We are not getting desired output

Connection:

DM388 -> THS7360 -> AD723 -> S-video display

AD723 Configuration:

4FSC - 14.31818MHz

TERM          - "0"
STND          - "1"
chip enable   - "1"
South America - "0"

Regards,

RAJM

I am using the AD9162-FMCC-EBZ eval board with the Xilinx KCU105 eval board. The JESD link fails to establish about 90% of the time after initialization and setup, but once it establishes, I get the DAC output I expect. When the link fails to establish, I continually "reset" the entire system (FPGA, Xilinx JESD core, and 9162) until the link establishes. I'm pretty sure all clocks are setup successfully; my sense is that something in the JESD link is marginal.

My startup and initialization process (on power-on and post-reset) is the following:

1. Initialize the onboard ADF4355 to output 5760 MHz. I do not believe this step ever fails.

2. Initialize the onboard AD9508. I do not believe this step ever fails.

3. Initialize the JESD FPGA core. This step involves writing registers to the core and issuing a soft reset. I do not continue past this step until the JESD core informs me that it has successfully reset.

4. Initialize the AD9162. This step involves writing data to all the registers via the SPI interface. 

Here are some other data points:

1. The PLL is locking. I have an LED that lights when locked, and it is always lit

2. The values in registers 0x470, 0x471, and 0x473 contain random values when initialization and setup fails, even from retry to retry.

3. The value in register 0x472 tends to be 0xFF even during a failure to setup correctly. 

4. The values in registers 0x4B0-0x4B7 are random from reset to reset.

So here is my question: What are the most likely causes of the inconsistent initialization, and what are the fixes most likely to work? Which registers should I monitor or modify? Any advice would be appreciated.

Hai ,Can any one suggest an ic to generate negative reference voltage for AD5545 to get positive o/p voltage from DAC of range 0 to 5V.

Hi there,

I'm having some issues reading from the AD7934. I will firstly describe my configuration, and then state the issue.

I have the ADC on a custom PCB, talking to an FPGA board over some trailing wires, not great for noise, but it mostly seems okay.

My ADC is configured W/B mode set to Word.

Post control register configuration, I set CS and RD low permanently so the output data bits are always driven with the latest data.

I have CLKIN free running. My CONVST falls on the first rising edge to kick off the conversion, the busy signal is detected to rise on the first (next) falling edge.

This is where I start to have a series of intermittent and linked issues. The busy signal should fall on the 14th falling edge of CLKIN. It normally does and a new reading is detected, however sometimes one of two things happen. Firstly the busy signal will fall on the 13th rising edge, not the 14th falling edge. Secondly, the busy signal will fall on the 13th rising edge and then rise again on the 14th falling edge. It will stay risen until the CONVST signal goes high again to end the conversion. I'm not sure what would happen if I delay the rising edge of the CONVST signal. When the busy signal is in the incorrect place, no new conversion is observed on the data bits.

I am not sure if this is due to some timing issue, if I'm not complying with figure 34 in the datasheet somehow. Could it be a noise or manufacturing issue on the PCB as it is intermittent?

Linked are some screenshots from my oscilloscope, The green trace is CONVST, yellow is BUSY, and red is CLKIN

A normal conversion, with busy signal rising on 14th falling edge of CLKIN. A new reading is achieved.

The busy signal falls on the 13th rising edge of CLKIN, and then rises again on the next falling edge. No new reading is achieved.

The busy signal falls on the 13th rising edge, but does not rise again. No new reading is achieved.

Any ideas?

By the way, I only have access to a terrible analogue scope for the next week, so if you want any new traces, they won't be so pretty.

EDIT. I appreciate that in the example in the pictures, the CLKIN signal is <700kHz, which is too low according to the datasheet, but this still happens if I put the frequency up.

Hello,

         I am working onEVAL-SDP-CH1Z and EVAL-AD7768-4FMCZ boards. I want to test more functions on these boards. Please give me source code for these boards.

My mail id is: sandeep@rioshtech.com

Please reply fast.

Thanks and Regards

Hello,

         I am working onEVAL-SDP-CH1Z and EVAL-AD7768-4FMCZ boards. I want to test more functions on these boards. Please give me source code for these boards.

My mail id is: sandeep@rioshtech.com

Please reply fast.

Thanks and Regards

Dear ADI Support Team,

Few days ago we received an #EVAL-AD9789 with QAM generation on-board, for my customer #Telkom-Telmor in Poland.

Unfortunately, it does not work properly.

Attached please find two pictures, one with the board, second with configuration.

Here goes more details on the issue:

- photo of the generator board after connecting all the wires - as you can see, only the yellow LED D1 is lit, while the XD1 diode is off

- screenshot of the configuration panel of the application to operate the generator after all operations have been carried out in accordance with the "Quick Start Guide"

Our comments:

- no waveform and voltage on the XY1 quartz

- MCU (PIC) has 5V power on all pins

- on lines USB_D- and USB_D + there are no waveforms, no signal can be measured

- connecting the eval to the computer does not activate system drivers; it seems to us that the computer cannot see the board (in the application of the generator there is no information about the connected unit),

- blue fields in the configuration panel of the application, despite following the instructions, do not change the content after pressing the RUN button; it seems to us that there should be answers from the generator / board

I appreciate your prompt reply and support on that case!

Thanks & Regards,
#Michal #Mazurkiewicz

Solution FAE at ARROW Poland

Hi,

AD5421 datasheet say that the DAC have to be loop-powered. But if loop is broken the AD5421 stops to communicate via SPI.

Is the any possibility to power AD5421  digital domain only to maintain SPI communication?

What happens if IODVdd pin will be connected to separate external power supply (or battery)?

Regards,

Ivan

Hi all, I would like to ask some questions regarding ZSDR Comms – AD9361. I am currently working on the controlling the AD9361 fast attack AGC.

According to the AD9361 UG-570 Reference Manual (p.g. 46). Our baseband can use EN_AGC control pin to unlock and restart fast AGC (when it is already running) so that it can re-lock to a new gain index. We have RF front end gain that needs to be adjusted to command the reset of fast AGC.

EN_AGC control pin is available on our custom board and we also have software to pull the EN_AGC high. However, when we pull the pin high, nothing happens to fast AGC. We do not see any of the following takes effect through the dedicated control out pins:

1) Gain Lock goes low;

2) Rx Gain changes;

3) AGC state changes;

Prior to this we have AGC that works fine in unlocking and locking the gain depending on various overloads conditions.

We followed UG-570 to set bits in 0x0FB[D6], 0x111[D5] and clear bits in 0x110[D6:D5] so that the gain is set maximum once AGC restarts. So the question is why pulling EN_AGC high have no effect on fast AGC.

Kindly advise if I have missed out any steps in configuring the AD9361 fast AGC.

Hello,

my custom board has a device that generates the clock for the AD9363, the device is programmable so during the unit boot it's not programmed and the kernel module prints this warning " Calibration TIMEOUT (0x287, 0x2)".

After the clock init, I have added a call to the "debugfs initialize", I have checked the RSSI and this call seems to be sufficient.

Now, I need to read also the chip temperature but I have found this post How to use the temperature sensor on ad9361 device correctly ? .

Is it possible to call other "debugfs" or "sysfs" attribute(s) to perform the needed initializations (executed during the driver loading) without remove (and re-add) the driver itself?

Thanks and Regards,

Ramon

When using external temperature sensor with AD7745/46/47 CDCs, what is the formula to use in order to convert the reading into temperature?

I've seen in "EXTERNAL TEMPERATURE SENSOR" section of datasheet that "The AD7745/AD7746 are factory calibrated for Transistor 2N3906 with the ideality factor nf = 1.008", but I just couldn't get any right temperature using external 2N3906 and the formula "Temperature(°C)= (Code/2048) − 4096", even trying to compensate by nf = 1.008. Maybe I didn't find the right way to use nf in the formula.

For instance, I've got a reading of 8478826 using external 2N3906, which is about 44˚C by the formula above, while internal sensor gives 8459790 that indicates  34.75˚C. A reference thermometer indicates ambient temperature around 29˚C.

Is it necessary to re-calibrate the part to get an external 2N3906 reading?

Regards.

Hello team,

I'm looking forward to design an ultrasound imaging system using phased array transducers(preferably 2D). I need to figure out the best AFE design for my need. I assume that AD9670  + HSC-ADC-EVALCZ Data Capture Board

would be suitable for interfacing the transducer.

I have a few queries

1. Do you provide any interfacing solutions on the transmitter side,say some sort of a pulser board ?

2. Is there a custom ASIC/ EVM that provides a complete interfacing solution(transmission+reception) for the ultrasound transducer.If not, what would be best way to assemble one ?

3. As far as AD9670 is concerned,  is there any input  specifications for the transducer to be used with it ?

4. What all imaging modes are available with PC visual analyzer software ?

I'm very new into this domain and please excuse if the query lacks clarity.

Thanks in advance

Jayadev

Hi,

I'm having some trouble configuring the ADC subsystem of the ADuCM3029. I'm using the ADICUP3029 board and CrossCore Embedded Studio.

I choose channel 2 for a single conversion.

Although I set ADC_IRQ_EN.CNVDONE to 0x01, I'm waiting ADC_STAT.DONE2 to be set, but this bit is never 1.

What am I doing wrong?

===

/*
 * ADuCM3029_Project_Test__ADC_Config.c
 *
 *  Created on: 26 de jan de 2018
 *      Author: tiago.dezotti
 */

#include <sys/platform.h>

#include "ADuCM3029_Project_Test__ADC_Config.h"
#include "ADuCM3029_Project_Test__TMR_Config.h"

uint16_t config_ADC(void)
{
    config_samptime(SAMPTIME);

    powerup_adc();

    program_adc();

    return(0x0033);
}

uint16_t powerup_adc(void)
{
    enable_powerup_adc();

    set_powerup_wait_adc();

    set_vref_adc();

    set_refbuf_adc();

    enable_adc();

    config_3_5_ms_timer();

    wait_3_5_ms_timer();

    clear_ready_adc();

    start_cal_adc();

    return(0x0033);
}

uint16_t program_adc(void)
{
    uint16_t adc2_value = 0x0000;

    select_channel_adc(SEL_CHANNEL_ADC);

    enable_int_adc();

    start_conv_adc();

    wait_conv_done_adc();

    adc2_value = read_data_adc();

    clear_flag_done_adc();

    disable_adc();

    return(adc2_value);

}

uint16_t config_samptime(uint8_t samp_time)
{
    *pREG_ADC0_CNV_TIME |= samp_time;

    return(0x0033);
}

uint16_t enable_powerup_adc(void)
{
    //Set the ADC_CFG.PWRUP bit (0) to power up the ADC.
    *pREG_ADC0_CFG |= 0x0001;

    return(0x0033);
}

uint16_t set_powerup_wait_adc(void)
{
    uint32_t clock_div = 0x00000000;

    //Set ADC_PWRUP.WAIT bits as 526/(CLKG_CLK_CTL1.PCLKDIVCNT field).

    clock_div = *pREG_CLKG0_CLK_CTL1 & 0x00003F00;

    clock_div = clock_div >> 8;

    *pREG_ADC0_PWRUP = 526/clock_div;

    return(0x0033);
}

uint16_t set_vref_adc(void)
{
    //Select 1.25 V as reference voltage using the ADC_CFG.VREFSEL bit (1).

    *pREG_ADC0_CFG |= 0x0002;

    return(0x033);
}

uint16_t set_refbuf_adc(void)
{
    //Assert the ADC_CFG.REFBUFEN bit (2).

    *pREG_ADC0_CFG |= 0x0004;

    *pREG_ADC0_CFG1 |= 0x0001;

    return(0x0033);
}

uint16_t enable_adc(void)
{
    //Assert the ADC_CFG.EN bit (4).

    *pREG_ADC0_CFG |= 0x0010;

    return(0x0033);
}

uint16_t clear_ready_adc(void)
{
    //Write 1 to clear the ADC_STAT.RDY bit (15).

    *pREG_ADC0_STAT |= 0x8000;

    return(0x0033);
}

uint16_t start_cal_adc(void)
{
    uint16_t wait_adc_cal = 0x0000;

    //Set the ADC_CFG.STARTCAL bit (5) to start the calibration cycle.

    *pREG_ADC0_CFG |= 0x0020;

    //Wait ADC_STAT.CALDONE bit (14).

    wait_adc_cal = *pREG_ADC0_STAT & ADC_CAL_BIT;

    while (wait_adc_cal != ADC_CAL_BIT)
    {
        wait_adc_cal = *pREG_ADC0_STAT & ADC_CAL_BIT;
    }

    return(0x0033);
}

uint16_t select_channel_adc(uint16_t sel_ch)
{
    //Set ADC_CNV_CFG.SEL bits (7-0) and select channel for conversion (for instance, channel 2).

    *pREG_ADC0_CNV_CFG |= sel_ch;

    return(0x0033);
}

uint16_t enable_int_adc(void)
{
    //Set ADC_IRQ_EN.CNVDONE = 0x1 to enable interrupt when conversion is done.

    *pREG_ADC0_IRQ_EN |= 0x0001;

    return(0x0033);
}

uint16_t start_conv_adc(void)
{
    //Set ADC_CNV_CFG.SINGLE bit (14) to start the conversion.

    *pREG_ADC0_CNV_CFG |= 0x4000;

    return(0x0033);
}

uint16_t wait_conv_done_adc(void)
{
    uint16_t wait_adc_ch2_conv_done = 0x0004;

    //Wait ADC_STAT.DONE2 bit (2).

    wait_adc_ch2_conv_done = *pREG_ADC0_STAT & ADC_CH2_CONV_DONE;  

    while (wait_adc_ch2_conv_done != ADC_CH2_CONV_DONE)
    {
        wait_adc_ch2_conv_done = *pREG_ADC0_STAT & ADC_CH2_CONV_DONE;
    }

    return(0x0033);
}

uint16_t read_data_adc(void)
{
    //Read ADC_CH2_OUT.RESULT to read the conversion result.

    return(*pREG_ADC0_CH2_OUT);
}

uint16_t clear_flag_done_adc(void)
{
    //Set ADC_STAT[0] to clear the interrupt.

    *pREG_ADC0_STAT |= 0x0001;

    return(0x0033);
}

uint16_t disable_adc(void)
{
    *pREG_ADC0_CNV_CFG &= 0xFFEE;

    return(0x0033);
}

===

===

/*
 * ADuCM3029_Project_Test__ADC_Config.h
 *
 *  Created on: 26 de jan de 2018
 *      Author: tiago.dezotti
 */

#ifndef ADUCM3029_PROJECT_TEST__ADC_CONFIG_H_
#define ADUCM3029_PROJECT_TEST__ADC_CONFIG_H_

#define SAMPTIME 0x80
#define ADC_RDY_BIT 0x8000
#define ADC_CAL_BIT 0x4000
#define ADC_CH2_CONV_DONE 0x0004
#define SEL_CHANNEL_ADC 0x0004

uint16_t config_samptime(uint8_t);
uint16_t enable_powerup_adc(void);
uint16_t set_powerup_wait_adc(void);
uint16_t set_vref_adc(void);
uint16_t set_refbuf_adc(void);
uint16_t enable_adc(void);
uint16_t clear_ready_adc(void);
uint16_t start_cal_adc(void);
uint16_t powerup_adc(void);
uint16_t select_channel_adc(uint16_t);
uint16_t enable_int_adc(void);
uint16_t start_conv_adc(void);
uint16_t wait_conv_done_adc(void);
uint16_t read_data_adc(void);
uint16_t clear_flag_done_adc(void);
uint16_t disable_adc(void);
uint16_t program_adc(void);
uint16_t config_ADC(void);

#endif /* ADUCM3029_PROJECT_TEST__ADC_CONFIG_H_ */

===

Hi everyone,

in "Self-Test" part of ADXL357 datasheet it is noted that "Only the z-axis response is specified to validate device functionality". Does this mean that if the z-axis is working properly the other two are working as well or that only the z-axis is validated?

Best regards.

The datasheet AD5443 mentioned 'Power-on reset with brownout detection' as a feature but without any further details? Can more details be supplied? I have a design that if I power cycle too quickly (~2 seconds) then the DAC chip ignores the serial data-stream. Does the power rails need to fall to a low voltage to reset the chips logic?

Hi,

I would like to ask some questions on the AD5290 power supply.

Please refer to the AD5290 rev.c dataseet.

Q1:  From the old answers on this part,  I assume it is  characterized and specified only for

+/-15v operation.  If it is correct , does it mean no single suppy opeartion is guaranteed for performance

(characteristics ), but functionality?

Q2: If the part  is operated from +15v/-5v asymmetric supplies , in what and how much

of  device performance degradation  from +/-15v operation could be expected?

Q2: On the front page of the dataseet , it is said that 20V/0V  operation is possible  but ,on the other hand,

it is said 4.5v/0v operation is possible.

Which is the usable  voltage for single supply opeartion , 20v or 4.5V?

Best Regards,

Lux

Hi,

I have a design that utilizes the Xilinx UltraScale FPGA and using the 2016_r1 version of the HDL library and No-OS software

Since these primitives are not used by the digital tune function of the No-OS software to determine the clock and data delays, it is absolutely necessary to use the IDELAYCTRL and IDELAYE3 Xilinx UltraScale primitives to interface with a AD9361 with the 2016_r1 version of the HDL library?

Or can these primitives be bypassed and connect the rx_data and rx_frame differential signals directly from the AD9361 into the UltraScale FPGA without incurring any kind of unexpected consequences?

I look forward to your response.

- Brad