I have a custom carrier card that holds multiple ADRV9361s and one of the ADRV9361 boards suddenly stopped working after around 6 months of use. Upon power up, the config done LED will blink rapidly (~4Hz) and VCCIO_EN is never enabled. Probing deeper into the issue, I have discovered that a failure seems to have occurred somewhere on the SOM causing a short of the internal power rail VCCPCOM-1P8V to GND (~0.2 ohm). Does anyone have any experience with this particular failure mode?
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ADRV9361-Z7035 failure
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AD9161-FMCC-EBZ external clock
Hello, dear colleagues!
In addition to previous question - AD9161-FMCC-EBZ external clock commutation
In wiki it's noted, so the same error can be with AD9162XBCZ or AD9162XBCAZ,
AD916x-FMCx-EBZ Evaluation Board User Guide [Analog Devices Wiki] (External Clock Switch Doesn't Work)
but can it be, if the AD9161BBCZ is on the eval board.
Thanks!
P.S.
If the board can be re-programmed, where I can download new software?
Thanks!
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ADAU1372 anti-aliasing filter
Hi,
i am designing a system where i have to pass some strict frequency mask tests on the analog audio inputs/outputs. These tests include unwanted signals that are not within the first nyquist zone of an 192 kS/s ADC and therefore need to be attenuated somewhere. To get an understanding of what anti-aliasing/reconstruction filter i have to provide external to the ADAU1372 i have some questions:
- What is the sample rate of the delta-sigma ADC/DAC? (not the sample rate i get on the serial ports) From the following datasheet plot and from the fact that is is a delta-sigma converter i assume that the sampling frequency is (much) higher than 192 kS/s because otherwise the decimation filter could not provide attenuation at frequencies above 96 kHz.
- Can you provide the decimation filter-response up to the nyquist-frequency of the ADC/DAC?
- Are there any analog anti-aliasing or reconstruction-filters inside the ADAU1372?
Best Regards
Michael
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AD9653--EVALUATION BOARDS
Hi,
In my project, I use AD9653 as the High-speed ADC with a sampling clock at 80MHz.The reference voltage of ADC is 1V.The frequency of the analog signal(sin and cos ) are 40kHz，and the amplitude of the analog signals is 2Vpp(after difference).But the data I got have noise,so could you sent me the data collected by AD9653 EVALUATION BOARDS,the test conditions are in accordance with my project as much as possible . Then I can analyse the data and improve my PCB board.
My email is 875994877@qq.com.
Thank you !
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AD9683 SYNCINB inputs
On p.40 of the datasheet, address 0x60 bit 4 is described as using the SYNCINB- pin when in single-ended CMOS mode. We mistakenly have connected to the SYNCINB+ pin, and have bypassed the SYNCINB- pin to ground. Will the part still work correctly in this manner?
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Simple C example for AD7091R
I need to do some prototyping with an AD7091R-4 ADC to verify some HW design choices. I've been searching with minimal luck for an actual example in C of setting up and using the AD7091R over SPI.
I thought I had found one via links on the analog.com site, but looking closer at the code while it does kind of show interfacing using SPI it doesn't appear to match what the spec sheet for the AD7091R says.
I'm referring to ad7091r.c that is in teh ad_7091r_generic.zip and (other related examples).
Specifically the example I found doesn't appear to drive the CONVST# pin and also doesn't appear to be sending 16 bit values for things like configuring the chip.
I was planning on doing an initial test using an Arduino just to make sure I understand how to use the IC, then I need to move over to a USB to SPI bridge IC that is going to be used on the custom HW design. I've already developed working code for the the USB to SPI bridge and talking to other SPI devices using that.
I can roll my own following the datasheet, but it would be nicer to have a starting framework that is known to work.
So, can anyone point me to a good simple example bit of code for the AD7091R that actually looks like it was written for the chip?
Note: I'm using the AD7091R-4 eval board that was supplied to me, but it doesn't include the interface board so I'm having to use the test points to access SPI and other control lines.
Thanks,
Burt
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Interface an AD 9613 to a Xilinx Zynq 7020
Hi there -
I'm a PhD student working on a project that requires some fairly fast data acquisition and we have settled on the AD9613. We're trying to interface it with a zynq 7020 FPGA and I'm struggling to find specifics on how one goes about doing that. Could someone direct ?
I have a good deal of coding experience in c,c++, php, etc and did some FPGA programming in an undergraduate coursework but we didn't do much high speed ADC interfacing. What I really need is a few book recommends and perhaps some good tutorials (Modern ones, many of the ones I've found dont apply well w/ the Vivado 2017 suites). I've gone through the basic VHDL books, basic Zync interfacing, but haven't really found what I need for this particular thing.
Thanks!!
Roy S.
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AD9250-FMC-250EBZ with HSC-ADC-EVALEZ
Hi,
We have troubles when we connected AD9250-FMC-250EBZ with HSC-ADC-EVALEZ:
1, Following the QuickStart Document, in VisualAnalog, we select AD9250 Average FFT; but the SPIController can't access the AD9250, it seems the VisualAnalog select the wrong MCS FPGA file: ad9250_evaldz.mcs.
2, Then we manually select another MCS FPGA file: ad9250_evalez.mcs, the SPIController can access the AD9250, but still can't capture data, it reports error: The number of converters in the ADC settings [1] need to match the number of headers selected [2];
3, Then we removed Ch.B Output Data at ADC Data Capture Settings; it still report error: Read cannot be performed because FIFO is not ready for readback. We check the clocks from AD9250 board to Data Capture Board: FPGA_GLBCLK_P/N and GBTCLK0_P/N; They are all ok, and have the same 50Mhz frequency as the CLKIN_P/N input of AD9250.
We download ad9250_evalez.mcs from this page: EVALUATING THE AD9250/AD6673 ANALOG-TO-DIGITAL CONVERTERS [Analog Devices Wiki]
We highly doubt about the MCS file at this page have some mistake.
Whether a higher version of VisualAnalog can auto select a correction MCS file for AD9250-FMC-250EBZ, or is there any other MCS file we can get. And Can you send us the FPGA design source code for AD9250-FMC-250EBZ with HSC-ADC-EVALEZ?
VisualAnalog version: 1.9.46.16
SPIController version: 4.0.11.3
BR
DiLu
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AD9258 : SYNC Pin
If the SYNC pin is not used, is it recommended to connect to GND?Or is it NC?
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Controlling ADC conversion of LTC2145-12
Dear Sir
I am desiging the circuits using LTC2145-12 ADC. to avoid the noise conditins around ADC, I would like to start ad
conversion when input analog signal meets over the threshold level.
Data sheets saying that ENC clocking shall be done all the time , So AD conversion will not stop .
So How can I control the AD conversion like AD9826?
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Observed 6.8dB delta in amplitude flatness of AD9208
Hi,
Hi,
I am using AD9208 for one of my application. I am using AD9208-3000EBZ+ADS7-V2EBZ for the evaluation.
The AD9208 datasheet mentions the 3dB bandwidth of the ADC as 9GHz.
When I measure power on the ADC across the frequencies, I have got following values.
The measured power varies around 6.87dB across the frequencies.
Is this expected?
Since 3dB BW is 9GHz, The power measurement flatness for freq < 9GHz should be lower than 3dB. Is this understanding correct?
Freq (MHz) | RF Power Set on Keysight MXG Sig Gen (dBm) | MeasPower on ADC (dBFS) |
0.5 | -40 | -56.44 |
1 | -40 | -56.12 |
1.4 | -40 | -55.82 |
2 | -40 | -55.59 |
2.5 | -40 | -55.8 |
2.9 | -40 | -56.4 |
3.5 | -40 | -56.94 |
4 | -40 | -57.54 |
5 | -40 | -58.67 |
6 | -40 | -61.48 |
6.5 | -40 | -62.46 |
Max | -55.59 | |
Min | -57.54 | |
Delta (dB) | 6.87 |
Regards,
Dwijen Pandya
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Interleaving ADCs
John Reyland
Rockwell Collins, Inc, January 7, 2018
Do you think the following this will work for interleaving four AD9689s please?
Figure below shows first two ADCs of an interleaved four ADC design. ADC0 samples at 0deg and ADC1 samples at 90deg. Clk1 is 90 deg delayed from Clk0. ADC0 gets SysRef (SDClk0) aligned with Clk0.
Clk1 retimes SDClk0 to make a SysRef aligned with Clk1.
Here is the corresponding timing diagram:
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Regarding AD9208 JESD204b configuration parameters
Hi Everyone,
I am currently using the AD9208-3000EBZ which is interfaced with VCU118 (Virtex Ultrascale +) board.
I need to use both ADC cores (ADC_0 and ADC_1) on the AD9208 chip. Each core needs to operate at 3GSPS.
When I look at the schematics of the VCU118 boards and AD9208 boards, I saw that the 8 serial JESD204b output lanes DOUT[0:7] from the the AD9208-3000EBZ board are routed to two non-adjacent quads on the VCU118 boards (GTY121 and GTY126 quads; DOUT[0:3] is routed to the quad GTY121 and DOUT[4:7] is routed to the quad GTY126).
Because the quads are not adjacent to each other, they can not share the same reference clock. Therefore, in order to reliably transfer the ADC samples into the FPGA fabric, I need to place ADC_0 core's samples into lanes 0 to 3 (DOUT[0:3]) and ADC_1 core's samples into lanes DOUT[4:7]. Using this approach, the samples from each core only go to one quad and the we will not any issue related to different reference clocks. I am also not using any DDC (Digital Down Converter) on the AD9208 chip.
My question is how do i configure the AD9208 chip to make ADC_0 core samples go to lanes 0 to 3, and to make ADC_1 core samples got to lanes 4 to 7 ?
I am thinking to set the parameters like this: L = 4, M = 1, F = 2 ? But I am still not sure if my thought is correct. Or Do I have to set other parameters as well?
Also, it would be very much appreciated if you can share with me any C or C++ example codes to do AD9208 or AD9689 SPI configuration.
Thank you very much for your kind help and support.
Regards,
Anh
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AD7266
Hi,
Is there any VHDL/Verilog simulation model for the
AD7266 , Urgent!
AD7490 , Urgent!
ADS7952, Nice-to-have
Thanks
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Amplifying 40 - 80 uV with DC bias of at least 200 mV.
I am using the AD8428 in-amp and it is very sensitive to input resistance and hence the classical DC coupling as seen in the datasheet will not suffice because the thermal noise will become so high that it renders the signal undetectable. How can I get rid of this DC-bias without using a DC coupling with high-value resistors? Any ideas are greatly appreciated.
All the best.
Frederik
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Clock interface of AD9635
The clock for an AD9635 is from an FPGA PLL in LVDS. In this case, can I directly connect the PLL clock outputs to the clock inputs of AD9635 with capacitors and resistors without using a clock buffer such as AD951x in Fig 60 on page 22 of AD9635 data sheets? If yes, what is the input impedance, i.e. parallel resistors to ground and coupling capacitors? Many thanks.
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Arria 10 GX - Interaction with AD9625CE04B1-EBZ FMC card
Hello,
I configured with Arria 10 GX development kit. but, I recently had a problem. Arria 10 is broken.(maybe..)
I have referenced that AD9625 evaluation Borad quick Start guide...
When I switched on, the system died.
I think it has a probelm(12V on the C2M power can cause probelm.. from xilinx), so I need to modify the daughter card to configure this system. Is there a way..?
Thanks.
ps. I bought a new arria 10 gx development kit.
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Where can I find ad9613-250ebz hsc-adc-evalcz default ise program?
I was trying to find default program of ad9613-250ebz hsc-adc-evalcz board, but I couldn't find this in ftp.
So my question is, can I use ad9643 in ftp for default?
if not, where can I find this default program?
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Pipelined ADC burst mode
Hello,
Will this mode work correctly with any your pipelined adc?
Best Regards
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ADAS3022 Register Address Map
Hello there,
I'm currently developing a data acquisition solution using the ADAS3022 product. I can't seem to find the device's register address map in the datasheet or the device's main webpage.
The provided evaluation board support package provides a "adas3022.h" file which contains what look like register addresses, but it still very ambiguous as they are not commented.
Can you please provide the materials on the devices internal register addresses?
Many thanks
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