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I am having issues with getting the GNU Radio Audio sink to work properly when using ADRV1CRR-FMC carrier and SOM boards.

January 23, 2018, 12:23 pm
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Hello Engineering support,

I am having issues when attempting to output to the GNU Radio audio sink block. I opened the example FMradio.grc and copied the parameter audiodevice which has a value of "dmix:CARD=monitor,DEV=0" and copied the audio sink block into a new project. I used the wave file source block and pointed to a pre recorded wav file and routed it to the audio sink block. I was not able to hear anything out of the speakers. Also, I tried the signal source block with a variable assigned to the amplitude and frequency without any luck. I was able to route the signals( wav source, signal source) to a wav file sink block and then open the recorded files with VLC media player and play them back successfully. The parole media player outputted an error when attempting to play back the files. Error="GStreamer backend error Could not initialize supporting library".

My thoughts are that the device value "dmix:CARD=monitor,DEV=0" may be for another piece of hardware, but I was not able to track down what would be the correct device value for this board. 

 

Any assistance would be greatly be appreciated.

 

Regards,

Brian B.

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AD9361+ZedBoard+fmcomms3 remote linux host

January 19, 2018, 11:18 am
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Hello, I'm newbie in GNU Radio and Analog devices, I'm trying tu run the fm-transmitter example script on a linux host machine but i cant get the Zedboard to do anything.

 

I Have succesfully compiled and installed gnuradio using pybombs, libiio, libad9361-iio, gr-iio and iio oscilloscope using this instructions GNU Radio [Analog Devices Wiki] .

The iio oscilloscope works perfectly on the linux host machine connecting to the zedboard via LAN, but when i try to execute the GNU radio scripts the only error I get is "Error:failed to enable real-time scheduling." and the script seems to execute but it doesn't do anything on the Zedboard.

 

I'm attaching an image of my sink configuration, I hope anyone can help me with my problem.

 

 

Thanks.

 

Isaac

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ADXL355 - Frequency spectrum and Noise

January 23, 2018, 12:55 pm
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Hi,

 

I have two questions:

1) Regarding the internal low-pass filter of the ADXL355 (eval. board): If I understood the data sheet correctly, the filter cutoff frequency is at 1/4 of the output data rate (e.g. 62.5 Hz ODR -> 15.625Hz Filter corner frequency). However the frequency spectrum of my measured data shows features even at higher frequencies, where i would assume the filter response to be close to zero. It would be awesome if you could help me understand the cause of this.

 

2) Noise: The noise level along the z-axis of the accelerometer seems to agree with the theoretical value obtained from the noise density from the data sheet, however for the other two axis, the noise seems to be about a factor of 2 lower. Is this expected?

 

Thank you in advance

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Filter calculation ADAU1466 192kHz

January 22, 2018, 11:35 pm
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Hi,

we encountered a problem with the calcuation of filter coefficients with the ADAU1466.

With the ADAU1452 we convertet our values to fixedpoint with a constant 0x01000000 but this seems not to work with the 1466, instead we would have to use 0x00800000 like with the SIGMA200 series.

The same problem is also visible with the filter implementation in sigma studio itself. If you create a peak filter with a f0 of 1k, it comes up at 250Hz.

 

Additional to that, we saw that there is the wrong safe load address written in the export files (0x0000 instead of 0x6000 in this case).

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AD5934(EVAL-CN0349) output frequency problem

November 24, 2017, 6:13 am
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Dear All,

 

I have some problem with the output frequency on my EVAL-CN0349 board. I found out this problem in connection of my other issue(Measure conductivity below 25us with EVAL-CN0349 (AD5934) ).

So I measured the output frequency on my eval board and it seems that it cannot genarate the proper output frequency. The voltage is proper. So I started to debug my code to see if I made any mistakes. I found one and corrected it, now I can set the system clock bit in the control register just fine. The start frequency code is calculated and written into the device properly. I checked it. 
I want to set 30kHz but I only get  around 6kHz in case of internal clock(today I will try to measure the output frequency at more setpoints and I will refresh this post), the frequency increment works but also not properly. The device increments the frequency but not with the given value it seems. 

 

I started to read some discussions on the forums and I found the next:

 

AD5933: Initialize With Start Frequency Command Not Working 
in which snorlax states the following:

Also make sure that the chip is not the AD5934 - the version that does not have the internal oscillator. 

 

Now these confused me. Can somebody help me to clarify this?

Is there internal 16MHz clock in the AD5934? (According to its datasheet yes, and my setup works with the internal clock setting just the frequency is not proper)

 

As the  documentation of the circuit states(http://www.analog.com/media/en/reference-design-documentation/reference-designs/CN0349.pdf ) :

 

The frequency of the clock applied to the MCLK pin is set to
1 MHz using a stable, low jitter, FXO-HC536R-1 (U6) quartz
crystal oscillator. This oscillator allows the AD5934 to excite the
conductivity cell with a frequency of 2 kHz, which is well suited
for conductivity measurements.

 

Naturally I tried the measurements with the output clock but the output frequency is not good in this case either.

 

What else could I do to correct the output frrequency, or what should I check? I have checked the following things:

-clock setting in the control register OK

-start frequency code OK

-increment frequency code OK

-start frequency and increment frequency code write to the registers OK 

 

Thanks for the help!

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MISO held high

November 13, 2017, 7:22 am
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I am trying to interface an ADXL372 with Freedom board. I am able to talk to the ADXL372 i.e. able to read Device ID, Part ID etc.Most of the times it works fine. But sometimes, i see that the MISO is held high by certain commands e.g. when i send 0x03 i get the expected result, but after that MISO stays high till any other command is sent. The MISO will stay even after deselecting the chip (CS = high).

I don't have any other device connected to SPI.

Has anybody faced this issue?

 

Thanks,

Neeraj

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ADAU1701 /1401 Recommended Crystal Layout

January 21, 2018, 4:35 pm
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Dear Analog,

 

We have designed a system using the ADAU1701 and have experienced inconsistent communication to the unit over I2C and SPI. We have narrowed it down to the crystal oscillator being at fault.

It appears to be an identical issue to a previous post. https://ez.analog.com/thread/9384#33074

When we remove the 100R damping resistor the communications works.

 

Can Anolog please comment on our findings based on our layout below.

Is there an obvious flaw in our crystal circuit layout?

Is there a recommended PCB layout for the crystal, load capacitors and damping resistor?

Should the damping resistor value be changed?

 

We are following the recommendation on page 18 of the manual,

Fundamental Crystal, 18pF. (Abracon ABLS-12.288MHZ-B4-T). 22pF load capacitor and 100R damping resistor.

http://www.analog.com/media/en/technical-documentation/data-sheets/ADAU1701.pdf  

 

Our layout is shown below. It is a 4 layer stack with a ground plane directly under the DSP and crystal. There is no copper pour on the top layer

ADAU1701 crystal layout

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AD9375 DPD Model Size

January 23, 2018, 2:36 pm
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In AD9375 User Guide UG992, the API MYKONOS_restoreDpdModel(mykonosDevice_t *device, mykonosTxChannels_t txChannel, uint8_t *modelDataBuffer, uint32_t modelNumberBytes)  requires modelNumberBytes to be 172 bytes per channel.   But the API source code (Ver. 3566) downloaded from link below,

AD9371/AD9375 Evaluation Software | Design Center | Analog Devices 

 

In Mykonos.c, it requires the modelNumberBytes  to be 182 bytes per channel (See below).

 

Which one is correct?

 

/**

* \brief This function will allow loading of the DPD model file.
*
* This function writes a copy of the user's DPD model to ARM memory and instructs the ARM to install that DPD model
* into hardware. Note that initializing the device will over write DPD model data. Note that the DPD model being
* restored must match the PA for which it is configured. Restoring a DPD model to a different PA than for which it
* is configured will not yield the desired performance. The user is responsible to insure the DPD model matches the
* PA configuration.
*
* \param device Structure pointer to the Mykonos data structure containing settings
* \param txChannel Desired transmit channel to which to write the DPD model file (Valid ENUM type mykonosTxChannels_t: TX1 or TX2 or TX1_TX2)
* \param modelDataBuffer Pointer to the user buffer containing the history/model data to be loaded to a txChannel
* Valid sizes: 182 bytes for a single model load to either TX1 or TX2.
* 364 bytes for a dual model load to both TX1_TX2, where the TX1 model data will occupy the first 182 bytes
* and TX2 model data will occupy the second 182 bytes.
* \param modelNumberBytes Total buffer size of the user history/model data buffer. Allowed sizes are 182 bytes for TX1 or TX2 and
* 364 bytes for TX1_TX2.
*
*
* \retval MYKONOS_ERR_OK Function completed successfully
* \retval MYKONOS_ERR_RESTDPDMOD_WRONGBUFFERSIZE User suppled modelNumberBytes size is incorrect. TX1 or TX2 = 182, TX1_TX2 = 364
* \retval MYKONOS_ERR_RESTDPDMOD_INVALID_TXCHANNEL User supplied txChannel does not match TX1 or TX2 or TX1_TX2
* \retval MYKONOS_ERR_RESTDPDMOD_ARMERRFLAG ARM returned error for Set ARM Command
*/
mykonosErr_t MYKONOS_restoreDpdModel(mykonosDevice_t *device, mykonosTxChannels_t txChannel, uint8_t *modelDataBuffer, uint32_t modelNumberBytes)

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What would cause the CP to go out of range after calibration?

January 23, 2018, 2:59 pm
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My customer is using an AD9361 transceiver on an FMCOMMS5 eval board.  For various reasons, they’re writing their own driver for the device, but want to initialize the device in essentially the same way as Analog’s driver.

 

So far, their driver is able to complete the calibration of the baseband PLL and the Rx RF charge pump.  Then they try to do the Rx RF VCO calibration, but it never completes, and reg 0x247 bit 7 indicates that the charge pump is overrange.

 

I’ve attached a list of the register writes and reads that they're doing, and the header code they're using.  They defined the functions atd_write and atd_read for writing and reading to the device regs over SPI.  The SPI interface is functioning without any problems as far as they can see. 

 

Do you have any thoughts on what would cause the overrange and the failure of the RF VCO cal?  Any advice would be appreciated.

 

The first two calibrations return the following results.

 

BBPLL VCO cal:                  reg 0x05E = 0x80, so BBPLL VCO cal is good

RF synth CP cal:                 reg 0x244 = 0xA8, so CP cal is done and valid, cal word = 8

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Question for SIGMA-STUDIO for SHARC

January 7, 2018, 11:41 pm
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hello, I'm making custom module

 

i have some question

 

1. trouble is in case of applying my module 

2. so I try address fetch in IC control window, but trouble arises

 

 

to solve this trouble, what do i do?

 

attach my CCES project, .dxe, .dyn, .dll, .ssg, .map, ssh4sh_module_xml.xml files in the debug folder

 

thank you.

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HMC704+HMC586 generate spurious signals at certain frequency

October 9, 2017, 8:32 pm
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Hi,our customer designing HMC704+HMC586+HMC1060  LO circuits,fref=320MHz,fpd=80MHz,LBW=300kHz,Frac B Mode,fout=4-8GHz,fstep= 1kHz.Spurious signals ( -60dBc@ 800kHz offset) can be found at 4019.999MHz,4020.001MHz,4059.999MHz,4060.001MHz,....and so on.We can see the spurious signal neither ref spur nor channel spur/int boundary spur.Can you help to analyze the causes and solutions of spur?Thanks.

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FMCDAQ2 RX Number of Lanes (2 instead 4)

January 22, 2018, 1:03 am
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Hi all,

 

I'm still stucking to find a solution to increase the DAC sample rate.
I use FMCDAQ2 R2017_R1 hdl and No-OS
{pls see Other Post FMCDAQ2 USING DACPLL
FMCDAQ2 ADC Decimation in mode ADC1Ghz-DAC1Ghz
}

 

The issue  seems  simple:
  my configuration  ADC 300Mhz & DAC 600Mhz  (My design is limited to 333 Mhz)
  I want just to increase the DAC sampling (for instance:  1Ghz or 1.2Ghz)
  I use only DDS mode
 
 First Trial: I used DACPLL (AD9144) :
        PLL AD9523 frequency is 4ghz/6    = 666 Mhz  (vco_diff_m1=5)
         ADC clock   666Mhz/2
         DAC clock = 1 Ghz comes from DACPLL that's driven by  reference clock 666Mhz from AD2523    
         DAC FPGA clock = 666 Mhz/4   becomes a problem ?     
        I wanted to ignore TX JESD204B, NO WAY,  because the DDS information comes through
         JESD204B  (the DDS setting in dac_core about phase, frequency, scaling)

 

Second Trial :
           Try   ADC 250Mhz & DAC 1000Mhz, and use only 2 Lanes  for RX JESD204B (to overcome the min. Lane rate)
           instead   m=2, l=4, f= 1  I use  m=2, l=2, f= 2
           it runs  without  error messages, no lock issue,  but no data is captured  (only zeros are captured) any suggestions to check ?
                     
My question:  is it possible to set 2 lanes in the sofware AD9680 Reg 0x570 
[see     ad9680_spi_write(dev, AD9680_REG_JESD204B_QUICK_CONFIG, 0x49);    // m=2, l=2, f= 2
  without changing the Hardware ?
 
 Thank you for your help
            
             Kind Regards

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About REF192 Characteristic graph

January 22, 2018, 1:56 am
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Hi,

Some of my customers are considering using REF 192.

I got a question from him.

#1　Is there a graph of "Load Current vs. REF 192 Dropout Voltage" in REF 192?
　　(Example: Figure 19)

#2　Is there data of Ta = -40 ° C, 125 ° C in the graph of "Load Current vs. REF 192 Dropout Voltage" in REF 192?

 

Best Regards

Yuya

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Trouble with ADP1613 DC/DC

January 18, 2018, 8:46 am
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I have designed a circuit according to the reference circuit found in the ADP1613 datasheet. Attached is my schematics and PCB.

 

Problem is that when i power the circuit, my PSU current-limits even though no load (ive tried bleeder resistors, doesnt work). Even 500mA or current limit will do. This suggests to me that there must be a short circuit somewhere.

 

I have tried everything i can think of; altering compensation loop, added capacitance on soft-start, disconnected frequency pin from VCC to try both frequencies. double checked the component solder joints, double checked schematics vs. reference design. Nothing can bring the device out of its non-working state. I have tried three of them, all with the same problem. My PCB is professionaly manufactured, the soldering is professional.

 

Enable pin works. Adding 10uF on softstart gives a very slow start, but when the device hits a certain voltage, current limiting occurs.

 

This has come to a point where it drived me crazy. Is it something that i am missing?

 

I'll be happy to provide more details...

 

My schematic diagram

 

Reference design

 

 

PCB top side

 

PCB bottom side (there is a battery charger there too, only C20 SS cap is relevant)

 

The board

 

Please help me!

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Where can I find ad9613-250ebz hsc-adc-evalcz default ise program?

January 23, 2018, 5:18 pm
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I was trying to find default program of ad9613-250ebz hsc-adc-evalcz board, but I couldn't find this in ftp.

 

So my question is, can I use ad9643 in ftp for default?

 

if not, where can I find this default program?

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Why SPI clock rate is so low?

January 23, 2018, 5:19 pm
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Hi!

I've a question about the frequency of the SPI clock to AD9371 EVB.

 

By checking the HDL projects downloaded from GitHub - analogdevicesinc/hdl: HDL libraries and projects, in the combination: AD9371 EVB + Altera Arria 10 SX (i.e., SoC)  Dev. Kit, the frequency of the SPI clock generated by the SPI Master is only 128 KHz. This is the same if Arria 10 GX Dev. Kit is used instead.

 

However, according to our waveform measurement on board, in the combination: AD9371 EVB + Xilinx ZC706, the SPI clock rate is around 20 MHz. 

 

Since AD9371's SPI slave supports SPI clock rate up to 50 MHz, we are trying to increase the SPI clock rate on Altera FPGA dev. kit. 

Could you explain why the SPI clock rate is only 128 KHz on Altera FPGA dev. kit? Maybe ADI failed to increase it to higher frequency?

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AD9144/AD9135/AD9136 Chirp signal generation

January 23, 2018, 5:22 pm
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Hello,

Is it possible to generate from 200 MHz to 800 MHz chirp signal with the AD9135 Evaluation board(AD9135 FMC EBZ)?

Or recommend?

I have an Arria 10 Dev. kit.

Thanks.

 

Sincerely

Jun.

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ADRF6720-27 RFoutput problem。

May 6, 2017, 11:56 pm
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MY ADRF6720-27's REFIN is 80M。I want to set 1700MHZ RF frequency。

Here is my config register set：

reg 00 == h0000};
reg 01 == hF6FF};
reg 10 == hF6FF};
reg 20 == h0C26};
reg 21 == h000B};
reg 22 == h2A03};
reg 30 == h0000};
reg 31 == h1101};
reg 32 == h0900};
reg 33 == h0000};
reg 40 == h0010};
reg 42 == h000E};
reg 43 == h0000};
reg 45 == h0000};
reg 49 == h16BD};
reg 02 == h0855};
reg 03 == h0000};
reg 04 == h0000}; 

The PLL of my ADRF6720-27 is locked，and the LOOUT can output 1700MHZ when i set reg22 = 0x2a23.

But the RFOUT of my ADRF6720-27 is not corret，here is my wave。

 

What is the problem?

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Inquiry about AD9371 TDD mode

January 21, 2018, 7:41 pm
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Hi,

My customer is testing the operation of AD9371 TDD mode using AD9371 EVB

The customer found that the tDELAY_TO_TXOUT and the tDELAY_TO_RXOUT were not constant value, according to AD9371 power reset. Is this normal operation of AD9371 ?

Would you please advise why the delay time between TDD path enable signal and actual signal output varies with AD9371 power reset ?

Thanks in advance.

 

 

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ADP160ACBZ-2.75-R7

January 4, 2018, 3:32 am
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Dear Sir/Madam.

I'm using Analog Devices ADP160ACBZ-2.75-R7 LDO in several products.

Recently in a certain product, in two units which succesfully passed all regular tests, I noticed that the current consumption is much too high (50mA instead of 10uA). After a failure invetigation it turned out that the extra current is related to the LDO.

Here are some facts from the failure analysis:

1.The LDO was observed as the cause to the extra current consumption after using a thermal imaging in which the LDO    was the only "HOT SPOT".

2. The system power source is a power supply with voltag range of 3V - 4.2V.

3. The LDO output voltage during the failure was OK (2.76V).

4. During the regular tests (before the failure occured) the circuit worked OK and current consumption was OK too (~10uA).

5. After replacing the LDO in one of the failed units the circuit returned to work as expected with current consumption of    10uA.

6. In the second failed unit the LDO was isoltaed from all other circuitry by taking out series passive components. The LDO    alone was powered by a 4V supply and still consumed around 50mA with the output voltage OK.

7. I measured the input imedance between Vin and GND in a good unit and in a failed unit. In a good unit the impedance is    around 1.6MOHM; in the failed unit the impedance is around 1.6KOHM.

 

The LDO component reel details:

Date Code: 1226

LOT ID: P048713.8

 

Please advice.

Thanks in advance,

Nadav R.

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