Hi. I'm debugging this on my own but decided to ask the experts here to accelerate the effort. I need to do RX1 to TX2 RF loopback on the FMCOMMS3/ZC702 platform. The only thing I've tried so far is adding "adi,tx_channel_swap_enable" line to the device tree. I am not sure if it's supposed to help, and it didn't actually. Is there a way to do such a loopback?

Hello,

I have a pressure sensor, which has a nominal voltage output voltage of 2.0VDC from the sensor and when pressure changes, the signal changes from 2.0VDC +/0.2V DC. So there is a 2.0V DC offset and +/-0.2V if the AC signal on top of the 2.0VDC offset, the signal frequency is 0.1Hz (I have attached a picuture (originalsignal.png)).

I have to amplify just the AC signal on top of the 2.0VDC offset by 5 times but keep the DC offset to 2.0VDC, which i can do it by a differential amplifer by connecting the inverting pin to the signal and non inverting pin to 2.0V reference signal and add a reference voltage of 2.0VDC on the inverting pin to get  (3.0V positive peak and 1.0V negative peak with 2.0VDC offset).

The real issue i have is, my 2V DC offset  on top of AC signal from the sensor may change anywhere between 2V - 1.5V, because of things happening at the reference port of the pressure sensor.

I need to have a fixed 2.0VDC offset on the output signal and just amplify the AC signal (+/0.2V AC signal), no matter where my DC offset on the input signal  (DC offset may change from 2V DC - 1.5V DC). So i has an idea of if i can build a Differential amplifier with reference of 2.0V on the non-inverting pin, so i get the error signal (DC offset error of 0.2VDC when the offset of the sensor signal is 0.8V) and if i know what the error is, i can add it back to the signal source using Opamp Adder. But the problem is that, i will have +/-0.2V AC signal on top of 0.2V DC offset.

I need a constant 0.2VDC error voltage to add it back to the 1.8VDC offset +/- 0.2V AC signal, so that i can have a constant DC offset of 2.0VDC. (I have attached a LTspice simulation file for reference)

I have tried a high pass filter, but the problem is my roll of frequency of 0.1Hz. At this low frequency, there is a huge signal phase shift on the output signal (nature of a filter) and my design cannot afford any signal distortion or phase shift because of the application.

I would really appreciate your help and ideas.

Thanks,

Raj kenika.

Dear All,

This question is somewhat connected to: OpenOCD GDB usage issues 

However, I've decided to start new thread to avoid mixing topics.

The problem is with ADI's BSP (Linux cces-linux-add-in/1.1.0/) gdb and OpenOCD port when working with Linux:

1. The ADI BSP's openocd:

sudo /opt/analog/cces/2.6.0/ARM/openocd/bin/openocd -f interface/ice1000.cfg -f target/adspsc58x.cfg
[sudo] password for lukma:
Open On-Chip Debugger (Analog Devices CCES 2.6.0 OpenOCD 0.9.0-g21dc5ad) 0.9.0
Licensed under GNU GPL v2
Report bugs to <processor.tools.support@analog.com>
adapter speed: 1000 kHz

Do not support "cortex_a dacrfixup [on|off]", which allows writing breakpoints to .text Linux section.

With Linux one can circumvent this issue with deselecting CONFIG_DEBUG_RODATA in Kconfig.

2. When one is able to setup breakpoints another issue shows up:

- Please log into the eval board prompt

- Start openocd (if not already running): sudo /opt/analog/cces/2.6.0/ARM/openocd/bin/openocd -f interface/ice1000.cfg -f target/adspsc58x.cfg

- With GDB: 

(gdb) target remote :3333
Remote debugging using :3333

Program received signal SIGINT, Interrupt.
cpu_v7_do_idle () at arch/arm/mm/proc-v7.S:75
75 ret lr
(gdb)

It seems like we are in a good place (the do_idle function execution is expected)

(gdb) c
Continuing.

And here the serial console hangs - no response from the board. The same behaviour is observed for SSH connection.

I can press Ctrl+C and then I do see the "do_idle" function again. However, the console is unresponsive.

The openocd output is "clear":

Info : accepting 'gdb' connection on tcp/3333
target state: halted
target halted in ARM state due to debug-request, current mode: Supervisor
cpsr: 0x60000093 pc: 0xc00178c8
MMU: enabled, D-Cache: enabled, I-Cache: enabled
semihosting is enabled

Can somebody try to reproduce this issue (sc584 + ezbrd devel board + ice1000)?

My goal is to set breakpoint (HW or SW) on sm_send_message_internal @ protocol.c (ICC driver) to inspect the code at some condition.

Thanks in advance for support,

Łukasz

Greetings!

We are currently trying to configure and debug AD9684 in byte mode. For now we are using 2 DDC (DDC0 and DDC1) which are configured as follows:

Register address     data

x300                       x00

x310                       x40 

x311                       x00  (I and Q inputs from CH A)

x314                       x00

x315                       x04

x330                       x40

x331                       x05  (I and Q inputs from CH B)

x334                       x00

x335                       x04

We are using LVDS byte mode with two converters (reg x568 x15).

But when we apply RF power to CH A input we are seeing zeros (x0000) in I0 and I1 places (according to Figure 9 of datasheet) and identical sine pattern both in Q0 and Q1.

When we apply RF power to CH B input we are still seeing zeros in I0 and I1 and some noise floor both in Q0 and Q1.

We've managed not to see zeros in I0 and I1 only when changed mixer from real to complex for both DDC0 and DDC1, but still it will only react on power on CH A input, but not on CH B input. And all four I0, Q0, I1 and Q1 looks the same, none of them are quadrature to other.

Also we used user patterns to try to understand what's happening and when we writed x05 in register x327 (both I and DDC0 test outputs enabled) we saw our test patterns in all four I0, Q0, I1 and Q1 in out frame. When using DD1 test outputs there is nothing on the output.

When cofiguring input from CH B for DD0 and input from CH A for DDC1 we are seeing the same picture but now for CH B and CH A (or DDC1) is ignored.

I'm including file with register map we are currently using. Could you please lokk into it and explain us what we have to do to see converted data from bath CH A and CH B inputs simultaneously.

Last question: could it be a typo in register address of last register in Table 29 of datasheet (output parallel driver adjust 2)? Could it be not x05B, but x56B? And if yes could the fact we are now writing x00 in wrong register x05B cause troubles?

Best regards,

Igor.

Hello,

I am working on a custom board with ADAU1452. The ADAU1452 should run in selfboot mode. Therefore, I attached a 25AA1024 SPI EEPROM coping the schematic from the evaluation board.

An USBi connects to the ADAU1452 via I2C on the slave port. Communication with SigmaStudio works. I can download a program and can verify that the DSP executes it.

But whatever I try I cannot program the 25AA1024 and therefore, not make the DSP selfbooting.

There is no error message in SigmaStudio. But after programming and cycling power on off the DSP does not execute any program and is set into factory settings.

With a scope I saw some traffic on the SPI Master port when booting but during programming there seems to be no traffic.

Thus, can the SPI EEPROM be programmed if the DSP is connected only via I2C to USBi?

Please note: I can not change the USBi-DSP connection to SPI atm because this would require a hardware redesign.

I attached some screentshots of the configuration in  SigmaStudio. Maybe here something is wrong?

For programming I followed the instructions given in the manual of the ADAU1452 evaluation board.

Raphael

Hi everone, 

can anyone help me to figure out what are the specifications of the microstrip lines using as inductors for matching network?

regards, 

Delaram

Hello

I have a ADC board based on AD9248 65MSPS.

I don't have any anti aliasing filter so I need to put a first-order RC filter at the input of ADC.

in the AD9248 datasheet, the default amount of R and C is 33Ohm and 22pF respectively. 

but when the sampling rate is 65MHz so the RC cut off frequency should be 32.5MHz.

How should I design RC filter for the best accuracy? I have concern about settling time and LSB accuracy

Regards

Hardware - ADRV-DPD1/PCBZ + Xilinx ZC-706 + Interpolator Card.

Issue - I can control the transmitter (see tone on spectrum analyzer, control attenuation, etc) using the AD9375 TES GUI (version 0.3.8).  However when I connect with the AD9375 Embedded DPD Interface GUI (version 3.000), I can only connect to the setup but CANNOT turn on the transmitter.  

Any idea what I am doing wrong?

Thanks

Dusty

Attached is a picture of my Hardware setup...

I am using the axi_i2s_adi (hdl_2017_r1 branch) IP block in a Zynq Ultrascale+ (ZCU102 ES1 Board) Vivado 2017 design and finding there is no back-pressure on the DMA when sending a block of 16 u32 words.

BCLK_DIV_RATE = 3

LRCLK_DIV_RATE = 24

The AXI I2S is configured as shown below.

The waveform shows 16 u32 words sent to the AXI I2S and tready goes low and then high before the I2S FIFO has sent the I2S data.

Same waveform as above just zoomed out to show I2S activity.

The listed Sidekiq SDRs use AD9361, but does Epiq have any SDR solutions which use the AD9371?

Hello. Can I get a circuit of at least one key from the chip ADG774BRZ? Here's how, for example, the circuit chip NE5532. Here the same scheme, where there is transistors, resistors and etc. I can get it for ADG774BRZ?

Hello again,

I have a few questions regarding JESD configuration. I am working with an AD9371 / ZC706 with 2016_r2 versions of HDL and No-OS.

1) I would like to be able to configure the AD9371 so that 2 lanes are being used by the RX0/RX1 channels, 1 lane for a single ORX channel, and 2 lanes for TX0/TX1. The remaining 3 JESD lanes should be disabled. When I try to start this by modifying the ORX Framer configuration to enable only one lane, I get a OrxFramerStatus = 0x20, which seems to me that the link synchronization isn't even starting? I get the same result when trying this with the RX framer configuration. This is the result when I leave the enableManualLaneXbar parameter disabled.

I tried to enable the enableManualLaneXbar parameter, but I'm confused about how the serializerLaneCrossbar parameter is supposed to work. When I enable enableManualLaneXbar for both rxFramer and obsRxFramer, everything works fine when I leave the default serializerLaneCrossbar parameters of 0x08 for RX and 0x40 for ORX. This is where I'm confused. Even if one byte is ignored for each, it appears that 0x08 will map to lane 2 and lane 0, and 0x40 will map to lane 1 and lane 0. This can't be correct, where is my misunderstanding?

When I try to configure the TX0/TX1 channels to 2 lanes instead of 4, I change the deserializerLanesEnabled to 0x03, deserializerLaneCrossbar to 0x08, and enableManualLaneXbar to 1. I get a similar result of DeframerStatus = 0x21.

Are there other modifications necessary to get the JESD configuration I desire, or will this not work for some other reason?

2) Next question is regards to JESD link latency, separate from above. When leaving all framer/deframer parameters at default values, I can drop the K factor down as low as 5, and the link still establishes and everything works fine. I am only testing the RX path and latency. With the no-OS unmodified, I made some minor modifications to the HDL to view test waveforms in ILA only, as well as connected the external user PMOD pins on ZC706 as a means to test latency. When I drop the K factor down from 32 to 5, we only see a gain of 200ns. We expected much more (estimated around 1us). There is no latency gain from decreasing the K factor from 32 to 16. Is there some reason I would not get what we expect from modifying this parameter?

Hi All,

I am using a BF537 with SCLK set to 95 MHz connected to a MT48LC16M16A2P-6A SDRAM. 

I'm trying to debug some strange results in my project and I'm looking at the EBIU settings.

I've used the calculator reference in BfSdcDmcCalculation_Release.xlsx  to determine my `EBIU_SDGCTL` settings based on the attached datasheet for the MT48LC16M16A2P-6A (found here: Micron Technology, Inc. - MT48LC16M16A2P-6A)

My existing code (which I'm trying to debug) sets:

• TRCD to 3
• TRP to 3
• TRAS to 6

Based on the above referenced calculator and the documentation in "ADSP-BF537 Blackfin Processor Hardware Reference", I believe I could set:

• TRCD to 2
• TRP to 2
• TRAS to 4

My understanding is:

1. my existing settings merely take longer to complete some SDRAM operations than if I used the smaller, calculated values
2. this is not an issue to the SDRAM/SDC interaction as long as I'm not concerned about the slight reduction in SDRAM speed performance

Can anyone tell me if my understanding is correct?

Thanks in advance.

-Matt

I am using HMC547ALC3 as RF switch. During power up of my board, the control pins A and B are both at 0V . What would be the state of RFC pin ? If A & B are at 0V and RF power of 10dbm is applied on RFC when A& B are at 0V.

Hi Istvan,

Thanks for your reply .

I have a question about the procedure to change the rate .

I need to modify the parameter configuration in the file axi_jesd_gt  IP or in the block design level: hdl <https://github.com/analogdevicesinc/hdl/tree/hdl_2015_r2>/projects <https://github.com/analogdevicesinc/hdl/tree/hdl_2015_r2/projects>/daq2 <https://github.com/analogdevicesinc/hdl/tree/hdl_2015_r2/projects/daq2>/kcu105 <https://github.com/analogdevicesinc/hdl/tree/hdl_2015_r2/projects/daq2/kcu105>/system_bd.tcl.

     source $ad_hdl_dir/projects/common/kcu105/kcu105_system_bd.tcl

source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl

p_sys_dmafifo  axi_ad9680_fifo 128 16

p_sys_dacfifo  axi_ad9144_fifo 128 10

source ../common/daq2_bd.tcl

set_property -dict  $axi_daq2_gt

set_property -dict  $axi_daq2_gt

set_property -dict  $axi_daq2_gt

At the beginning i think the parameter are overwrited with  system_bd.tcl because the project is created for the first time.

But when i re-launch a new generation bitstream with Vivado GUI, the file  system_bd.tcl is considered or not if i modified it (

set_property -dict  $axi_daq2_gt)?

Thanks for your help,

Bouchaib

Hi Guys,

i use a FMCOMMS5-EZB with an ZC706 Eval Board. Right now, i try to understand the sync process of both ICs via the provided No-OS driver. The process itselfs seems to work, since both AD9361 were initialzed correctly.

Starting from the Vivado reference design and figure out where the Sync_in signal is ported to (Pin W25 of the ZC707 Zynq, and AA9 for the ZC702 Zynq) and how the NO-OS driver is triggering this GPIO. At this point i need your support. I can not follow the driver, how the function exactly knows how to trigger this dedicated PIN. I noticed that you have defined the GPIO_SYNC to 99, but i have no clue what that means (is this a adress to the Pin)

I hope i could explain what i was looking for and you can help me out.

Thanks and regards
Jan

Hi,

I'm working on the KC705 with FMCOMMS5 boards. I'm using the No-os software for AD9361 IC's.

My problem is simple, I can drive one of the two AD9361 but I can't drive the other one.

I can't activate the SPI_ENB_B when i would like to communicate with the AD9361_B.

For information, in config.h i activate :

                                                                 #define CONSOLE_COMMANDS

                                                                 #define XILINX_PLATFORM

                                                                 #define FMCOMMS5

But i always transmit command to the AD9361_A. I can't understand that.

How can I activate the SPI_ENB_B ?

Thank you in advance.

I am attempting to run the reference design for the AD-FMCADC5-EBZ FMC Board on a Xilinx VC707 carrier. After some stalled attempts I have discovered that (as of July 5th, 2016) the github/hdl/ 'dev' branch appears to have the latest Vivado v2015.4.2 release design, and the github/no-OS/ '2016_R1' branch has the most up-to-date microblaze code. (the current no-OS 'dev' branch will not compile under SDK v2015.4.2)

Unfortunately, I am finding that the FPGA/SW combination above seems to be failing with the following errors in the UART console window:

SYSREF Calibration Failed!!

ADC Core Initialized (156 MHz).

ADC Core Initialized (156 MHz).

ADC PN Status: 0, 1, 0x02!

Does anyone have any advise on what is going wrong?

Regards

Arnold

hi,

    i am using zedboard along with fmcomms1 board and running on no-os driver , i wanted to know what is the sampling rate range for both adc and dac in fmcomss1 and is it possible to get a sampling rate of 1 mhz as i need it in my application,thanks

regards

rahul

Hi,

we are now proceeding with an E2E LTE transmission using two FMCOMMS5 and two ZC706 Xilinx boards. We have achieved to transmit and receive a sequence of 8192 samples of the LTE waveform and we would like now to have a real-time LTE baseband aggregated on the processors that produce LTE waveforms, i.e. LTE frames continuously per 10ms, where one subframe is 1ms.

A part of this discussion was taken place here: https://ez.analog.com/message/257692?et=watches.email.thread#comment-257692 where you directed us to a multiple transfer solution provided by you for the adc_core (Rx side) only.

The first question is whether this task can be completed much easier, for example:

- to use a for loop to transmit the LTE I and Q samples per subframe (through the Xil_Out32) in dac_core 

- to use a for loop to call adc_capture and then to invalidate the cache (through the Xil_DCacheInvalidateRange) in main.c so that we can receive the subframes from the memory continuously, emptying the memory per loop and so on.

Please advice, if there is any easier way to provide streaming of the data from one machine to another.

Fotis