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How to write UART ON BF609
Hi，everyone Using CrossCore Embedded Studio write a serial program，Using CrossCore Embedded Studio packaging good function, but debugging failure when set the baud...
View ArticleQueries about ADF4158/9's Maximum TXDATA Rate
Dear Supporters, I have read the datasheet of ADF4158/9 PLL Synthesizer IC.The Synthesizer is capable of FSK and PSK modulations as wel. In order to decide for this device, for my new design, I must...
View ArticleADFMCOMMS-1 ZedBoard Reference Design DMA Configuration
Hi,We are currently working on the reference design for ADFMCOMMS-1 ZedBoard. It seems that the DMA for ADC is configured in scatter-gather (SG) mode and polling or interrupt are not used in order to...
View ArticleAD5933 source code for AVR problem
HI, I am trying to connect AD5933 with AVR microcontroller. My circuit is with AFE based on CN0217 with two ADG706 for calibration and feedback resistive networks. I have problem to measure unknown...
View ArticleAD7763 Filter Download Question
Hi, I am having problems downloading filters to the AD7763. I have tried the example in the datasheet (in Table 16) so that I know the checksum is correct but I am not getting the FILTER_OK or DL_OK...
View ArticleAbout ADG3241 Level shift IC
Hi there,I have a simple question about ADG3241, level shift IC.http://www.analog.com/static/imported-files/data_sheets/ADG3241.pdfI want the levelshift from 3.3V to 1.8V/2.5V.I checked out the...
View ArticleAD7176-2 REFOUT while using an external reference
Hi, I am designing a board to read +-10V signals using the AD7176-2. I want to drive it by a AD8475 as on page 24, but to be able to use a single 5V supply, I will use an ADR444 supplying 4.096V as an...
View ArticleMax data rate?
According to the data sheet, the max data rate is 3.906Khz, but when I play with the Excel sheet, the max data rate is 7.8125Khz (0 for SF,AF,Notch2, Revg2 and Chop) Did I miss anything?
View ArticleSDH device driver examples
Hello!Where I can find examples for BF548 SDH device driver(adi_sdh)? I've found only "raw" SD in VisualDSP examples.
View ArticleAD8333 double-ended output to single ended
Hello everyone, I am trying to demodulate a 5MHz signal using the AD8333 and need to have a low pass filter after the output, which means I will need a single ended output. On the datasheet they just...
View ArticleAD5292 SDO Readback mode
Hello, I have a circuit containing two digital potentiometers (AD5292) that are part of a voltage regulator circuit. I'm trying to send the wiper words back to the microcontroller via the SDO pin in...
View ArticleFM-Comms2/ZC706 GUI question
We have a FM-Comms2 and a ZC706 eval board. On the GUI for the ZC706 board there is a Tx freq input on the GUI that sets Tx1 output. How do I set Tx2 output? My understanding is the two Tx paths are...
View ArticleQuestion about ADV7612 connect with DM368?
We connect ADV7162 with DM368 vpif port, Connection: vpif0<--->LLC, Y0-Y7 <---->P16-P23, C0-C7<--->P4-P17,HS<--->HS,VS<---->VS. Input: 720*576 50HZ(PAL mode) from...
View ArticleAD-FMCOMMS1-EBZ Board no longer responding
Engineer Zone: AD-FMCOMMS1-EBZ Board that was responding yesterday not responding.1) HDL Reference design for ML605 and linux kernel that was working yesterday is no longer working2) It boots FMC...
View ArticleFIR Accelerator consuming core cycles in ADSP-21488
Hello Although I cannot find any documented reference to it, I am finding that the FIR Accelerator is consuming some core cycles. It's not much, but enough to prevent some demanding audio processing...
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ADV7403 CVBS-525 signal shows too much jitter
We have a problem using the ADV7403 to A/D-convert a CVBS-525 signal. The Hsync output produces a jitter of up to 120ns which the following genlock (LMH1982) doesn't allow to lock. The jitter rises...
View ArticleProgramming multiple ADuC7xxx Evaluation Boards
Hi all, My group is using two separate ADuC7026 evaluation boards for a project. Each board is running separate code and hardware. I am attempting to program both using the same laptop, currently...
View ArticleADV7842 ： TMDS_LCK_A_ST(TMDS_LCK_A_RAW) generate logic
Hi all.We use ADV7842 for HDMI input.We check the HDMI ch.A input by TMDS_LCK_A_ST interrupt.1st TMDS_LCK_A_ST interrupt arrived when TMDS_LCK_A_RAW(IO map 0x6B[5]) is 0 with TMDS_PLL_LOCKED(HDMI map...
View ArticleADAU1361, PLL and Fs=32kHz
Hi My MCLK=27MHz. I am need to get Fs=32kHz(frequency on pin LRCLK, p.43 Figure 57..59). That mean - it’s need PLL in fraction mode. DataSheet state:1. The PLL output clock rate is always 1024 × Fs...
View ArticleADV7511 PLL not locking
We have designed a board using an FPGA to drive video to an ADV7511. We used the Xilinx ZC702 Evaluation platform schematics as a reference. Our ZC702 eval board works, but when we run the same...
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