I have the boards Avnet ZedBoard and AD FMCOMMS1. From FPGA I give 100Mhz CLK signal to the AD9548, which generate 122.88Mhz clock to the AD9523-1. I need 98.304Mhz CLK signal for ADC from AD9523-1. Required CLK signal for the ADC is formed by AD9523-1, but both PLL1 and PLL2 is not lock! However lock PLL2 sometimes is set on few second, but always disappear. What I do wrong?
Here my register settings. After all register write I do calibrate VCO and sync outputs.
0x000=0x00
0x004=0x00
0x010=0x00
0x011=0x00
0x012=0x00
0x013=0x00
0x014=0x00
0x016=0x01
0x017=0x00
0x018=0x0C
0x019=0x03
0x01A=0x52
0x01B=0x04
0x01C=0x8C
0x01D=0x04
0x0F0=0x78
0x0F1=0x03
0x0F2=0x23
0x0F3=0x00
0x0F4=0x00
0x0F5=0x19
0x0F6=0x00
0x0F7=0x01
0x190=0x02
0x191=0x00
0x192=0x00
0x193=0x20
0x194=0x00
0x195=0x00
0x196=0x03
0x197=0x09
0x198=0x00
0x199=0x20
0x19A=0x00
0x19B=0x00
0x19C=0x20
0x19D=0x00
0x19E=0x00
0x19F=0x20
0x1A0=0x00
0x1A1=0x00
0x1A2=0x20
0x1A3=0x00
0x1A4=0x00
0x1A5=0x20
0x1A6=0x00
0x1A7=0x00
0x1A8=0x20
0x1A9=0x00
0x1AA=0x00
0x1AB=0x20
0x1AC=0x00
0x1AD=0x00
0x1AE=0x20
0x1AF=0x00
0x1B0=0x00
0x1B1=0x20
0x1B2=0x00
0x1B3=0x00
0x1B4=0x20
0x1B5=0x00
0x1B6=0x00
0x1B7=0x20
0x1B8=0x00
0x1B9=0x00
0x1BA=0x00
0x1BB=0x01
0x230=0x02
0x231=0x03
0x232=0x00
0x233=0x00
