BF607 SMC Timing

Hi,

I'm confused about processor's signal AMSx (SMC chip select)

I initialise processor (CLKIN = 32M) as

<register-reset-definitions>

  <!-- Init clocks( CCLK = 496 Mhz, SCLK = 250Mhz, SCLK0 = 125Mhz -->

  <register name="CGU0_CLKOUTSEL" reset-value="3" core="Common" />

  <register name="CGU0_DIV" reset-value="0x01024241" core="Common" />

  <register name="CGU0_CTL" reset-value="0x00001f01" core="Common" />

then, in the code, SMC is initialized as:

now I'm expecting that, when executing a read in AMS1 domain, the cycle lenght is 3 cycles of (1/124MHz) = 8.065nS*3 = rroughly 25nS.

Instead I measure roughly 380nS, which is an enormous time.

Where I'm wrong?

Thanks...